The mainstream SSOP-8 package is JEDEC MO-187 variation DA: eight gull-wing leads on 0.65 mm pitch, a 2.80 mm body width, a 4.00 mm lead span and a 1.30 mm maximum height. At least three physically different outlines ship under that name, and their lead spans differ by 2.4 mm. Below are the dimension table, both candidate land patterns, the thermal numbers, and the check that stops you buying the wrong one.
Key takeaways
- The common SSOP-8 (TI DCT, Diodes SSOP-8) is MO-187 variation DA: 0.65 mm pitch, 4.00 mm lead span, 2.80 mm body width, 1.30 mm max height.
- ROHM’s SSOP-B8 also runs 0.65 mm pitch, but its lead span is 6.40 mm. Same name, no shared footprint.
- MSOP-8 sits under the same JEDEC registration at variation AA, with a 4.90 mm lead span and 1.10 mm max height.
- Renesas sells an 8-pin SSOP photocoupler rated 2.5 kV r.m.s. with 4.0 mm creepage and 4.0 mm clearance. Different package, different job.
- TI measures RθJA at 220 °C/W for the SSOP-8, only 7 °C/W better than the physically smaller VSSOP-8.
- DigiKey files these parts as “8-LSSOP, 8-MSOP (0.110 in, 2.80 mm Width)”, so an SSOP-8 keyword search returns almost nothing.
[IMAGE 1: top and side view of an 8-lead SSOP with lead span, body width and 0.65 mm pitch dimensioned | alt: “SSOP-8 package dimensions showing 0.65 mm pitch, 2.80 mm body width and 4.00 mm lead span”]
What an SSOP-8 package is
An SSOP-8 package is an 8-lead shrink small outline package: a plastic body with four gull-wing leads per side on 0.65 mm pitch, a 2.80 mm body width, a 2.95 mm body length and a maximum seated height of 1.30 mm. Texas Instruments and Diodes Incorporated both build it to JEDEC MO-187 variation DA.
The JEDEC title explains the naming mess. MO-187 is registered as a Plastic Low/Thin/Very Thin Shrink Small Outline Package, 0.65 and 0.50 pitch. Every part built to it has a legitimate claim to an SSOP name, which is why the same registration produces packages labelled SSOP, MSOP and VSSOP depending on who is selling them.
Two neighbouring registrations matter for context. MO-150 covers the 5.3 mm body, 0.65 mm pitch SSOP family and does list an 8-lead member, although it is rare in current catalogues. MO-137, the 0.150 in body SSOP, has no 8-lead variant at all: its smallest is 14 leads. If a supplier offers you a “150-mil SSOP-8”, ask for the drawing.
Three different packages ship as “SSOP-8”
| Designation | Vendor | Pitch | Body width | Lead span | Max height | Reference |
| SSOP-8 (DCT) | Texas Instruments | 0.65 mm | 2.70–2.90 mm | 3.75–4.25 mm | 1.30 mm | MO-187 var. DA, JESD30 code R-PDSO-G8 |
| SSOP-8 | Diodes Incorporated | 0.65 mm | 2.70–2.90 mm | 3.75–4.25 mm | 1.30 mm | Package sheet dated 2021-07-22 |
| SSOP-B8 | ROHM | 0.65 mm | 3.00 mm | 6.40 mm | 1.25–1.35 mm | 2,500 pieces per reel |
| 8-pin SSOP (photocoupler) | Renesas | Isolation package | — | — | — | 2.5 kV r.m.s., 4.0 mm creepage, 4.0 mm clearance |
Read the lead span column twice. A ROHM SSOP-B8 reaches 6.40 mm across its leads; a TI DCT reaches 4.00 mm. Drop one into the other’s land pattern and the leads land 1.2 mm outside the pads on each side. There is no partial fit and no rework path.
ROHM’s own catalogue makes the point again internally. Its SSOP-B8 measures 6.40 mm by 3.00 mm at 1.35 mm tall, while its TSSOP-B8 is the same 6.40 mm by 3.00 mm at 1.20 mm and its MSOP8 is 4.00 mm by 2.90 mm at 0.90 mm. In ROHM’s naming, SSOP and TSSOP share a footprint and differ only in height. In TI’s naming they do not.
The Renesas part deserves its own line. Its 8-pin SSOP photocouplers, including the PS8802, PS9821 and PS9851, carry 4.0 mm of outer creepage, 4.0 mm of clearance and a 0.2 mm insulator between input and output. Those numbers exist because the package is a safety barrier. Nothing about its footprint transfers to a logic SSOP-8.
SSOP-8 dimensions
Values below are MO-187 variation DA, taken from the Diodes SSOP-8 package outline and cross-checked against the DCT drawing in TI’s Little Logic application report SCEA029, drawing number 4188781/C.
| Symbol | Parameter | Min | Typ | Max | Unit |
| e | Lead pitch | — | 0.65 | — | mm |
| E | Overall lead span | 3.75 | 4.00 | 4.25 | mm |
| E1 | Body width | 2.70 | 2.80 | 2.90 | mm |
| D | Body length | 2.75 | 2.95 | 3.15 | mm |
| A | Overall height | — | — | 1.30 | mm |
| A1 | Standoff | 0.05 | — | 0.15 | mm |
| A2 | Body thickness | 0.95 | 1.05 | 1.20 | mm |
| b | Lead width | 0.15 | 0.225 | 0.30 | mm |
| c | Lead thickness | 0.08 | — | 0.23 | mm |
| L | Foot length | 0.20 | 0.40 | 0.60 | mm |
| θ | Lead angle | 0 | 4 | 8 | degrees |
One discrepancy worth knowing. Diodes specifies standoff A1 as 0.05 mm to 0.15 mm; TI’s DCT drawing shows 0.00 mm to 0.10 mm for the same variation. If your stencil design assumes guaranteed standoff, use the number from the datasheet in front of you rather than a library value.
Maximum outline area is 4.25 mm by 3.15 mm, or 13.4 mm². For reference, an SOIC-8 occupies roughly 30 mm², so the SSOP-8 saves more than half the board area of the part it usually replaces.
SSOP-8 vs MSOP-8, VSSOP-8 and TSSOP-8
| Attribute | SSOP-8 (TI DCT) | MSOP-8 (MO-187 AA) | VSSOP-8 (TI DCU) | TSSOP-8 (ROHM TSSOP-B8) |
| Pitch | 0.65 mm | 0.65 mm | 0.5 mm | 0.65 mm |
| Body width | 2.80 mm | 3.00 mm | 2.30 mm | 3.00 mm |
| Lead span | 4.00 mm | 4.90 mm | 3.20 mm nominal | 6.40 mm |
| Max height | 1.30 mm | 1.10 mm | 1.10 mm | 1.20 mm |
| JEDEC | MO-187 var. DA | MO-187 var. AA | MO-187 (0.5 mm) | Vendor outline |
| RθJA | 220 °C/W | Part dependent | 227 °C/W | Part dependent |
| Hand rework | Practical | Practical | Difficult | Practical |
Two conclusions follow.
MSOP-8 and SSOP-8 are the same registration at different variations. Variation AA gives a 3.00 mm square body on a 4.90 mm lead span at 1.10 mm tall; variation DA gives a 2.80 mm wide body on a 4.00 mm span at 1.30 mm tall. The 0.9 mm difference in lead span is fatal to a shared footprint even though both are 0.65 mm pitch.
Shrinking the package buys almost nothing thermally. TI’s SN74LVC2G74 datasheet, revision Q, reports RθJA of 220 °C/W for the DCT SSOP-8 and 227 °C/W for the DCU VSSOP-8, both per JESD51-7. The same die in the YZP chip-scale ball grid array measures 102 °C/W. If thermal performance is driving the package choice on an 8-pin part, the leaded options are within noise of each other and the die-scale package is the only real answer.
SSOP-8 pinout
Pin numbering follows the universal small-outline rule. Pin 1 sits at the upper left in the top view, identified by a moulded dot or the chamfered index area. Pins 1 to 4 run down the left side, pin 5 sits opposite pin 4, and pins 5 to 8 run back up the right side. Pin 1 and pin 8 face each other across the body.
Function assignment is device-specific. Two real examples:
- TI PCA9306, an I²C voltage-level translator: pin 1 EN, pin 2 VREF1, pin 3 SCL1, pin 4 SDA1, pin 5 SDA2, pin 6 SCL2, pin 7 VREF2, pin 8 GND.
- ROHM LM4565FV, a dual op-amp in SSOP-B8: pin 1 OUT1, pin 2 −IN1, pin 3 +IN1, pin 4 VEE, pin 5 +IN2, pin 6 −IN2, pin 7 OUT2, pin 8 VCC. This is the classic dual-op-amp map inherited from DIP-8.
Here is the trap that costs boards. TI publishes a single pinout drawing headed “DCT or DCU package (top view)” for the PCA9306, because the electrical pinout is identical across both. The footprints are not: DCT is 0.65 mm pitch on a 4.00 mm span, DCU is 0.5 mm pitch on a 2.30 mm body. A shared pinout diagram is not a shared land pattern, and the datasheet will not warn you.
[IMAGE 2: SSOP-8 top view with pin 1 index area and numbering direction annotated | alt: “SSOP-8 pinout numbering with pin 1 index area, pins 1 to 4 and 5 to 8”]
SSOP-8 footprint
You have two defensible patterns. Diodes publishes a recommended layout on its package sheet; IPC-7351B produces a slightly different one. Both are shown so you can pick with your eyes open.
Vendor pattern (Diodes, referenced to IPC-7351A): pad 0.400 mm wide by 1.100 mm long, on 0.650 mm pitch, with an outer pad extent of 4.900 mm and a pad row length of 2.350 mm. Diodes adds a process note: for wave soldering, add 0.2 mm to the outer extent.
Computed pattern (IPC-7351B, Nominal density). SSOP-8 falls under IPC-7353, gullwing leads on two sides. Using Level B fillet goals of Jt = 0.35 mm, Jh = 0.35 mm and Js = 0.03 mm, with 0.05 mm fabrication allowance and 0.05 mm placement accuracy:
Lead span L runs 3.75 mm to 4.25 mm, so Ltol = 0.50 mm. Inner lead separation S runs from 3.75 − 2(0.60) = 2.55 mm to 4.25 − 2(0.20) = 3.85 mm, so Stol = 1.30 mm. Lead width W runs 0.15 mm to 0.30 mm, so Wtol = 0.15 mm.
Outer pad extent
Z = Lmin + 2Jt + √(Ltol² + F² + P²)
= 3.75 + 0.70 + 0.505 = 4.96 mm
Inner pad gap
G = Smax − 2Jh − √(Stol² + F² + P²)
= 3.85 − 0.70 − 1.302 = 1.85 mm
Pad width
X = Wmin + 2Js + √(Wtol² + F² + P²)
= 0.15 + 0.06 + 0.166 = 0.38 mm
| Parameter | Diodes recommended | IPC-7351B Level B |
| Pad size | 0.40 mm × 1.10 mm | 0.38 mm × 1.55 mm |
| Outer extent (Z) | 4.90 mm | 4.96 mm |
| Inner gap (G) | 2.70 mm | 1.85 mm |
| Row centreline | 3.80 mm | 3.40 mm |
| Pad-to-pad clearance | 0.25 mm | 0.27 mm |
| Copper area, 8 pads | 3.52 mm² | 4.71 mm² |
The outer extents agree within 0.06 mm. The difference is entirely inboard: the IPC pattern pushes each pad 0.85 mm further under the body to build a larger heel fillet, at the cost of 34% more copper and less visibility for AOI. Diodes’ shorter pad keeps the joint where a camera and an operator can see it.
Pick the vendor pattern for hand-assembled prototypes and anything you expect to rework. Pick the IPC pattern for high-volume reflow where joint fatigue life matters more than inspection access. KiCad’s official Package_SO library ships SSOP-8_2.95×2.8mm_P0.65mm, which matches this outline; there is no need to draw one from scratch.
Reflow, stencil and rework
At 0.65 mm pitch with a 0.38 mm to 0.40 mm pad, a 0.12 mm stencil foil at 1:1 aperture gives an area ratio comfortably above 0.66. Chamfer the aperture corners rather than trimming width. Narrowing apertures on a package this short produces starved heels at the corner leads, which is where coplanarity is worst.
Standoff is 0.05 mm to 0.15 mm on the Diodes drawing. That is enough for solder mask and a tented via, and nothing else. Keep test pads and passives clear of the body outline.
The 1.30 mm body height makes this an easy hot-air rework target. A 4.00 mm lead span means the whole part fits under a small nozzle, and the joints stay visible from the side throughout.
Moisture sensitivity is a device property, not a package property. ROHM ships SSOP-B8 parts in MSL 1 dry pack; other vendors ship the same outline at MSL 3. Read the bag label rather than the package family page.
Sourcing
Distributor taxonomy is where SSOP-8 searches fail. DigiKey classifies TI’s DCT parts as 8-LSSOP, 8-MSOP (0.110 in, 2.80 mm Width) with a supplier device package of SM8. Searching “SSOP-8” on that site returns adapters and little else. Search 8-LSSOP, or filter on the 2.80 mm width, and the parts appear.
A live price check on the SN74LVC2G74DCTR, a representative SSOP-8 logic part: active status, 10,501 pieces in distributor stock, $0.65 at quantity 1, $0.31518 at 1,000, and $0.29356 on a 3,000-piece reel, with a 6-week factory lead time. Standard packing is a reel of 3,000 for TI’s DCT and 2,500 for ROHM’s SSOP-B8.
Availability across the family is uneven. Several DCT SKUs, including the SN74LVC2G157DCTRG4 and SN74LVC2G66DCTR, are flagged as no longer stocked at RS while remaining orderable elsewhere. Check two authorised distributors before committing, and note that where a part exists in DCT, DCU, X2SON and DSBGA, as the PCA9306 does, the SSOP-8 version is usually the one with the longest lead time and the widest board footprint.
Five ways an SSOP-8 design goes wrong
- Assuming one SSOP-8 exists. ROHM’s SSOP-B8 and TI’s DCT differ by 2.4 mm of lead span. Match the drawing, not the name.
- Reusing an MSOP-8 footprint. Same JEDEC registration, different variation, 0.9 mm more lead span. The pads will not reach.
- Trusting a shared pinout diagram. TI draws DCT and DCU together. The pinouts match; the footprints do not.
- Searching the distributor for “SSOP-8”. The parts are filed under 8-LSSOP. Engineers conclude the package is dead when it is stocked in five figures.
- Choosing SSOP-8 for thermal reasons. At 220 °C/W it is 7 °C/W better than a smaller VSSOP-8 and less than half as good as the chip-scale option.
SSOP-8 FAQ
What is the pitch of an SSOP-8 package?
0.65 mm across every mainstream variant, including TI’s DCT, the Diodes SSOP-8 and ROHM’s SSOP-B8. Pitch alone does not identify the package. Lead span separates them: 4.00 mm for the MO-187 variation DA outline against 6.40 mm for ROHM’s SSOP-B8. Always confirm span before selecting a footprint.
Is SSOP-8 the same as MSOP-8?
They share JEDEC registration MO-187 but sit at different variations. SSOP-8 is variation DA, with a 2.80 mm body width, a 4.00 mm lead span and 1.30 mm maximum height. MSOP-8 is variation AA, with a 3.00 mm body, a 4.90 mm lead span and 1.10 mm maximum height. The footprints are not interchangeable.
What are SSOP-8 dimensions in millimetres?
Lead span 3.75 mm to 4.25 mm, body width 2.70 mm to 2.90 mm, body length 2.75 mm to 3.15 mm, overall height 1.30 mm maximum, standoff 0.05 mm to 0.15 mm, lead pitch 0.65 mm, lead width 0.15 mm to 0.30 mm, foot length 0.20 mm to 0.60 mm. Maximum outline area is 13.4 mm².
Can SSOP-8 and TSSOP-8 use the same footprint?
It depends on the vendor. In ROHM’s catalogue, SSOP-B8 and TSSOP-B8 share a 6.40 mm span and a 3.00 mm body, so they do share a land pattern and differ only in height. In TI’s naming they do not: the SSOP-8 span is 4.00 mm. Check both drawings.
Why can’t I find SSOP-8 parts on DigiKey?
DigiKey files this outline as “8-LSSOP, 8-MSOP (0.110 in, 2.80 mm Width)” with a supplier device package of SM8, so an SSOP-8 keyword search misses almost everything. Search 8-LSSOP or filter by the 2.80 mm body width instead. Mouser and LCSC do accept SSOP-8 directly.
Choosing SSOP-8
Specify SSOP-8 when you want SOIC-8 handling characteristics in half the board area, when the assembly line is 0.65 mm capable but you would rather not commit to 0.5 mm, and when the part you need ships in it. On those terms the package is a good default for 8-pin logic, translators and small analog.
Move to VSSOP-8 or a chip-scale package only when board area is genuinely the constraint, and accept that hand rework gets materially harder. Move up to SOIC-8 when the board is wave-soldered or field-serviceable.
Whichever you choose, run this check before you place a footprint: read the lead span off the drawing, compare it against the pad row extent in your library, and confirm the distributor’s package field matches. Three numbers, two minutes, and it removes the only failure mode this package reliably produces.
[IMAGE 3: side-by-side land patterns for SSOP-8, vendor recommended and IPC-7351B nominal | alt: “SSOP-8 footprint comparison showing 0.40 by 1.10 mm vendor pads against 0.38 by 1.55 mm IPC-7351B pads”]
Internal links to add
- [INTERNAL LINK: SSOP-56 package → SSOP dimensions and footprint at high pin count]
- [INTERNAL LINK: SOIC-16 package → SOIC family pitch and body reference]
- [INTERNAL LINK: MSOP vs VSSOP naming → decoding JEDEC MO-187 variations]
- [INTERNAL LINK: IPC-7351 land pattern density levels → choosing Most, Nominal or Least]
- [INTERNAL LINK: stencil aperture design → area ratio rules for fine-pitch packages]
