A standard SOIC-8 measures 4.80 mm to 5.00 mm long, 3.80 mm to 4.00 mm across the molded body, and 1.35 mm to 1.75 mm tall, with a 5.80 mm to 6.20 mm lead span on 1.27 mm pitch. Those are the JEDEC MS-012-AA limits. Two other packages also ship as SOIC-8, and both are larger. Below are the numbers, the land pattern, and what the size buys you.
Key takeaways
- Lead span, not body width, is the dimension your footprint has to match: 5.80 mm to 6.20 mm on the narrow SOIC-8.
- Height is capped at 1.75 mm, with 0.10 mm to 0.25 mm of standoff under the body.
- Three vendors converge on a 7.0 mm overall land length with roughly 1.5 mm pads, but disagree on pad width: 0.60 mm, 0.72 mm and 0.76 mm.
- A 210 mil SOIC-8 and a 7.5 mm wide-body SOIC-8 both exist. The wide one spans 11.5 mm.
- Bigger runs cooler. The 5.3 mm body reaches 95 °C/W junction-to-ambient against 147.8 °C/W for the 3.9 mm one.
[IMAGE 1: annotated SOIC-8 top view and side view with D, E, E1, A, A1, b, c and e callouts | alt: “SOIC-8 dimensions diagram showing 4.90 mm body length, 3.90 mm body width and 6.00 mm lead span”]
SOIC-8 dimensions, narrow body
These are the Analog Devices R-8 drawing limits, which state compliance with JEDEC MS-012-AA. The Texas Instruments D0008A drawing, revision 4214825/C, references the same registration and agrees on every row within 0.04 mm.
| Dimension | Symbol | Min (mm) | Max (mm) | Note |
| Molded body length | D | 4.80 | 5.00 | Excludes mold flash |
| Molded body width | E1 | 3.80 | 4.00 | Excludes interlead flash |
| Lead span, tip to tip | E | 5.80 | 6.20 | Drives the land pattern |
| Overall height | A | 1.35 | 1.75 | Seated |
| Standoff | A1 | 0.10 | 0.25 | Body to board |
| Lead pitch | e | — | 1.27 BSC | Basic dimension |
| Foot length | L | 0.40 | 1.27 | Contact length |
| Lead width | b | 0.31 | 0.51 | At the foot |
| Lead thickness | c | 0.17 | 0.25 | TI allows 0.13 min |
| Corner chamfer | h | 0.25 | 0.50 | At 45° |
| Foot angle | — | 0° | 8° | |
| Coplanarity | — | — | 0.10 | Across all eight feet |
| Mold flash allowance | — | — | 0.15 | Per side, TI drawing |
Design to the lead span, never to the body. The 3.80 mm to 4.00 mm body width tells you nothing about where the feet land. The 5.80 mm to 6.20 mm span does, and the 0.40 mm spread in that span is what your pad length has to absorb.
Three different packages ship as SOIC-8
The name covers at least three outlines. JEDEC MS-012 defines a 3.9 mm body; MS-013 defines a 7.50 mm one; JEITA, formerly EIAJ, defines a 5.3 mm Type II body that distributors often still list as SOIC.
| Parameter | Narrow (TI D) | 210 mil / EIAJ | Wide (TI DWV) |
| Body length (mm) | 4.81 to 5.00 | 5.00 to 5.60 | 5.75 to 5.95 |
| Body width (mm) | 3.81 to 3.98 | 5.00 to 5.60 | 7.4 to 7.6 |
| Lead span (mm) | 5.80 to 6.19 | 7.40 to 8.20 | 11.5 typ |
| Max height (mm) | 1.75 | 2.20 | 2.80 |
| Lead pitch (mm) | 1.27 | 1.27 | 1.27 |
| Lead width (mm) | 0.31 to 0.51 | 0.35 to 0.51 | 0.31 to 0.51 |
| Max envelope area (mm²) | ≈ 31 | ≈ 46 | ≈ 68 |
| Typical use | Op-amps, logic, sensors | Serial flash, optocouplers | Reinforced isolators |
The wide variant exists for creepage, not for die size. TI specifies 9.1 mm nominal clearance and creepage on the DWV land pattern, which is why an eight-pin isolator occupies more than twice the board area of an eight-pin op-amp.
Check the lead span before reusing a footprint. A 210 mil part dropped onto a narrow SOIC-8 pattern misses its pads by more than a millimetre per side.
[IMAGE 2: three 8-lead outlines drawn to scale, 3.9 mm, 5.3 mm and 7.5 mm bodies | alt: “SOIC-8 dimensions compared across narrow body, 210 mil and wide body variants”]
The SOIC-8 land pattern three vendors agree on
Published footprints from Texas Instruments, onsemi and International Rectifier were compared. All three sit inside 7.0 mm of overall land length and use pads near 1.5 mm long. They disagree only on width.
| Source | Pad length (mm) | Pad width (mm) | Spacing (mm) | Width as % of pitch |
| TI D0008A example layout | 1.55 | 0.60 | 5.40 center to center | 47 % |
| onsemi case 751AZ footprint | 1.52 | 0.76 | 7.00 outer to outer | 60 % |
| International Rectifier SO-8 | Not stated | 0.72 | 6.46 outer to outer | 57 % |
The TI and onsemi numbers describe the same pattern from two directions. Adding TI’s 5.40 mm center spacing to one 1.55 mm pad gives 6.95 mm outer to outer, within 0.05 mm of onsemi’s 7.00 mm. Build either and the part solders.
Pad width is a real choice. At 0.60 mm you get 0.67 mm of copper-free gap between adjacent pads; at 0.76 mm that falls to 0.51 mm. The wider pad grows the side fillet and the joint area, and it narrows the bridging margin. Use 0.60 mm on a dense board with a fine stencil, 0.76 mm where hand rework is likely.
Stencil thickness is 0.125 mm on the TI paste example for this package, with apertures matching the copper one for one.
[IMAGE 3: SOIC-8 land pattern with pad length, pad width and center-to-center callouts | alt: “SOIC-8 land pattern with 1.55 mm by 0.60 mm pads on 1.27 mm pitch and 5.40 mm center spacing”]
Height, standoff and coplanarity
The 1.75 mm height cap is the number that decides whether a SOIC-8 fits under a shield can or inside a card slot. Add board thickness and the standoff sits between 0.10 mm and 0.25 mm above the copper, which is what lets flux escape and lets a cleaning process reach underneath.
Coplanarity is specified at 0.10 mm across all eight feet on the Analog Devices drawing. A part outside that will place fine and reflow with one or two open joints, and the failure passes electrical test intermittently. It is worth checking on tube-shipped parts that have been handled.
What the dimensions buy you thermally
One device, the TL072, is offered in four 8-pin packages. Its data sheet lists thermal resistance for each on a common test board, which makes the size-to-heat relationship measurable rather than assumed.
| 8-pin package | RθJA (°C/W) | RθJC top (°C/W) | ψJT (°C/W) |
| P, PDIP | 85 | — | — |
| PS, SO 5.3 mm body | 95 | — | — |
| D, SOIC narrow 3.9 mm | 147.8 | 88.2 | 36.8 |
| DDF, SOT-23-THIN | 181.5 | 112.5 | 17.2 |
| PW, TSSOP 4.4 mm | 200.3 | 89.4 | 22.2 |
The ranking tracks lead frame size, not pin count. The 5.3 mm SO body moves heat 36 % better than the 3.9 mm SOIC-8, and the TSSOP is 35 % worse. Shrinking the outline costs power budget every time.
Worked example. Maximum dissipation is (TJ max − TA) ÷ RθJA. The TL072 junction limit is 150 °C. At a 70 °C ambient, a SOIC-8 allows 80 ÷ 147.8 = 0.54 W. The same die in TSSOP-8 allows 80 ÷ 200.3 = 0.40 W, and in the 5.3 mm SO package 0.84 W. A dual op-amp drawing 1.4 mA per channel at 30 V burns 84 mW, so the SOIC-8 has better than six times margin, and the package choice is free. Put a 400 mW load in the same outline and it is not.
Tape, reel and stock, which the drawing does not tell you
Package size propagates into the feeder. The TL072 packing tables give the carrier tape geometry for each outline.
| 8-pin package | Tape width (mm) | Pocket A0 × B0 × K0 (mm) | Pitch P1 (mm) | Parts per reel |
| D, SOIC narrow | 12 | 6.4 × 5.2 × 2.1 | 8.0 | 2,500 |
| PW, TSSOP | 12 | 7.0 × 3.6 × 1.6 | 8.0 | 2,000 |
| PS, SO 5.3 mm | 16 | 8.35 × 6.6 × 2.4 | 12.0 | 2,000 |
| DDF, SOT-23-THIN | 8 | 3.2 × 3.2 × 1.4 | 4.0 | 3,000 |
SOIC-8 rides 12 mm tape at 8 mm pitch. Moving to the 5.3 mm body pushes you to a 16 mm feeder at 12 mm pitch, which is a wider slot on the machine and fewer parts per unit tape length. On a crowded feeder bank that is a scheduling constraint, not a detail.
Availability check. The TL072CDR in 8-SOIC lists at $0.35 for one unit and $0.1874 at 100 on DigiKey, with 66,018 in stock. The factory lead time behind that stock is 16 weeks. Distributor inventory on a mature SOIC-8 hides a long replenishment tail, so second-source the footprint, not just the part number.
Moisture sensitivity on this package is Level 1 with a 260 °C peak, meaning unlimited floor life. That is a property of the specific device, not of SOIC-8 generally, so read the bag label.
SOIC-8 dimensions FAQ
What are the dimensions of a SOIC-8 package?
A narrow-body SOIC-8 is 4.80 mm to 5.00 mm long and 3.80 mm to 4.00 mm wide across the molded body, standing 1.35 mm to 1.75 mm tall. Lead span is 5.80 mm to 6.20 mm on 1.27 mm pitch, per JEDEC MS-012-AA. Two larger outlines also ship under the SOIC-8 name.
What is the lead span of a SOIC-8?
5.80 mm to 6.20 mm, measured lead tip to lead tip. That figure, not the body width, is what your land pattern has to match. The 210 mil variant spans 7.40 mm to 8.20 mm and the 7.50 mm wide-body variant spans 11.5 mm typical, so verify the drawing before reusing a footprint.
How tall is a SOIC-8?
1.75 mm maximum, 1.35 mm minimum, measured from the seating plane. Of that, 0.10 mm to 0.25 mm is standoff between the body and the board. The 210 mil variant is capped at 2.20 mm and the wide-body variant at 2.80 mm, so height headroom is worth checking per variant.
Is SOIC-8 the same as SOP-8?
Not reliably. Texas Instruments and Fairchild reserve SOIC for the JEDEC 3.9 mm and 7.5 mm bodies and use SOP for the 5.3 mm EIAJ Type II body. Other vendors use the names interchangeably. The lead span settles it: 6.0 mm nominal for narrow SOIC-8, about 7.8 mm for the EIAJ part.
What pad size does a SOIC-8 footprint need?
Roughly 1.55 mm long by 0.60 mm to 0.76 mm wide, on 1.27 mm pitch, with 5.40 mm between the two pad rows measured center to center. TI publishes 1.55 mm by 0.60 mm; onsemi publishes 1.52 mm by 0.76 mm. Both give about 7.0 mm of overall land length.
What is the pin pitch of a SOIC-8?
1.27 mm, listed as a basic dimension, equal to 0.050 in. All three SOIC-8 body widths share it, which is why the packages look interchangeable in a parts list and are not. Design the footprint in metric using the exact 1.27 mm value rather than converting from inches.
Which SOIC-8 to specify
Take the narrow body when the part is a signal-level device dissipating under about 300 mW at your worst-case ambient. It is the smallest of the three, the cheapest, and the one every assembly line already has feeders for.
Move to the 5.3 mm body when you need the thermal headroom and can afford a 16 mm feeder, and to the 7.50 mm wide body only when creepage requires it. Neither is a drop-in for the narrow footprint.
Before releasing the layout, pull the case outline for your exact orderable part number, confirm the lead span rather than the body width, and pick a pad width deliberately: 0.60 mm for density, 0.76 mm for reworkability.
Internal links to place:
- [INTERNAL LINK: JEDEC MS-012 vs MS-013 explained → small outline package registrations]
- [INTERNAL LINK: IPC-7351B land pattern construction → footprint density levels and toe fillets]
- [INTERNAL LINK: reading thermal resistance on a datasheet → RθJA, ψJT and JEDEC test boards]
