An SO-8 package is an 8-lead gull-wing surface-mount body on 1.27 mm pitch, 3.90 mm wide, 4.90 mm long, and 1.75 mm tall at most, with a 6.00 mm lead span. Unlike most packages, SO-8 carries several de facto pinouts that are honored industry-wide, so the eight pins are largely predictable once you know the device class. Both the dimensions and those pinouts are below.

Key Takeaways

• Standard SO-8 is JEDEC MS-012 variant AA: 1.27 mm pitch, 3.90 × 4.90 mm body, 6.00 mm lead span, 1.75 mm maximum height.
• Five device classes have settled pinouts on SO-8 — SPI flash, I²C EEPROM, single power MOSFET, dual op-amp, and the 555 timer. Table 2 gives all five.
• A 208 mil SO-8 exists alongside the 150 mil version and is common on serial flash. The footprints are not interchangeable.
• Standard leaded SO-8 has no exposed pad. Thermal resistance runs 100 to 160 °C/W; the flat-lead and PowerPAK derivatives cut that to roughly 40 to 50 °C/W.
• In quad SPI mode, pins 3 and 7 stop being WP# and HOLD# and become IO2 and IO3. Route them as signals from the start.

SO-8, SOIC-8, SOP-8: what the name fixes

SO stands for Small Outline. In current datasheets, SO-8 and SOIC-8 refer to the same JEDEC-registered outline, MS-012 variant AA. SO is the older term, inherited from the original Philips and Signetics parts; vendors use both interchangeably.

The name fixes three things: eight leads, 1.27 mm pitch, gull-wing lead form. It fixes nothing about pin function, thermal capability, or whether there is an exposed pad on the underside.

EIAJ/JEITA SOP-8 is a separate registration with its own tolerances, not a synonym. MSOP-8, TSSOP-8 and SOT-23-8 all carry eight pins and appear similar in a BOM line, but none of them fits an SO-8 land pattern.

[IMAGE 1: annotated top and side view of an SO-8 with D, E, E1, A and e called out, plus a side-by-side silhouette against MSOP-8 | alt: “SO-8 package dimensions diagram with lead span, body width and height labeled”]

SO-8 package dimensions

SO-8 package dimensions are 1.27 mm lead pitch, 3.90 mm body width, 4.90 mm body length, 6.00 mm overall lead span, and 1.75 mm maximum seated height. Standoff runs 0.10 to 0.25 mm. The footprint occupies roughly 29 mm² of board area including the pads.

Symbol	Dimension	Value (JEDEC MS-012 AA)
A	Overall height, max	1.75 mm
A1	Standoff	0.10 – 0.25 mm
b	Lead width	0.31 – 0.51 mm
c	Lead thickness	0.17 – 0.25 mm
D	Body length	4.80 – 5.00 mm
E	Lead span, overall	5.80 – 6.20 mm
E1	Body width	3.80 – 4.00 mm
e	Lead pitch	1.27 mm BSC
L	Foot length	0.40 – 1.27 mm
θ	Lead foot angle	0° – 8°

Table 1. Controlled dimensions for standard SO-8. Confirm against the MS-012 revision cited on your manufacturer’s mechanical drawing.

Two notes on the drawing decide whether your machine vision accepts good parts. Dimension D excludes mold flash, typically capped at 0.15 mm per side; dimension E1 excludes interlead flash, typically capped at 0.25 mm per side. Load the un-flashed values into the package definition.

A second SO-8 width exists and catches people out. Serial flash vendors offer a 208 mil SO-8 alongside the 150 mil version, with a body near 5.3 mm and a lead span near 8 mm. The pinout is identical, the footprint is not. Read the package suffix on the ordering code, not the outline name.

SO-8 pinout: five de facto standards

Pin numbering follows the usual rule. Viewed from above with the pin 1 marker at the upper left, numbering runs counterclockwise: pins 1 to 4 down the left side, pins 5 to 8 up the right side. Pin 1 is marked with a molded dimple, a laser dot, or a beveled body edge.

Function assignment is not part of the registration, but for eight pins the industry converged anyway. These five arrangements hold across nearly every vendor in their class.

Pin	SPI flash (25-series)	I²C EEPROM (24-series)	Single N-ch MOSFET	Dual op-amp	555 timer
1	CS#	A0	Source	OUT A	GND
2	DO / IO1	A1	Source	IN A−	TRIG
3	WP# / IO2	A2	Source	IN A+	OUT
4	GND	VSS	Gate	V−	RESET
5	DI / IO0	SDA	Drain	IN B+	CTRL
6	CLK	SCL	Drain	IN B−	THRES
7	HOLD# / IO3	WP	Drain	OUT B	DISCH
8	VCC	VCC	Drain	V+	VCC

Table 2. The five settled SO-8 pinouts. Confirm each against the specific datasheet revision before layout — these are conventions, not standards.

The SPI flash column carries a trap worth designing around. In single-bit mode, pin 3 is write protect and pin 7 is hold or reset. Enable quad mode and both become bidirectional data lines, IO2 and IO3. Tie either one to a rail and quad reads fail on the bench with no warning at compile time.

For FPGA configuration flash, that matters twice over: the bitstream loads over single-bit SPI at power-up, then the same device may switch to quad for application data. Route pins 3 and 7 as signals with pull-ups, never as hard-tied logic levels.

[IMAGE 2: top-view SO-8 pin map overlaid with the SPI flash and single-MOSFET assignments side by side | alt: “SO-8 pinout diagram showing SPI flash and MOSFET pin assignments”]

Power SO-8: exposed pad and leadless derivatives

Standard SO-8 has no thermal path other than its eight leads. Power MOSFET vendors solved that by keeping the 5 × 6 mm outline and replacing the gull-wing leads with flat leads plus an exposed drain pad.

Outline	Lead form	Max height	Exposed pad	Typical RθJA
Standard SO-8	Gull-wing	1.75 mm	No	100 – 160 °C/W
SO-8FL / flat lead	Flat, no bend	≈ 1.10 mm	Yes (drain)	40 – 50 °C/W
PowerPAK SO-8 (5 × 6)	Leadless	≈ 1.05 mm	Yes (drain)	40 – 50 °C/W
WSON-8 (3 × 3)	Leadless	0.80 mm	Yes	50 – 60 °C/W

Table 3. SO-8 and its power derivatives. RθJA figures are order-of-magnitude and board-dependent; take the number from the datasheet you are designing to.

These are not drop-in substitutions. The exposed pad is electrically the drain, so a footprint designed for leaded SO-8 will short the drain to whatever copper sits under the body. Decide leaded or leadless before you place the part, not after.

Thermal: work the number for your copper, not the datasheet’s

MOSFET datasheets quote RθJA on one square inch of 2 oz copper. Very few real layouts give a single SO-8 that much pour. The gap between the quoted figure and your board is where thermal reviews go wrong.

Worked example, N-channel SO-8 MOSFET, 10 mΩ RDS(on) at VGS = 10 V and 25 °C:

• Load 5 A continuous. Cold loss = I²R = 25 × 0.010 = 0.25 W.
• RDS(on) rises about 0.4%/°C. At Tj ≈ 100 °C the multiplier is roughly 1.3, giving 13 mΩ and 0.33 W.
• On 1 in² of 2 oz copper, RθJA ≈ 50 °C/W → ΔT = 16.5 °C. At 85 °C ambient, Tj ≈ 101.5 °C. Self-consistent, so the iteration converges here.
• On a cramped 2-layer board with 40 mm² of pour, RθJA can exceed 100 °C/W → ΔT ≈ 33 °C → Tj ≈ 118 °C, and RDS(on) climbs further.

Run the loop twice. Loss raises temperature, temperature raises RDS(on), and higher RDS(on) raises loss again. One pass understates the answer, and for a part running near its limit that single pass is the difference between a design that ships and one that browns out at 45 °C ambient.

Land pattern, stencil, and assembly

IPC-7351B names the standard footprint SOIC127P600X175-8N. The trailing letter is density level: L for least, N for nominal, M for most. Choose M when hand rework or in-line optical inspection is planned, since the longer toe fillet is what an inspector actually sees.

Generate pads from an IPC calculator rather than copying an old footprint. Nominal-density pads land near 0.60 mm wide by 1.55 mm long.

Stencil design is undemanding here. With a 0.12 mm foil and a 0.60 × 1.55 mm aperture, the area ratio is (0.60 × 1.55) ÷ (2 × (0.60 + 1.55) × 0.12) = 1.80, well clear of the 0.66 minimum in IPC-7525. Use 1:1 apertures. Leadless derivatives need the opposite treatment: window the thermal pad aperture to 60 to 80% coverage or the part floats.

Lead coplanarity is specified at 0.10 mm maximum. When one corner of a production run shows open joints, measure coplanarity before you touch the reflow profile.

SO-8 versus the smaller 8-pin packages

Package	Pitch	Body (W × L)	Max height	Lead span	Board area
SO-8 (MS-012 AA)	1.27 mm	3.9 × 4.9 mm	1.75 mm	6.0 mm	≈ 29 mm²
TSSOP-8 (MO-153)	0.65 mm	4.4 × 3.0 mm	1.20 mm	6.4 mm	≈ 19 mm²
MSOP-8 / VSSOP-8 (MO-187)	0.65 mm	3.0 × 3.0 mm	1.10 mm	4.9 mm	≈ 15 mm²
SOT-23-8	0.65 mm	1.6 × 2.9 mm	1.45 mm	2.8 mm	≈ 8 mm²
WSON-8 (3 × 3)	0.65 mm	3.0 × 3.0 mm	0.80 mm	Leadless	≈ 9 mm²

Table 4. Board area is lead span × body length — the rectangle the footprint actually consumes.

Decision rules:

• Default to SO-8 when 29 mm² is affordable. It hand-solders, it inspects visually, and second sources are everywhere.
• Move to MSOP-8 to halve the area, accepting 0.65 mm pitch and harder rework.
• Choose SOT-23-8 only when area dominates and dissipation is under about 200 mW.
• Go leadless when height is capped below 1 mm or the part needs a thermal pad. Budget for X-ray or endoscope inspection.

Second-sourcing and counterfeit checks

SO-8 serial flash looks like the easiest second-source in electronics. The pinout matches across vendors, the command set is largely common, and drop-in swaps usually work. Three differences break that assumption.

• The quad-enable bit sits in different status register locations depending on vendor. Read the status register map, not just the command table.
• Erase granularity varies. A driver written around 4 kB sectors will misbehave on a device whose smallest erase unit is larger.
• Read the JEDEC ID with command 9Fh and confirm it against the datasheet, then use the SFDP table under JESD216 for anything your driver auto-detects.

For counterfeit screening on SO-8, the cheap checks catch most of it. Compare the marking method against the manufacturer standard, since a laser-marked part where the vendor uses molded marking is a red flag. Wipe with isopropyl alcohol to see whether the top coat lifts. Read back the device ID before assembly, and on MOSFETs measure RDS(on) at a known gate drive against the datasheet limit.

Five mistakes that cause respins

1. Laying out a 150 mil SO-8 footprint and ordering the 208 mil serial flash. The part sits across the pads and bridges nothing.
2. Hard-tying pins 3 and 7 on an SPI flash, which forecloses quad mode permanently.
3. Quoting the 1 in² RθJA in a thermal review when the layout gives the part 40 mm² of copper.
4. Treating SO-8FL as pin-compatible with leaded SO-8 and shorting the exposed drain pad to a ground pour.
5. Second-sourcing serial flash on pinout alone and shipping firmware that cannot enable quad mode on the alternate device.

Frequently asked questions

Is SO-8 the same as SOIC-8?

Yes. Both names refer to the 8-lead small outline package registered as JEDEC MS-012 variant AA. SO is the older term inherited from the original Philips and Signetics parts. Vendors use SO-8, SOIC-8 and SOIC8 interchangeably in ordering codes and datasheets, and the mechanical drawing is the same.

What are the dimensions of an SO-8 package?

Body width is 3.90 mm, body length 4.90 mm, and overall lead span 6.00 mm. Maximum seated height is 1.75 mm and standoff is 0.10 to 0.25 mm. Lead pitch is 1.27 mm BSC. The footprint consumes roughly 29 mm² of board area including pads.

What is the standard SO-8 pinout?

There is no single standard, but five conventions hold across vendors. SPI flash uses CS#, DO, WP#, GND, DI, CLK, HOLD#, VCC on pins 1 to 8. A single N-channel MOSFET uses pins 1 to 3 for source, pin 4 for gate, and pins 5 to 8 for drain. Dual op-amps and the 555 have their own settled maps.

What is the difference between SO-8 and MSOP-8?

MSOP-8 uses 0.65 mm pitch against 1.27 mm for SO-8, with a 3.0 × 3.0 mm body instead of 3.9 × 4.9 mm. That halves board area to about 15 mm² and cuts maximum height to 1.10 mm. The trade is harder hand rework and less lead area for heat.

How much power can an SO-8 dissipate?

A standard leaded SO-8 with RθJA near 130 °C/W handles roughly 0.4 W before a 50 °C rise. Flat-lead and PowerPAK derivatives with an exposed drain pad reach 40 to 50 °C/W on adequate copper, allowing well over 1 W. The copper area under and around the part sets the real limit.

What to do next

Pick standard leaded SO-8 for signal parts, memory, and anything dissipating under about 0.4 W. It is the last package on the shelf that a technician can rework with an iron and a bench microscope, and that alone justifies the 29 mm².

Cross to a flat-lead or leadless derivative the moment dissipation passes half a watt or the enclosure caps height below 1.2 mm. Then do three checks before the design review: confirm the width variant on the ordering code, route pins 3 and 7 as signals if the part is serial flash, and recompute the junction temperature with your actual copper area rather than the datasheet test board.