SMD package types fall into three groups: passive chip packages named by case code, discrete transistor and diode packages in the SOT and SOD families, and IC packages from SOIC up to BGA. This guide maps each one to its code, its size and lead pitch, and what it is actually used for — including the JEDEC aliases that make the same package answer to three or four different names.

Key takeaways

• SMD packages split into passives (case codes), discretes (SOT, SOD, DPAK), and ICs (SOIC, QFP, QFN, BGA).
• One package often carries several names: SOT-23 = JEDEC TO-236AA/AB = SC-59, formalized in JEDEC MO-178.
• Lead pitch sets hand-solderability: down to 0.65 mm is workable by hand; QFN and BGA are reflow-only.
• Power discretes add a thermal tab: a D2PAK (TO-263) reaches θJA ≈ 18 °C/W with one square inch of copper, per TI.
• Diodes use their own codes: SMA / SMB / SMC = JEDEC DO-214AC / AA / AB.
• Match the package to the job: SOT-23 for small-signal, DPAK/D2PAK for power, QFP/QFN for MCUs and RF, BGA for high I/O.

The SMD package families at a glance

Surface-mount packages exist to do one of a few jobs: hold a passive, house a discrete transistor or diode, or carry an IC die at a given pin count. The table sorts the whole field by that job.

[IMAGE 1: a board populated with one part from each family — chip resistor, SOT-23, DPAK, SMA diode, SOIC, QFN, BGA — at matched scale | alt: “SMD package types compared: passive chip, SOT, DPAK, diode, SOIC, QFN and BGA”]

Family	Example codes	Leads / mounting	Typical use
Passive chip	0201, 0402, 0603, 0805, 1206	2-terminal	Resistors, capacitors, inductors, LEDs
Small-signal discrete	SOT-23, SC-70, SOD-123	3–6 leads / 2-lead	Transistors, small diodes
Power discrete	SOT-223, DPAK, D2PAK	Leads + thermal tab	MOSFETs, regulators, power diodes
Power diode	SMA, SMB, SMC	2-lead (DO-214)	Rectifiers, Schottky diodes
General IC	SOIC, TSSOP, LQFP	Gull-wing, 2 or 4 sides	MCUs, analog, logic
High-I/O IC	QFN, BGA, CSP	Leadless / area-array	SoCs, FPGAs, processors

The rest of this guide takes each family in turn, because identifying a part usually starts with placing it in one of these rows.

Passive chip packages: the case codes

Chip resistors, ceramic capacitors, and inductors share a four-digit case code that states body length and width — imperial 0603 is 0.060 in × 0.030 in (1.6 mm × 0.8 mm, metric 1608). Common sizes run 0201, 0402, 0603, 0805, and 1206, with 0603 the usual default.

Two variations matter. MELF resistors use a cylindrical body (0102, 0204, 0207) for lower drift, and tantalum capacitors ignore the four-digit code entirely, using letter codes (A, B, C, D) mapped to metric outlines. For the full dimensional chart and the imperial-versus-metric trap, see the dedicated size-code reference.

[INTERNAL LINK: SMD package size chart -> case code dimensions for every SMD size]

Discrete transistor and diode packages: the SOT/SOD zoo

Discrete transistors, MOSFETs, and diodes live in the SOT (small-outline transistor) and SOD (small-outline diode) families. This is where package naming gets messy, because JEDEC, JEITA, and each vendor use different labels for the same body.

Package	JEDEC / other names	Size L×W×H (mm)	Pitch	Typical use
SOT-23 (SOT-23-3)	TO-236AA/AB, SC-59	2.9 × 1.3 × 1.0	0.95 mm	Small-signal transistors, diodes, MOSFETs
SC-70 (SOT-323)	SC-70-3, JEITA	2.0 × 1.25 × 0.9	0.65 mm	Space-critical small-signal parts
SOT-363 (SC-88)	SC-70-6, SOT-323-6	~2.0 × 1.25	0.65 mm	Dual and complex small-signal, 6-lead
SOT-89	TO-243AA	4.5 × 2.5 × 1.5	1.5 mm	Medium-power transistors, regulators (tab)
SOT-223	TO-261AA	6.5 × 3.5 × 1.6	2.3 mm	LDO regulators, power transistors (tab)
SOD-123 / SOD-323	JEDEC SOD outlines	~2.7 × 1.6 / 1.7 × 1.25	—	Small-signal and switching diodes

The SOT-23 is the workhorse, introduced to replace the through-hole TO-18 and TO-92, and its 3-, 5-, and 6-lead versions all share a 0.95 mm pitch and a common 6-pin footprint. The SC-70 (SOT-323) is a smaller 0.65 mm-pitch shrink for tight boards. Both handle small-signal transistors, dual diodes, and logic-level MOSFETs.

Diodes add their own naming layer. Small-signal parts use SOD-123, SOD-323, and SOD-923 — the last is about 1.0 mm × 0.5 mm. Power rectifiers use the DO-214 family, where SMA is DO-214AC, SMB is DO-214AA, and SMC is DO-214AB, from smallest to largest. Reading the letter as the size, or the JEDEC number as the letter, is a common footprint mistake.

The practical rule: never trust the name alone. Measure the body and lead pitch with calipers, then confirm against the datasheet, because a single part may be listed as SOT-23-3, TO-236-3, and SC-59 across different distributors.

Surface-mount power packages: DPAK, D2PAK, and up

When a MOSFET, regulator, or rectifier has to shed real heat, it moves to a package with an exposed metal tab that solders to a copper pour. These are surface-mount versions of the old TO-220.

[IMAGE 2: cross-section of a DPAK/D2PAK showing die, thermal tab, and copper pour path to the PCB | alt: “surface-mount power package thermal tab and copper pour heat path for DPAK and D2PAK”]

The DPAK (TO-252) is the medium-power step, with a 1.27 mm lead pitch, used for medium-power MOSFETs and linear regulators. The D2PAK (TO-263) is larger — the surface-mount equivalent of the TO-220, sometimes called “SMD-220” — with a standard height of 4.57 mm (a TO-263 THIN variant drops to 2.0 mm), for higher-current MOSFETs and power diodes. Above it sits the D3PAK (TO-268).

The tab is only as good as the copper behind it. Per TI’s data, a TO-263 reaches θJA ≈ 18.0 °C/W with one square inch of copper connected to the tab, and ROHM specifies junction-to-case values near 2.8 °C/W for DPAK and 2.4 °C/W for D2PAK. Shrink the copper and θJA climbs fast.

Worked example. A D2PAK MOSFET dissipates 2 W. With one square inch of copper, θJA ≈ 18 °C/W, so the rise is 2 W × 18 °C/W = 36 °C. In a 60 °C ambient, the junction sits near 96 °C — comfortable. Halve the copper and θJA rises, pushing the junction toward its limit. The package rating assumes the copper; the layout has to deliver it.

IC packages: SOIC to BGA

Integrated circuits scale by pin count and pitch, from wide-lead SOIC up to area-array BGA. Pitch is the deciding variable: it sets both how many pins fit and whether the part can be hand-soldered.

Package	Pitch	Pin range	Hand-solder?	Typical use
SOIC / SOP	1.27 mm	8–28	Yes	General analog, logic, op-amps
SSOP / TSSOP	0.65 mm	up to 56	With care	Compact logic, MCUs, drivers
MSOP	0.5 mm	8–12	Difficult	Small analog, space-limited parts
QFP / LQFP / TQFP	0.4–0.8 mm	32–280	Reflow (fine pitch)	MCUs, DSPs, FPGAs, ASSPs
QFN / DFN	0.4–0.65 mm	up to ~100	Reflow only	Wireless SoCs, RF, power ICs
BGA	0.4–1.0 mm ball	100–2000+	Reflow + X-ray	Processors, FPGAs, DDR, ASICs
CSP / WLCSP	0.35–0.5 mm ball	up to ~200	Reflow + X-ray	Mobile, wearables, tight space

SOIC at 1.27 mm is the friendliest IC package, with visible joints and easy rework — the default for jelly-bean analog and logic. TSSOP and SSOP at 0.65 mm shrink the footprint for MCUs and drivers while staying hand-workable with care.

For higher pin counts, QFP and LQFP put gull-wing leads on four sides at 0.4–0.8 mm pitch across 32 to 280 pins, covering most microcontrollers and mid-density FPGAs. QFN trades leads for perimeter pads and an exposed thermal pad, which makes it compact and thermally strong for wireless SoCs and power ICs, but its hidden joints demand reflow and X-ray. BGA and CSP move all connections under the body as solder balls, the only way to reach very high I/O — and they require X-ray inspection and reflow infrastructure.

How the codes and names actually work

Three bodies name these packages, and they do not agree. JEDEC registers mechanical outlines in Publication 95 (JEP95) using codes like TO-236 for SOT-23, TO-243 for SOT-89, and MO-178 for the SOT-23 family dimensions. JEITA/EIAJ uses SC-prefixed names such as SC-70 and SC-59. Vendors add brand names on top — Toshiba calls the SOT-323 “USM,” and Fairchild called the SOT-23 “SuperSOT-3.”

The result is that one physical package answers to several labels, and the numbers in a name are usually just serial identifiers, not dimensions — SOT-23 is simply “SOT package number 23.” The digits that do carry meaning are the pin-count suffixes: SOT-23-5 means five leads, sometimes wrongly written SOT-25. For passives and ICs, the EIA case-code and metric conventions apply, and taping follows EIA-481. Always resolve the outline to a JEDEC or datasheet drawing before committing a footprint.

How to pick an SMD package

Work from the part’s job, and the package usually follows.

1. Identify the function. Passive, small-signal discrete, power discrete, diode, or IC — that sets the family.
2. Fix the pin count. For ICs, under ~28 pins suits SOIC or TSSOP; up to a few hundred needs QFP or QFN; beyond that, BGA.
3. Check the thermal path. For power parts, choose a tabbed package (SOT-223, DPAK, D2PAK) and budget the copper the θJA assumes.
4. Match your assembly. Hand or mixed build: stay at 0.65 mm pitch or wider and avoid QFN and BGA. Reflow line: any package, with X-ray for hidden joints.
5. Confirm the outline. Resolve the package name to a JEDEC or datasheet drawing, and verify the land pattern before routing.

SMD package mistakes that cause returns

• Trusting a package name across vendors — ordering a SOT-23 when the design used a SC-70, or vice versa.
• Reading a diode letter as a size — swapping SMA (DO-214AC) for SMB (DO-214AA) on the same land.
• Starving a power tab of copper, so the D2PAK or DPAK runs far hotter than its datasheet θJA.
• Specifying QFN or BGA without reflow and X-ray, then being unable to inspect or rework.
• Assuming QFP and QFN are interchangeable — they have different footprints and cannot be swapped without a redesign.
• Confusing a pin-count suffix (SOT-23-6) with a different package family.

FAQ

What are the different types of SMD packages?

SMD packages fall into passive chip packages named by case code (0402, 0603, 0805), discrete transistor and diode packages (SOT-23, SC-70, SOD-123, and the DO-214 diode family), power packages with thermal tabs (SOT-223, DPAK, D2PAK), and IC packages (SOIC, TSSOP, QFP, QFN, BGA). Each maps to a pin count, pitch, and use.

What is the difference between SOT-23 and SC-70?

Both are small-outline transistor packages, but the SC-70 (also called SOT-323) is smaller with a finer 0.65 mm lead pitch, versus 0.95 mm for the SOT-23. The SOT-23 body is about 2.9 mm × 1.3 mm; the SC-70 is about 2.0 mm × 1.25 mm. Use the SC-70 where board space is tight.

Is TO-236 the same as SOT-23?

Yes. TO-236 is the formal JEDEC outline name for the SOT-23 package — specifically TO-236AA and TO-236AB for the 3-lead version. The same part may appear on datasheets and distributor listings as SOT-23-3, TO-236-3, or SC-59. They describe one physical package; always confirm the land pattern against the datasheet.

What is the difference between DPAK and D2PAK?

Both are surface-mount power packages with an exposed thermal tab. The D2PAK (TO-263) is larger than the DPAK (TO-252) and handles more power — it is the surface-mount equivalent of the TO-220. The DPAK suits medium-power MOSFETs and regulators; the D2PAK handles higher-current MOSFETs and power diodes. Both need copper pour for their thermal rating.

Which SMD packages can be hand-soldered?

Packages with leads at 0.65 mm pitch or wider are hand-solderable: chip passives 0603 and up, SOT-23, SC-70, SOIC (1.27 mm), and TSSOP (0.65 mm). Leadless and area-array packages — QFN, BGA, and CSP — have hidden joints and generally require reflow with X-ray inspection, not hand soldering.

What is the difference between QFP and QFN?

A QFP has gull-wing leads extending from all four sides, giving visible, hand-solderable joints. A QFN is leadless, using perimeter pads under the body plus an exposed thermal pad, which makes it smaller and thermally better but requires reflow and X-ray. They have different footprints and cannot be swapped without redesigning the board.

The bottom line

Start by placing the part in a family — passive, discrete, power, diode, or IC — then let pin count, thermal need, and your assembly line pick the package. For general ICs, default to SOIC or LQFP; for power discretes, choose a tabbed DPAK or D2PAK and give the tab its copper; for high I/O, plan for BGA with reflow and X-ray. Above all, resolve every package name to its JEDEC outline or datasheet drawing before you route — the same package wearing three names is what sends boards back.