Power semiconductor packages fall into three families: through-hole parts like the TO-220 and TO-247, leaded surface-mount parts like the DPAK and D2PAK, and leadless or clip parts like the TOLL, LFPAK, and DirectFET, with bolt-on modules above them. The choice is driven by three things: how you get heat out, how fast the device switches, and how you assemble it. This guide covers the power semiconductor package types an engineer actually chooses between, with the numbers that separate them.
Key takeaways
- The package sets your parasitics, not just your footprint. Adding a Kelvin source pin cuts a SiC MOSFET’s switching loss roughly threefold, from about 430 microjoules to 150 microjoules at 30 A in one Wolfspeed comparison of TO-247-3 versus TO-247-4.
- Through-hole TO-220 and TO-247 dominate discrete power by volume; their surface-mount equivalents are the DPAK (TO-252) and D2PAK (TO-263).
- Cooling side matters. Top-side-cooled packages route about 95 percent of the heat straight to the heatsink and offer roughly 3 times lower power-loop inductance than through-hole or bottom-cooled parts, per Infineon’s data.
- Clip interconnects beat bond wires. The LFPAK56 (Power-SO8, JEDEC MO-235) uses a copper clip instead of wires and is 50 percent smaller than a DPAK while carrying more current.
- For fast SiC and GaN, pick the package for inductance and cooling first, then confirm the current and footprint, the reverse of the old habit.
The three families of power packages
Discrete power packages divide into three families. Through-hole packages such as the TO-220 and TO-247 bolt to a heatsink through a metal tab. Leaded surface-mount packages such as the DPAK and D2PAK are their reflow-solderable equivalents. Leadless and clip packages such as the TOLL, LFPAK, and DirectFET drop parasitic inductance and improve cooling for fast switching. Power modules sit above all three, integrating several dies in one isolated case.
Each family answers the same two questions differently: where the heat exits the die, and how much stray inductance the leads add. Through-hole parts cool through a rear tab and carry the most lead inductance. Leaded SMD parts cool through a bottom pad into the board. Leadless and top-cooled parts shorten every current path and can dump heat from the top. Those differences decide switching speed and thermal headroom.
[IMAGE 1: side-by-side of TO-247, TO-220, D2PAK, DPAK, LFPAK56, and a top-cooled TOLT package | alt: “Power semiconductor package types explained showing TO-247, TO-220, D2PAK, DPAK, LFPAK and TOLT”]
Power package comparison table
The table below is built for decisions. It pairs the cooling path and interconnect with relative parasitic inductance, the combination that decides whether a package can keep up with a fast SiC or GaN die.
| Package (JEDEC) | Mount | Cooling side | Interconnect | Parasitic L | Typical use |
| TO-247 / TO-247-4 | Through-hole | Rear tab to heatsink | Bond wire | High (Kelvin option) | SiC/IGBT, 5–20 kW |
| TO-220 (TO-220AB) | Through-hole | Rear tab to heatsink | Bond wire | High | Regulators, mid-power |
| DPAK (TO-252) | SMD leaded | Bottom pad to board | Bond wire | Medium | Mid-power MOSFETs |
| D2PAK (TO-263) | SMD leaded | Bottom pad to board | Bond wire | Medium | High-power MOSFETs |
| D2PAK-7 (TO-263-7) | SMD leaded | Bottom pad to board | Bond wire (Kelvin) | Lower | SiC with Kelvin source |
| LFPAK56 (Power-SO8 / MO-235) | SMD leadless | Bottom pad to board | Copper clip | Low | Automotive, DC-DC |
| TOLL / TOLT | SMD leadless | Bottom / top | Copper clip | Low | High-density SiC |
| DirectFET | SMD can | Top (dual-side) | Metal can | Very low | High-frequency VRM |
| SOT-227 module | Bolt-down | Baseplate | Bond wire | Module-level | Isolated half-bridge |
[IMAGE 2: heat-flow diagram contrasting bottom-side cooling through thermal vias with top-side cooling to a heatsink | alt: “Top-side versus bottom-side cooling for power semiconductor package types”]
Through-hole: TO-220 and TO-247
The TO-220 is the classic power package: a 2.54 mm-pitch, three-lead body with a tabbed metal back and mounting hole that bolts to a heatsink. On a large heatsink it can shed 50 W or more of waste heat. Junction-to-case resistance depends on the die, but the range is instructive: National’s LM317 in TO-220 lists a junction-to-case resistance of 4 degrees C per watt, while a big power MOSFET like the IRF2807 reaches 0.65 degrees C per watt in the same outline per its datasheet.
The TO-247 is the larger, higher-dissipation relative, standard for IGBTs and SiC MOSFETs in the multi-kilowatt range. Its extra body area lowers thermal resistance and handles higher voltage and current than a TO-220. Both are hand- and wave-solderable and rugged in vibration, which keeps them in industrial and high-power designs despite the board area they consume.
The catch with both is lead inductance. The source connection runs through a bond wire and a long package pin, and that inductance interferes with fast switching, which is exactly what the four-lead variant fixes.
The Kelvin source pin: why 4-pin packages cut switching loss
In a three-lead package, the source inductance is shared by the power current loop and the gate-drive loop. During a fast di/dt transition, the voltage across that shared inductance opposes the gate driver, pulls down the gate-source voltage at the die, and slows the switch, burning energy as loss. This common-source inductance is the single biggest package limit on SiC switching speed.
A Kelvin source pin breaks the sharing. The four-lead TO-247-4 adds a separate gate-driver return that carries no power current, so the driver sees the true die voltage. The payoff is large and measured. Wolfspeed reports a TO-247-3 part with about 12 nH of source inductance dissipating close to 430 microjoules per switching event at 30 A, while the same die in a TO-247-4 drops to roughly 150 microjoules. Powermaster’s app note AN-CM2307 measured a 1200 V, 80 milliohm SiC MOSFET and found the TO-247-4L cut turn-on loss by 71 percent and turn-off loss by 28 percent at 25 A, trimming total loss about 18 percent in a 5 kW inverter.
| Package | Source configuration | Switching-loss / inductance effect | Source |
| TO-247-3 | Common source (~12 nH) | ~430 µJ per event at 30 A | Wolfspeed |
| TO-247-4 | Kelvin source | ~150 µJ at 30 A (~3× lower) | Wolfspeed |
| TO-247-4L | Kelvin source | Turn-on −71%, turn-off −28% at 25 A | Powermaster AN-CM2307 |
| D2PAK-7 (TO-263-7) | Kelvin, parallel source pins | Much lower stray L than TO-247 | ROHM / Wolfspeed |
| TOLT (top-cooled) | Leadless | ~3× lower loop inductance vs TH | Infineon |
The four-lead package also spreads its terminals for isolation: Wolfspeed’s TO-247-4L specifies 8 mm of creepage between the drain and the adjacent pin. If you run SiC or GaN in a three-lead package, you are leaving switching efficiency on the table.
Surface-mount power packages: from DPAK to leadless clips
Surface-mount power packages trade the bolt-on tab for a bottom pad soldered to board copper. The DPAK (TO-252) handles mid-power MOSFETs and regulators; the D2PAK (TO-263) is effectively a surface-mount TO-220, carrying 3 to 7 terminals for higher power. Both cool through the board, so they need generous copper and thermal vias to reach their ratings, and both come in a low-profile THIN form: TI’s TO-263 THIN is 2 mm tall against the standard 4.5 mm.
The seven-lead versions matter for wide-bandgap devices. The D2PAK-7 (TO-263-7) adds a Kelvin source and realizes the drain as a large-area pad with the source split across several short parallel leads, giving much lower stray inductance than a TO-247 while staying surface-mount.
Leadless and clip packages push further. The LFPAK56, also called Power-SO8 and standardized as JEDEC MO-235, replaces bond wires with a copper clip to the die top, cutting resistance and inductance while running about 50 percent smaller and 40 percent thinner than a DPAK. It is AEC-Q101-qualified with a 175 degrees C maximum junction, and NXP’s thermal note AN90003 shows a single device dissipating about 5.3 W at 20 degrees C ambient on a generous copper pour. The DirectFET takes the idea to a metal can with dual-sided cooling and very low inductance for high-frequency voltage regulators.
Top-side versus bottom-side cooling
Where the heat leaves the package changes both thermals and layout. A bottom-cooled SMD part sends heat down through the board, usually via a thermal-via array, which works but blocks the ground-plane return directly under the device and enlarges the high-frequency current loop, raising EMI, as WeEn’s package analysis notes.
Top-side cooling flips the heat path upward to a heatsink and frees the board underneath. Infineon’s TOLT package exposes the drain at the top surface and routes about 95 percent of the heat straight to the heatsink, which it measures as roughly 20 percent better junction-to-ambient resistance and 50 percent better junction-to-case resistance than the bottom-cooled TOLL, while supporting more than 300 A. Across a set of SiC packages, Infineon found top-side-cooled devices deliver about 3 times lower power-loop parasitic inductance than through-hole and bottom-cooled parts. For high-density SiC, top-side cooling wins on heat and layout at once.
How to choose a power package
Work the decision in this order for a switching device.
First, set the cooling path from your power dissipation: a bolt-on tab (TO-220, TO-247) for the highest single-die watts, a bottom pad with copper and vias (DPAK, D2PAK) for moderate SMD power, or top-side cooling (TOLT, DirectFET) for high density. Second, gate on switching speed: for fast SiC or GaN, require a Kelvin source and a low-inductance package (TO-247-4, D2PAK-7, LFPAK, TOLT). Third, confirm assembly: through-hole for hand or wave build and vibration, surface-mount for automated lines. Only then check that the current rating, creepage, and footprint fit. Choosing the package last, after the die, is the habit that produces slow, hot designs.
Design mistakes and failure modes
The recurring failures start at the package and the board around it.
Running SiC in a three-lead package is the most common efficiency mistake: the shared source inductance slows switching and inflates loss for no benefit when a four-lead part exists. Starving an SMD power part of copper is next, since DPAK and D2PAK reach their ratings only with adequate pour and via arrays, and without them the junction runs hot. Over power cycling, the dominant hardware failures are bond-wire lift-off and heel cracking as the wire flexes with thermal expansion, and die-attach or solder-joint fatigue under the die, both accelerated by large temperature swings, which is part of why clip packages that eliminate source wires are more robust. Ignoring creepage on a compact high-voltage layout rounds out the list.
FAQ
What are the main power semiconductor package types?
Three families plus modules. Through-hole packages like the TO-220 and TO-247 bolt to a heatsink through a tab. Leaded surface-mount packages like the DPAK (TO-252) and D2PAK (TO-263) solder to board copper. Leadless and clip packages like the TOLL, LFPAK56, and DirectFET cut inductance and improve cooling. Power modules integrate several dies in one isolated case.
What is the difference between TO-220 and TO-247?
Both are through-hole, tab-cooled power packages, but the TO-247 is larger, dissipates more heat, and handles higher voltage and current, which is why IGBTs and SiC MOSFETs favor it. The TO-220 is smaller and cheaper and dominates mid-power regulators and MOSFETs. Neither is pin-compatible with the other’s surface-mount equivalents.
What is a Kelvin source pin?
A Kelvin source is a separate gate-driver return pin that carries no power current, found on four-lead packages like the TO-247-4 and D2PAK-7. It removes the common-source inductance shared between the power and gate loops, so the driver sees the true die voltage. The result is faster switching and lower loss, often a large reduction for SiC MOSFETs.
What is the best package for SiC MOSFETs?
The one with the lowest inductance that meets your cooling and assembly needs. For through-hole, use the four-lead TO-247-4 rather than the TO-247-3. For surface-mount, the D2PAK-7, LFPAK, or a top-cooled TOLT cuts inductance further. Prioritize a Kelvin source and low package inductance, then confirm current rating, creepage, and footprint.
What is top-side cooling?
Top-side cooling exposes the drain pad on the top of a surface-mount package so a heatsink mounts directly to it, instead of routing heat down through the board. Infineon’s TOLT sends about 95 percent of the heat to the heatsink and improves junction-to-case resistance by roughly 50 percent over the bottom-cooled TOLL, while freeing the board underneath and lowering EMI.
Which power package has the lowest parasitic inductance?
Leadless clip and can packages lead. DirectFET and top-cooled leadless packages like the TOLT minimize lead length and offer roughly 3 times lower power-loop inductance than through-hole parts, per Infineon. Among leaded options, the D2PAK-7 with its parallel source leads and a Kelvin pin beats the TO-247. Through-hole three-lead packages carry the most inductance.
What to do
Choose the package from the device’s job, not its parts-bin familiarity. For a fast SiC or GaN switch, start with a low-inductance, Kelvin-source package: TO-247-4 for through-hole power, or D2PAK-7, LFPAK, or a top-cooled TOLT for surface-mount, then verify current, creepage, and footprint. For a linear regulator or mid-power MOSFET where switching speed is not the constraint, a TO-220, DPAK, or D2PAK with adequate copper and thermal vias is correct and cheaper. Reserve modules for isolated multi-die stages above roughly 20 kW. Match cooling side to your mechanical design early, and give any bottom-cooled SMD part the copper and vias its rating assumes.
