A PLCC-68 package is 24.13 mm to 24.33 mm square across the plastic body, carries 68 J-leads on a 1.27 mm pitch with 17 leads per side, and stands 4.19 mm to 4.57 mm tall when seated. Pin 1 sits at the center of the beveled edge, and numbering runs counterclockwise viewed from the top. What follows are the JEDEC-traceable dimensions, the pin map, the reflow land pattern, and the sockets still orderable today.
[IMAGE 1: top and side view of a PLCC-68 package with body, lead-tip span, seated height and pin 1 bevel called out | alt: “PLCC-68 package dimensions showing 24.13 mm body, 25.27 mm lead span and 1.27 mm pitch”]
Key takeaways
- The registered outline is JEDEC MS-018, part of the MO-047 family for square plastic chip carriers, cross-referenced to IEC 112E10 and JEITA EDR-7319.
- Body is 24.13 mm to 24.33 mm square, but lead tips reach 25.02 mm to 25.27 mm. The lead-tip figure sets your keep-out, not the body.
- Pin 1 is at the center of the beveled edge. The corner leads are 9/10, 26/27, 43/44 and 60/61.
- Reflow land pattern: 3.25 mm by 0.70 mm lands, 21.40 mm inner span, 27.90 mm outer span, 28.15 mm occupied area.
- A socket adds roughly 2.5 mm per side, 4.4 mm of height and 15 mΩ to 30 mΩ of contact resistance.
- Junction-to-ambient thermal resistance is about 41.9 °C/W typical in still air, with junction-to-case near 9.5 °C/W.
PLCC-68 dimensions (JEDEC MS-018)
The PLCC-68 package has a plastic body 24.13 mm to 24.33 mm square (0.950 in to 0.958 in), a seated height of 4.19 mm to 4.57 mm, and 68 J-leads on a 1.27 mm (0.050 in) pitch, 17 leads per side. Measured lead tip to lead tip, the package spans 25.02 mm to 25.27 mm.
| Symbol | Parameter | Millimeters | Inches |
| D, E | Body length and width | 24.13 – 24.33 | 0.950 – 0.958 |
| HD, HE | Span across lead tips | 25.02 – 25.27 | 0.985 – 0.995 |
| A | Seated height | 4.19 – 4.57 | 0.165 – 0.180 |
| A2 | Body thickness (nominal) | 3.81 | 0.150 |
| A1 | Standoff, minimum | 0.51 | 0.020 |
| e | Lead pitch | 1.27 | 0.050 |
| bp | Lead width | 0.33 – 0.53 | 0.013 – 0.021 |
| ZD, ZE | Maximum lead offset at corners | 2.16 | 0.085 |
| β | Corner bevel angle | 45° | — |
| n2 | Terminations | 68 | — |
Table 1. PLCC-68 outline dimensions per NXP SOT188-2, JEDEC outline MS-018, issue date 14 November 2001.
Two details there cause more layout errors than the rest combined. JEDEC defines PLCC outlines in inches, so the millimeter column is a conversion and tolerance stacks should run against the inch values. And the gap between the 24.33 mm body maximum and the 25.27 mm lead-tip maximum is nearly a millimeter of overhang that falls outside a silkscreen drawn from the body.
One arithmetic check catches a bad library part in seconds: 16 lead spaces at 1.27 mm put 20.32 mm between the first and last lead centers on each side. If a footprint disagrees, it is not a PLCC-68.
Height is the one dimension that moves between suppliers. NXP publishes a pedestal variant, SOT188-3, with a 24.15 mm by 24.15 mm by 3.56 mm body against the 3.81 mm nominal body thickness of the standard outline. Infineon lists its PG-LCC-68-800 at 24.232 mm body length and width. Confirm the height against the specific datasheet before committing to an enclosure gap.
PLCC-68 pinout and pin numbering
PLCC packages number their pins counterclockwise when viewed from the top, with pin 1 in the center of the beveled edge, and Xilinx states this explicitly in its packaging databook. That single convention differs from QFP, where pin 1 sits in a corner, and it is the reason a rotated PLCC-68 footprint is a common first-article failure.
| Edge (viewed from the top) | Pin numbers | Count |
| Top edge, pin 1 at center | 61 – 68, then 1 – 9 | 17 |
| Left edge | 10 – 26 | 17 |
| Bottom edge | 27 – 43 | 17 |
| Right edge | 44 – 60 | 17 |
Table 2. PLCC-68 pin map. Corner leads are 9/10, 26/27, 43/44 and 60/61, as marked on the SOT188-2 outline drawing.
Reading along the top edge left to right gives 9, 8, 7 down to 1, then 68 back down to 61. Pin 1 is the ninth position from either end of a 17-lead edge, which is what makes the bevel the only reliable orientation feature on the part.
Two traps sit downstream of that map. Socket contacts are numbered to match device pins, but many socket drawings are bottom views, so a pinout that looks mirrored usually is; Ironwood Electronics publishes contact-to-base mapping tables for its PLCC-68 adapters for that reason. And not every 68-position socket follows the JEDEC map: the Atari ST used a different layout, so retrofits need an adapter board.
[IMAGE 2: top-view PLCC-68 pin numbering diagram with the beveled corner, pin 1, and the four corner lead pairs labeled | alt: “PLCC-68 pinout diagram showing pin 1 at the center of the beveled edge and counterclockwise numbering”]
PCB land pattern for a soldered PLCC-68
NXP publishes a generic reflow footprint alongside the SOT188-2 outline. These are the numbers to check a library part against.
| Footprint parameter | Value |
| Land pitch | 1.27 mm |
| Land size | 3.25 mm × 0.70 mm |
| Inner span between opposing land rows | 21.40 mm |
| Outer span across the land pattern | 27.90 mm |
| Occupied area | 28.15 mm × 28.15 mm |
Table 3. Reflow soldering footprint for PLCC68, SOT188-2.
The land extends 3.25 mm radially while the J-lead foot tucks under the body, so much of each land sits inboard of the lead. That is deliberate: the inboard area pulls solder under the foot and forms the joint you cannot see. Trimming land length to recover routing channels produces marginal joints.
Wave soldering needs a different pattern. NXP publishes a separate wave footprint with a solder thief and a specified board direction, because the trailing row of J-leads on a 25 mm package bridges readily. Reflow is the better process unless the assembly forces otherwise.
PLCC-68 socket options and what each one costs you
Sockets are why this package outlived its contemporaries: a programmable device can be programmed off-board and dropped in, and a failed part swapped without rework. The price is board area, height, contact resistance and another mechanical interface.
| Socket | Mounting | Housing | Contact plating | Temperature range |
| 3M 8468-21B1-RK-TP | Surface mount, closed frame | PBT, glass filled, UL94 V-0 | Tin, 160 µin over copper alloy | −40 °C to +105 °C |
| Adam Tech PLCC-68-AT-SMT | Surface mount, open frame | PPS, glass reinforced, UL94 V-0 | Tin over copper (gold optional) | −55 °C to +105 °C |
| Adam Tech PLCC-68-AT | Through hole, 0.100 in grid | PBT (PPS optional), UL94 V-0 | Tin over copper (gold optional) | −55 °C to +105 °C |
| Winslow WPLCC068-ST1RC | Through hole | Polyphenylene sulphide | Tin over copper | −55 °C to +105 °C |
| Preci-Dip 540-88-068-24-008 | Through hole, 4 row | PPS, glass reinforced | Tin | −55 °C to +125 °C |
Table 4. PLCC-68 sockets listed as orderable by DigiKey, Mouser, Future Electronics and RS Components at the time of writing.
Electrical ratings across the group are consistent: 1 A per contact, 15 mΩ contact resistance on the 3M part and 30 mΩ maximum initial on the Adam Tech series, 250 V AC operating on the Adam Tech sockets and 150 V DC on the Winslow. Adam Tech also specifies 6.35 oz maximum insertion force and 1.0 oz minimum withdrawal force, with UL recognition under file E224053. The withdrawal figure is the number to watch on a board that will be serviced: retention degrades with insertion cycles, and 1.0 oz is not much holding a 25 mm part against vibration.
The area penalty is concrete. A directly soldered PLCC-68 occupies 28.15 mm square. The Adam Tech surface-mount socket body is 30.52 mm square and 4.40 mm tall, and its through-hole version needs a 31.50 mm square board outline with Ø0.80 mm holes on a 0.100 in grid. Socketing therefore costs roughly 2.5 mm per side and stacks the device height on top of a 4.40 mm socket.
Use the extraction tool. Adam Tech sells a PLCC-EXT remover, and levering a part out with a screwdriver deforms the J-leads on the fulcrum side, which then read as intermittent contacts after reinsertion. If the socket must survive many cycles or carry low-level signals, order the gold-plated option rather than tin.
Thermal performance of the PLCC-68 package
Xilinx characterized its PC68 package, a PLCC-68, socketed per the SEMI method and published the full curve. None of the ranking PLCC-68 pages carry this data.
| Condition | PLCC-44 (PC44) | PLCC-68 (PC68) | PLCC-84 (PC84) |
| θJA still air, maximum | 53.7 °C/W | 46.2 °C/W | 41.7 °C/W |
| θJA still air, typical | 46.5 °C/W | 41.9 °C/W | 33.3 °C/W |
| θJA at 250 LFM, typical | 35.1 °C/W | 31.6 °C/W | 25.8 °C/W |
| θJA at 500 LFM, typical | 31.4 °C/W | 28.2 °C/W | 20.8 °C/W |
| θJC, typical | 14.9 °C/W | 9.5 °C/W | 5.6 °C/W |
| Dimension including leads | 17.53 mm | 25.15 mm | 30.23 mm |
Table 5. Thermal resistance and body size across the PLCC family, from the Xilinx packaging and thermal characteristics databook. The 25.15 mm figure for PC68 agrees with the 25.02 mm to 25.27 mm lead-tip span in Table 1.
A worked example. A 0.9 W device in a PLCC-68 at 55 °C ambient, still air, at the typical 41.9 °C/W: the junction rises 37.7 °C, giving a junction temperature near 92.7 °C. Add 250 LFM of airflow and the same device runs at 31.6 °C/W, a 28.4 °C rise and roughly 83.4 °C junction. Against a 125 °C rating both pass; against an 85 °C industrial junction limit the still-air case does not.
Two caveats apply. These figures were measured socketed, so a directly soldered part on a board with copper under the lands will do somewhat better. And θJA is a comparison metric measured on a standard test board, useful for first-order sizing rather than for signing off a thermal design.
When PLCC-68 is still the right choice
For a new design, almost never. The package burns 28 mm square of board for 68 connections, has worse thermal resistance than the larger PLCC-84, and draws on a shrinking supply of legacy silicon. A QFP or QFN delivers the same pin count in a fraction of the area.
Three cases still justify it. Field-replaceable programmable logic or firmware, where the socket is the requirement and the package is incidental. Sustaining engineering on an existing board, where the footprint is fixed. And low-volume instrumentation, where the ability to hand-place, hand-solder and inspect at 10× magnification outweighs density.
The decision path is short. If the part must be removable in the field, socket it and budget 31.50 mm square plus 4.40 mm of height. If it is fixed, solder it directly and recover 2.5 mm per side and the contact resistance. If neither the footprint nor the device is locked, move to a QFP or QFN and stop paying for the package.
Failure modes worth designing against
- Hidden solder joints. The J-lead foot curls under the body, so the joint is only partly visible. IPC-A-610 defines maximum side overhang, minimum side joint length and minimum fillet height for J-lead terminations, with tighter Class 3 limits. Angled optics or X-ray verify these; a top-down camera does not.
- Popcorning. The molded body absorbs moisture. Classify to J-STD-020 and observe the floor life and bake conditions in J-STD-033 before reflow, particularly for stock that has been sitting in a drawer since the last build.
- Bridging on the trailing edge in wave solder. Use the published wave footprint with its solder thief, or move the part to reflow.
- Contact degradation in sockets. Tin-plated contacts fret and oxidize under thermal cycling and vibration. Gold plating is the mitigation where the signal levels are low or the service life is long.
- Lead deformation during extraction. Prying without the proper tool bends the J-leads on one side, and the resulting intermittent is difficult to find because it reappears only after reinsertion.
- Silkscreen drawn to the body dimension. The outline needs the 25.27 mm lead-tip maximum, not the 24.33 mm body maximum.
Availability, lifecycle and counterfeit risk
Devices in this package are mostly legacy. Zilog’s Z80180 and Z8S180 microprocessors are documented in 68-pin PLCC alongside 64-pin DIP and 80-pin QFP, and the Z8S18020VSG is still catalogued at DigiKey. The Western Design Center W65C134S carries a 68-lead PLCC pinout in a datasheet revised 18 March 2024, which makes it one of the few actively supported parts in the package. Intel 80C186 and 80C196 variants in PLCC-68 are long obsolete and dominate the open-market listings.
Sockets are thinning too. The 3M 8468-21B1 series carries a last-time-buy date of 31 March 2026 at DigiKey, though stock remains against that. Adam Tech, Winslow, Preci-Dip and E-TEC still list active PLCC-68 sockets, so a design that specifies 3M by part number should qualify a second source now rather than at the next build.
Obsolete packages attract counterfeits, and PLCC-68 has the two features that make remarking easy: a large flat top surface and buyers who cannot test the part in system. Buy through authorized distribution while the part still exists there. Otherwise require a distributor working to SAE AS6081, which since Revision A in April 2023 points to the AS6171 test methods. OEM-side systems fall under AS5553.
[IMAGE 3: side-by-side comparison of a directly soldered PLCC-68 land pattern and the same device in a through-hole socket, with board area and height annotated | alt: “PLCC-68 socket versus direct solder showing board area and height penalty”]
Frequently asked questions
How many pins does a PLCC-68 have on each side?
Seventeen per side, on all four sides, at a 1.27 mm pitch. The top edge carries pins 61 through 68 followed by pins 1 through 9, the left edge carries 10 through 26, the bottom edge 27 through 43, and the right edge 44 through 60.
Where is pin 1 on a PLCC-68 package?
At the center of the beveled edge, viewed from the top. Numbering then runs counterclockwise. Pin 1 is the ninth position from either end of that 17-lead edge, so the bevel, not a corner dot, is the orientation feature to trust.
What are the PLCC-68 dimensions in inches?
The body is 0.950 in to 0.958 in square with a seated height of 0.165 in to 0.180 in, and lead tips span 0.985 in to 0.995 in. Lead pitch is 0.050 in. JEDEC defines the outline in inches, so these are the controlling values.
Do I need a socket, or can I solder a PLCC-68 directly?
Both are supported by the same package. Solder directly for fixed parts and save about 2.5 mm per side plus 4.4 mm of height. Socket it when the device is programmed off-board, replaced in the field, or heat sensitive during reflow.
Is PLCC-68 the same as QFJ-68 or LCC-68?
PLCC and QFJ describe the same quad J-leaded plastic body; vendors differ in naming, and Infineon files the outline as PG-LCC-68-800. A leadless ceramic chip carrier is a different part with castellated terminations and no J-leads, and it is not interchangeable.
Can a PLCC-68 be hand-soldered?
Yes, with a fine tip and flux, though the J-lead foot sits under the body so the joint cannot be fully seen. Drag soldering works on the exposed portion of the land. Verify with angled optics; a top-down check will pass joints that have not wetted under the foot.
What to do next
Pull the SOT188-2 outline and check your library footprint against three numbers: 1.27 mm pitch, 20.32 mm between end lead centers per side, and a 25.27 mm keep-out. If any disagree, fix the footprint before the board goes out.
Then make the socket call explicitly rather than by inheritance. Socket the part if it will be reprogrammed or replaced in service, and specify the gold-plated option with a qualified second source. Solder it directly otherwise. If the footprint is not yet fixed, specify a QFP or QFN and treat PLCC-68 as a sustaining-engineering package.
