Pango FPGA is the programmable-logic line from Shenzhen Pango Microsystems, China’s largest domestic FPGA vendor, spanning five families: Compa CPLDs, the cost-optimised Logos and Logos-2 FPGAs, the high-performance Titan and Titan-2 FPGAs, the Kosmo-2 ARM-plus-FPGA SoPC, and — as of 1 July 2026 — the 12 nm FinFET Titan-3. If you are here to buy one, three things will decide your project: the part number you pick, the ball pitch it arrives in, and whether your line can put a 900-ball BGA down without voiding it. This guide covers all three, with the complete part list, real price anchors, and an honest read on which Pango devices genuinely drop into a Xilinx footprint and which ones do not.
Key takeaways
- Five families in production: Compa (1K–10K LUT4 CPLD), Logos (12K–102K LUT4), Logos-2 (27K–233K LUT4), Titan-2 (90K–390K logic cells) and Kosmo-2 (dual Cortex-A53 SoPC). Titan-3 launched July 2026 at up to 1,500K logic cells on 12 nm FinFET.
- Pango’s own cross-reference lists PGL25G, PGL50G, PGL50H, PG2L100H and PG2T390H as pin-to-pin replacements for specific Spartan-6, Artix-7 and Kintex-7 devices. It states plainly that PGL12G, PGL22G and PGT180H are not.
- Packages run from 0.4 mm-pitch WLCSP to 1.0 mm-pitch 35×35 mm BGAs. Pitch, not price, is what sets your PCB class and most of your board cost.
- A mainstream 27K-LUT Logos device lands around $6.50 to $9.50 depending on quantity; distributors generally position Pango at 60–80% of the comparable international part.
- Every Pango BGA in volume is a moisture-sensitive, X-ray-mandatory device. MSL handling and IPC-A-610 void limits belong in the plan before the purchase order, not after.
What Is a Pango FPGA, and Who Actually Makes It?
A Pango FPGA is a field-programmable gate array designed by Shenzhen Pango Microsystems Co., Ltd. (Pango Microsystems), founded in December 2013 and headquartered in Nanshan District, Shenzhen, with R&D and sales offices in Shanghai, Beijing and Chengdu. The company sits inside the New Unigroup semiconductor group and is an affiliate of listed chipmaker Ziguang Guowei. Its own product selection guide puts headcount above 600 with roughly 90% in R&D, close to 300 patents, RMB 500 million in registered capital and over RMB 4 billion invested.
The track record matters more than the corporate structure. Pango shipped PGT180H in September 2016, the first 180K-logic-element device designed in China. The Logos family followed in October 2017, 28 nm Logos-2 entered production in 2020, and the Compa CPLD family arrived in October 2021. Revenue crossed RMB 100 million in 2019 and RMB 700 million by 2021, with industry press putting 2023 above RMB 1.95 billion. The company filed for A-share IPO coaching in April 2025 and completed its third coaching phase in January 2026.
Two consequences follow for anyone buying. Pango is a chip vendor, not a reseller, so a search for a Pango distributor is really a search for an authorised channel — Pango maintains a distributor and IDH partner network rather than an online storefront. And the toolchain is entirely its own.
Pango Design Suite (PDS) is the only way to build a bitstream for a Pango device. There is no Vivado or Quartus path. PDS runs the full flow — RTL entry, synthesis, device mapping, place and route, timing analysis, power estimation, bitstream generation and configuration download — and its documentation states it currently handles designs up to the 1000K-LE level. It works with third-party simulators, and its IP compiler covers DDR3 and DDR4, PCIe 2.0 and 3.0, 10G EMAC, SGMII, QSGMII, Interlaken, JESD204B, MIPI with a hardened D-PHY, HDMI, SDI and a Cortex-M1 soft core.
Honestly, engineers coming from Vivado tend to describe PDS as closer in feel to the previous-generation ISE flow. It closes timing and it runs fast. The IP catalogue is thinner than AMD’s and third-party IP for it is scarce. Budget the engineering time rather than pretending the gap is not there.
Pango FPGA Series Compared: Compa, Logos, Titan and Kosmo
Pango covers CPLD through high-end FPGA with five families. The table below is the fastest way to land in the right one before you start reading datasheets.
| Family | Process | Logic capacity | Key hard IP | Max transceiver | Where it fits |
| Compa (CPLD) | 55 nm eFlash | 1,276–9,907 LUT4 | Non-volatile, dual-boot with no external flash, user flash memory, RAM SEU correction | None | Board management, power-on sequencing, I/O expansion and bridging |
| Logos | 40 nm | 12,480–102,451 LUT4 | DDR3 800 Mbps, 12-bit ADC, AES-256; PCIe Gen2 x4 on 50H/100H only | 4–8 lanes at 6.375 Gbps (H parts only) | High-volume, cost-sensitive industrial and video |
| Logos-2 | 28 nm | 26,700–232,800 LUT4 | DDR3 1066 Mbps, PCIe Gen2 x4, 12-bit/1 MSPS ADC, AES-256, RAM SEU correction | 4–16 lanes at 6.6 Gbps | Mainstream production: machine vision, medical imaging, test and measurement |
| Titan (legacy) | 40 nm | Up to 180K LUT4 (PGT180H) | DDR3 800 Mbps, PCIe Gen2 x4 | 3 lanes at 5 Gbps | Older comms designs. No foreign-device compatibility was designed in |
| Titan-2 | 28 nm | 90K–390K logic cells | DDR4 1866 Mbps, PCIe Gen3 x8, SEU detection and correction, AES-256 | 8–16 lanes at 13.125 Gbps | Comms, instrumentation, 4K video, network security |
| Titan-3 | 12 nm FinFET | Up to 1,500K logic cells | PCIe Gen4 hard core, DDR4, multi-rate EMAC hard cores, HRM+DRM on-chip memory | High-rate SerDes | Data centre, next-generation comms, network security |
| Kosmo-2 | 28 nm | PG2K100 / PG2K400 | Dual-core ARM Cortex-A53 to 1 GHz, PCIe Gen3 x8, AXI interconnect | Up to 16 HSSTHP lanes | SoPC: ADAS, machine vision, industrial HMI |
Titan-3 is the news. Pango launched it at electronica Shanghai on 1 July 2026 as the first domestically designed 100-million-gate-class FPGA on a 12 nm FinFET process, in two devices — PG3T1300 and PG3T1500 — alongside a PG3T1300 accelerator card carrying four 25G optical ports on a PCIe 4.0 x8 interface in a single-slot, full-height half-length card.
Here is the truth about that launch, though: if your program ships next quarter, Titan-3 is not the part you design in. Mainstream Logos-2 and Titan-2 silicon has years of production history, a distributor network that can quote it, and reference designs you can actually get hold of. A sixth family, Visto-3, is still in development for very large-scale work such as SoC prototyping and EDA emulation acceleration. Treat it as a roadmap item, not a BOM line.
The Full Pango FPGA List: Part Numbers, Resources and Packages
Every number below comes from Pango’s own product selection guide. Read the package column before you read anything else — it is the one engineers skip and pay for two months later.
Logos Family (40 nm)
| Part number | Equivalent LUT4 | Block RAM (Kbit) | APM (DSP) | Max user I/O | Transceivers | Packages (body, pitch) |
| PGL12G | 12,480 | 540 | 20 | 160 | None | LPG144 (22×22 mm, 0.5 mm); FBG256 (17×17 mm, 1.0 mm) |
| PGL22G | 21,043 | 864 | 30 | 240 | None | FBG256 (17×17 mm, 1.0 mm); MBG324 (15×15 mm, 0.8 mm) |
| PGL22GS | 21,043 | 864 | 30 | 140 | None | LPG176 (22×22 mm, 0.4 mm) |
| PGL25G | 27,072 | 1,080 | 40 | 308 | None | FBG256; MBG324; FBG484 (23×23 mm, 1.0 mm) |
| PGL50G | 51,360 | 2,412 | 84 | 341 | None | FBG484 (23×23 mm, 1.0 mm) |
| PGL50H | 51,360 | 2,412 | 84 | 304 | 4 at 6.375 Gbps | FBG484 (23×23 mm, 1.0 mm) |
| PGL100H | 102,451 | 5,148 | 188 | 498 | 8 at 6.375 Gbps | FBG900 (31×31 mm, 1.0 mm) |
All Logos parts support DDR3 at 800 Mbps and LVDS at 800 Mbps. PGL50H and PGL100H add a PCIe Gen2 x4 hard core. PGL12G and PGL22G integrate the ADC hard core; the larger Logos parts do not.
Logos-2 Family (28 nm)
| Part number | Equivalent LUT4 | Block RAM (Kbit) | APM (DSP) | Max user I/O | Transceivers | Packages (body, pitch) |
| PG2L25H | 26,700 | 1,980 | 80 | 150 | 4 at 6.6 Gbps | SBG236 / SBG238 (10×10 mm, 0.5 mm); FBG256; MBG324 / MBG325 (15×15 mm, 0.8 mm) |
| PG2L50H | 53,700 | 3,060 | 120 | 250 | 4 at 6.6 Gbps | MBG324 / MBG325; MBB484 (19×19 mm, 0.8 mm); FBG484 / FBB484 (23×23 mm, 1.0 mm) |
| PG2L100H | 99,900 | 5,580 | 240 | 300 | 8 at 6.6 Gbps | MBG324; FBG484 / FBB484; FBG676 / FBB676 (27×27 mm, 1.0 mm) |
| PG2L200H | 232,800 | 14,940 | 740 | 500 | 16 at 6.6 Gbps | FBG676 / FBB676; FFBG1156 (35×35 mm, 1.0 mm) |
Every Logos-2 device carries a PCIe Gen2 x4 hard core, a 12-bit 1 MSPS ADC, 256-bit AES bitstream encryption, RAM soft-error detection and correction, and DDR3 at 1066 Mbps. Pango states that FBG484 and FBB484 are pin-to-pin compatible with each other, as are FBG676 and FBB676 — useful if you want a single footprint that can take two supply variants.
Titan-2 Family (28 nm)
| Part number | Logic cells | Block RAM (Kbit) | APM (DSP) | Max user I/O | Transceivers | Packages (body, pitch) |
| PG2T90H | 90K | 5,400 | 240 | 300 | 8 at 13.125 Gbps | FBB484 (23×23 mm, 1.0 mm); FBB676 / FFBG676 (27×27 mm, 1.0 mm) |
| PG2T210H | 210K | 12,240 | 600 | 400 | 8 at 13.125 Gbps | FBB676 / FFBG676 (27×27 mm); FFBG900 (31×31 mm, 1.0 mm) |
| PG2T390H | 390K | 17,280 | 840 | 500 | 16 at 13.125 Gbps | FFBG676 (27×27 mm); FFBG900 (31×31 mm, 1.0 mm) |
Titan-2 adds DDR4 at 1866 Mbps, a PCIe Gen3 x8 hard core, LVDS to 1.4 Gbps and a 12-bit 1 MSPS ADC across the family. FBB676 and FFBG676 are pin-to-pin compatible with each other.
Compa CPLD Family (55 nm eFlash)
| Part number | Equivalent LUT4 | Block RAM (Kbit) | User flash (bits) | PLL | Max user I/O | Packages (body, pitch) |
| PGC1K | 1,276 | 63 | 350 | 1 | 207 | UWG36 (2.5×2.5 mm, 0.4 mm); LPG100 (14×14 mm); LPG144 (20×20 mm); MBG256 (14×14 mm, 0.8 mm); FBG256 (17×17 mm, 1.0 mm) |
| PGC2K | 2,428 | 72 | 80 | 2 | 207 | UWG49 (3.2×3.2 mm, 0.4 mm); SSBG256 (9×9 mm, 0.5 mm); LPG100; LPG144; MBG256; FBG256 |
| PGC4K | 4,761 | 99 | 1,520 | 2 | 280 | UWG81 (3.8×3.8 mm, 0.4 mm); SSBG256; LPG144; MBG256; MBG324 (15×15 mm, 0.8 mm); FBG256 |
| PGC7K | 7,104 | 234 | 2,070 | 2 | 336 | LPG144; MBG256; MBG400 (17×17 mm, 0.8 mm); FBG484 (23×23 mm, 1.0 mm) |
| PGC10K | 9,907 | 405 | 3,016 | 2 | 384 | MBG484 (19×19 mm, 0.8 mm) |
Compa is non-volatile eFlash, so it boots instantly with no external configuration flash — which is exactly why it ends up doing power sequencing and board management alongside a larger FPGA. Note that the UWG and SSBG packages exist only on the 1.2 V low-power variants. Two devices carry automotive qualification: PGL25G-6AFBG256 in the Logos family and PG2L50M-5AMBG256 in Logos-2 have both passed AEC-Q100 Grade 2, which covers ambient operation from -40 °C to +105 °C.
How to Read a Pango FPGA Part Number
Take PG2L100H-6IFBG676. It decodes into six fields, and getting any of them wrong will cost you a build.
- PG — the Pango prefix. Every device starts with it.
- 2L — the family. C is Compa CPLD, L is Logos, 2L is Logos-2, 2T is Titan-2, 2K is Kosmo-2, 3T is Titan-3.
- 100 — logic capacity in thousands. 100 corresponds to 99,900 equivalent LUT4.
- H — the variant letter. On Logos, Logos-2 and Titan-2, H means the device has high-speed serial transceivers and G means it does not. On Logos there is also GS, which adds SDRAM support. On Compa, G is general, L is low-power and D is dual-boot.
- 6 — the speed grade. 5 is low, 6 is mid, 7 is high. Most volume parts in the channel are -6.
- I — the temperature grade. C is commercial, I is industrial, A is automotive.
- FBG676 — the package. The leading letter is the ball pitch: S is 0.5 mm, M is 0.8 mm, F is 1.0 mm, and FF is a fine-pitch 1.0 mm variant on the larger bodies. LPG is an LQFP, UWG is a wafer-level CSP. The number is the ball or lead count.
The variant letter is not cosmetic. PGL50G and PGL50H have identical logic, block RAM and DSP resources and sit in the same FBG484 package. The G has zero transceiver lanes. The H has four at 6.375 Gbps plus a PCIe Gen2 x4 hard core. Buy the wrong letter and your SerDes design has nowhere to land.
The temperature grade is junction temperature, not ambient. Pango specifies commercial as Tj 0 °C to +85 °C and industrial as Tj -40 °C to +100 °C. That is the die, not the air around it. On a PG2T390H in a 31×31 mm FFBG900 running sixteen transceiver lanes, the die-to-ambient delta under a modest heatsink runs 25–35 °C. Specify the -C part for a fanless industrial enclosure and you can be out of spec at 55 °C ambient while the datasheet still reads 85. Default to -I unless someone has actually done the thermal math.
Pango FPGA vs Xilinx and Altera: What Actually Drops In
Pango publishes a cross-reference table stating exactly which of its devices were designed as footprint-compatible replacements for AMD/Xilinx, Altera and Lattice parts, and which were not. It is the most useful document the company produces and almost nobody quotes it.
| Pango device | Closest AMD/Xilinx or Lattice part | Pango’s own compatibility claim |
| PGL25G | XC6SLX25 (Spartan-6) | Pin-to-pin compatible |
| PGL50G | XC6SLX45 (Spartan-6) | Pin-to-pin compatible |
| PGL50H | XC6SLX45T (Spartan-6 LXT) | Pin-to-pin compatible |
| PG2L100H | XC7A100T (Artix-7) | Compatible — pin-to-pin |
| PG2T390H | XC7K325T (Kintex-7) | Pin-to-pin compatible |
| PGC1K to PGC10K | Lattice MachXO3 (XO3LF-1300 to XO3LF-9400) | Pin-to-pin compatible — direct replacement |
| PGL12G | XC6SLX9 (Spartan-6) | Function replacement only — not pin compatible |
| PGL22G / PGL22GS | No Xilinx equivalent claimed | Function replacement only — no compatibility designed in |
| PGT180H | XC6SLX150T / EP4CGX150 | Function replacement only — no compatibility designed in |
| All Altera equivalents | Cyclone-IV, Cyclone-V, MAX10 | Function replacement only — different pinout and SerDes count |
Two lines in that table deserve a second look.
The most popular Pango part on dev boards is the one Pango says will not drop in. PGL22G is the device on half the training boards in China, so it is the part most engineers reach for first. Pango’s own cross-reference is blunt: PGL12G and PGL22G were designed without compatibility for foreign competitors and cannot be directly replaced. If you are migrating a Spartan-6 design, the parts actually designed to drop in are PGL25G, PGL50G and PGL50H — and on every headline resource, they meet or beat the Spartan-6 they replace. PGL25G brings 27,072 LUT4 against the XC6SLX25’s 24,051, and 308 user I/O against 266.
The second is what pin-to-pin compatibility actually buys you. It is a statement about the land pattern and the pin map, and that is a real thing worth having. A PG2T390H in FFBG900 and an XC7K325T in FFG900 are both 31×31 mm, 1.0 mm pitch, 30-by-30 ball arrays on the same 1.0 V core rail. Your footprint, your stencil aperture set, your placement program and your reflow profile all carry over unchanged.
What does not carry over is everything above the copper. Bitstream format, configuration flow, JTAG chain, DDR controller calibration, I/O bank rules and the transceiver primitive set are all different. Every RTL block gets re-synthesised in PDS, every hard-IP instantiation gets swapped, and every timing constraint gets rewritten. Teams that budget a BOM change for that are the teams that slip.
The trade-off, stated plainly: the die is cheaper and the lead time is shorter, but the engineering is not free. A realistic port of a mid-size Artix-7 design to PG2L100H runs weeks, most of it spent re-verifying DDR3 timing and the SerDes link rather than rewriting logic. If a supply-chain mandate is driving the decision, that is simply a cost of doing business. If BOM cost alone is driving it on a design that already works, do the arithmetic first: at 5,000 units, a $4 per-unit saving is $20,000, which is a handful of engineer-weeks. It can easily be a wash.
Pango FPGA Price and How to Buy: Distributors, Stock and Lead Times
What a Pango FPGA Actually Costs
Pango pricing is quoted rather than listed, so treat the numbers below as anchors, not a price list. A PGL25G-6IMBG324 — 27,072 LUT4, industrial grade, 324-ball 15×15 mm package — prices at a major assembly house’s component library as follows.
| Quantity | Unit price (PGL25G-6IMBG324) |
| 1 piece | $9.32 |
| 10 pieces | $8.01 |
| 30 pieces | $7.21 |
| 100 pieces | $6.54 |
| Full reel | 1,000 pieces |
That puts a mainstream 27K-LUT Logos device in the same neighbourhood as a small Artix-7 and comfortably below it at volume. Distributors typically position Pango at 60–80% of the comparable international device, and the 2025–2026 run-up in international FPGA pricing has widened that gap in Pango’s favour at the low end.
If you are budgeting a bring-up rather than a production BOM, module pricing is a cleaner signal.
| System-on-module (Pango device) | Approximate price |
| P22 (PGL22G) | $46 |
| P25G (PGL25G) | $47 |
| P50G (PGL50G) | $79 |
| P50 (PGL50H) | $125 |
| P100 (PG2L100H) | $129 |
| P200 (PG2L200H) | $153 |
Complete development boards run from roughly EUR 105 for a PGL12G kit to EUR 620–730 for a PG2T390H Titan-2 or Kosmo-2 PG2K400 platform.
How to Buy a Pango FPGA Without Getting Burned
- Fix the full part number first, all six fields. A PGL25G-6C and a PGL25G-6I are different devices in every way that matters to a qualification report, and they look identical in a tray.
- Apply for the PDS license before you commit the BOM. It comes through Pango or a distributor and it is not instant. Build your RTL against the target device once, in PDS, and confirm it fits and closes timing before anyone raises a purchase order.
- Go through an authorised channel. Pango maintains a distributor and IDH partner list, and those are the parties who can also supply samples, reference designs and FAE support. FPGAs are among the most counterfeited components in electronics — remarked speed grades, remarked temperature grades and devices harvested from e-waste all circulate.
- Ask for the paperwork. Date code, unbroken moisture barrier bag, fresh humidity indicator card, desiccant, and a lot number that matches the label on the reel or tray. If a broker cannot produce those, walk away.
- Confirm the packaging format. Full reel is typically 1,000 pieces and larger BGAs ship in trays. If you are building 200 boards you are buying a cut reel or a partial tray, and the per-piece price reflects that.
- Get the lead time in writing. Distributors have been quoting Pango in the region of 12–16 weeks against 40 weeks or more for some international parts, but a stock screen is not a lead time and a lead time is not a delivery date.
An honest note on stock, because the “in stock” filters mislead: on the day this article was written, a mainstream Logos device sat at zero in-house stock in a major assembly house’s own component library while remaining fully orderable on lead time. That is entirely normal for FPGAs. If your schedule depends on a specific date code landing in a specific week, buy it against a purchase order and a written commitment, and let your component sourcing partner carry the incoming inspection.
Pango FPGA PCB Assembly: What the BGA Actually Demands
The FPGA is usually not the expensive decision. The package is — and this is the part of a Pango design that never appears in a datasheet comparison.
Ball Pitch Decides Your PCB Class
| Ball pitch | Example Pango packages | What the PCB build actually needs |
| 1.0 mm | FBG256 (17×17), FBG484 (23×23), FBG676 / FBB676 (27×27), FFBG900 (31×31), FFBG1156 (35×35) | Conventional dogbone fanout. 0.20–0.25 mm mechanical drills, 0.45–0.50 mm pads, 6–8 layers. Standard multilayer pricing. |
| 0.8 mm | MBG324 / MBG325 (15×15), MBB484 (19×19), MBG484 (19×19) | Tight dogbone or via-in-pad. Typically 8–10 layers, 0.15–0.20 mm drills, laser microvias on the outer layers. |
| 0.5 mm | SBG236 / SBG238 (10×10), SSBG256 (9×9) | HDI. Via-in-pad with resin fill and copper cap, 1+N+1 build minimum, laser microvias throughout. Bare-board cost steps up hard. |
| 0.4 mm | UWG36 / UWG49 / UWG81 WLCSP, LPG176 LQFP | HDI for the WLCSP; fine-pitch stencil and paste control for the LQFP. |
The smallest package is the expensive one. A 31×31 mm FFBG900 Titan-2, for all its 900 balls, is a well-behaved 1.0 mm-pitch part that any competent line will fan out on a conventional 8-layer stack-up. A 10×10 mm SBG236 Logos-2 — a part chosen precisely to keep a board small — is 0.5 mm pitch and drags you straight into HDI: via-in-pad, resin fill, copper cap, laser microvias, a 1+N+1 build minimum. Pick the die for the logic and you can find you have picked the fabrication class along with it.
We have watched this go the same way more than once. A machine-vision customer selected the SBG236 package for a compact camera head because the die was a few dollars cheaper than the equivalent MBG324 option in the same family. The 0.5 mm pitch forced a via-in-pad HDI build, the bare-board price more than doubled at 500 pieces, and the assembly process needed two iterations before yield settled. At their volume, the package choice cost several times what the die choice saved. The fix would have taken ten minutes at schematic stage: read the pitch column before the price column.
Moisture, Reflow and the 168-Hour Clock
Every Pango BGA is a moisture-sensitive device. The PGL25G-6IMBG324 is rated MSL 3 under IPC/JEDEC J-STD-020, which means 168 hours of cumulative floor life at 30 °C and 60% relative humidity once the moisture barrier bag is opened. That clock is cumulative — putting the reel back on a shelf does not reset it. Once it runs out, J-STD-033 requires a bake, and J-STD-033 caps cumulative bake time above 90 °C at 96 hours unless the manufacturer says otherwise.
A counterintuitive one: on a 23×23 mm or 31×31 mm BGA, use the thickness-based bake table rather than the thin-package column. There is far more organic substrate holding water in a large FPGA package than the ball count suggests, and an under-baked part will popcorn — trapped moisture flashing to steam above 200 °C, delaminating the substrate and displacing balls. It passes AOI, it passes functional test, and it fails in the field six months later.
Inspection, Power and Signal Integrity
BGA joints cannot be seen, so X-ray is not optional. One major assembly house flags X-ray inspection as required on the Pango part record itself. Under IPC-A-610, the Class 2 defect threshold for a BGA ball is a cumulative projected void area exceeding 25% of the ball’s image area in the X-ray image. IPC-7095, now at Revision E, is the BGA-specific design and assembly standard and goes considerably further, classifying voids by cause and by location. Location matters more than the headline percentage: a 24% void at the centre of a ball is usually benign, while a 15% void at the ball’s edge, where thermal-cycling stress concentrates, is the one that cracks.
On power, Pango’s 28 nm devices run a 1.0 V core and the 40 nm Logos parts run 1.1 to 1.2 V. Sequence core before I/O per the datasheet, keep the small decoupling capacitors directly under the BGA and the bulk capacitance outside it, and settle the stack-up before you route rather than adding layers afterwards. If you are running Titan-2’s 13.125 Gbps transceiver lanes, controlled impedance stops being a nice-to-have: 100 ohm differential on the lanes, ground stitching at every layer transition, and a laminate that will not eat the insertion-loss budget. Standard FR-4 gets expensive in decibels at those rates, and a mid-loss laminate such as Panasonic Megtron or Isola costs more per panel while buying back link margin you cannot recover any other way. Sort this out during PCB fabrication planning, not during debug.
Common Pango FPGA Mistakes and a DFM Checklist
Send this section to whoever on your team is doing the selection. It is the list of things that go wrong.
- Reading the temperature grade as ambient. C is a junction temperature of 0 to +85 °C. Your enclosure specification is not the datasheet’s specification.
- Assuming PGL22G is a Spartan-6 drop-in. Pango’s own cross-reference says it is not. PGL25G, PGL50G and PGL50H are.
- Reading pin-to-pin compatible as bitstream compatible. Same footprint, entirely different toolchain, IP set and constraints.
- Ignoring the G versus H letter. PGL50G has zero transceivers, PGL50H has four, and they share a package.
- Choosing the small package to shrink the board, then discovering that 0.5 mm pitch means HDI and a doubled bare-board price.
- Committing the BOM before you have a PDS license and one clean build against the target device.
- Specifying a device that exists only in a package you cannot afford to fabricate. PGL100H ships in FBG900 (31×31 mm) and nothing else.
- Treating a stock screen as a lead time, and a lead time as a delivery date.
- Skipping X-ray because the board powers up. Voids and head-in-pillow defects pass functional test and fail in year two.
Five things you can do on Monday
- Open Pango’s cross-reference table and confirm your target device sits on the pin-to-pin list, not the functions-replacement list.
- Apply for the PDS license today, then get one clean build of your existing RTL against the target device before anything else happens.
- Read the package pitch column before the price column. It is the single number that decides your PCB class.
- Default to the -I industrial grade unless someone has run the junction-temperature numbers for your enclosure.
Send the BOM and Gerbers for a DFM review with the BGA fanout strategy, stack-up and impedance targets called out explicitly, before you release the layout.
Frequently Asked Questions About Pango FPGA
Is Pango FPGA the same as Ziguang Tongchuang?
Yes. Pango Microsystems is the English name of Shenzhen Ziguang Tongchuang Electronics, founded in December 2013 and headquartered in Shenzhen. It sits within the New Unigroup semiconductor group and is an affiliate of the listed company Ziguang Guowei. The product names — Titan, Logos, Kosmo, Compa — are identical in both markets.
Can I use Vivado or Quartus with a Pango FPGA?
No. Pango devices build only in Pango Design Suite, the company’s own toolchain, which runs the full flow from RTL through synthesis, place and route, timing analysis and bitstream generation. PDS works with third-party simulators. Plan a toolchain migration, not a plug-in.
Is Pango Design Suite free?
PDS is distributed under a license you apply for through Pango or an authorised distributor rather than downloading unconditionally. Licenses are routinely issued to design-in customers at no charge, but the application is a step in your schedule. Complete it before you commit your BOM, not after.
Which Pango FPGA replaces a Xilinx Artix-7?
PG2L100H is Pango’s declared replacement for the XC7A100T: 99,900 equivalent LUT4 against 95,100, matching 240 DSP slices, matching 300 user I/O, DDR3 at 1066 Mbps and eight transceiver lanes at 6.6 Gbps, in matching 15×15 mm, 23×23 mm and 27×27 mm packages.
What is the largest Pango FPGA?
As of July 2026 it is the Titan-3 series — PG3T1300 and PG3T1500, built on a 12 nm FinFET process and reaching 1,300K and 1,500K logic cells, with PCIe Gen4 hard cores, DDR4 and multi-rate EMAC hard cores. Before Titan-3, the ceiling was PG2T390H at 390K logic cells.
Are Pango FPGAs automotive qualified?
Some are. PGL25G-6AFBG256 in the Logos family and PG2L50M-5AMBG256 in Logos-2 have both passed AEC-Q100 Grade 2, covering ambient operation from -40 °C to +105 °C. The rest of the catalogue is commercial or industrial grade. Check the temperature letter in the part number: A is the automotive code.
What is the minimum order quantity for a Pango FPGA?
There is no universal MOQ, but the practical unit is the packaging. A full reel is typically 1,000 pieces and larger BGAs ship in trays. Below reel quantity you are buying a cut reel or a partial tray and the per-piece price rises accordingly. Prototype volumes are normally handled through a distributor or an assembly partner.
Do Pango FPGAs support PCIe Gen4 and DDR4?
Titan-2 supports DDR4 at up to 1866 Mbps with a PCIe Gen3 x8 hard core. PCIe Gen4 arrives with Titan-3 (PG3T1300 and PG3T1500), which also carries DDR4 and multi-rate EMAC hard cores. Logos and Logos-2 top out at DDR3 and PCIe Gen2 x4.
Getting Your Pango FPGA Design Quoted and Built
Choosing a Pango FPGA is really three decisions stacked on top of each other, and they get made in the wrong order almost every time. Engineers pick the logic capacity first, the price second, and discover the package third — by which point the stack-up, the fabrication class, the assembly process and a large slice of the board cost have already been decided for them by a letter in the part number.
Reverse it. Start with the ball pitch, because that sets your PCB class. Then check Pango’s own compatibility table, because it will tell you honestly which devices were designed to land in your existing footprint and which were not. Then price it — the board, not just the die. A Pango FPGA supplier who only quotes you silicon is quoting you half the problem.
Send us your Gerbers and BOM and we will come back with a DFM review and a quote covering the bare board and the PCB assembly of the Pango BGA together.
