The package sets three things the silicon cannot: how much heat you can pull out, how much parasitic inductance sits in series with your switching node, and how much board area you spend. This guide walks the full range of MOSFET package types, from the 3-lead SOT-23 that carries a few hundred milliwatts to the leadless TOLL that moves 300 A, with the thermal and parasitic numbers you need to choose one.
Key takeaways
- Package choice is a thermal and parasitic decision first, a footprint decision second — the die is often identical across packages.
- SOT-23 handles roughly a few hundred milliwatts; TOLL handles up to 300 A with a junction-to-case impedance near 0.65 °C/W (Diodes DMTH series).
- Clip-bonded power packages (LFPAK, PowerPAK, TOLL) cut package resistance and inductance versus wire-bonded SO-8.
- A Kelvin-source pin (TO-247-4, TOLL 4-pin) separates gate return from power current and cuts switching loss by up to ~8% (Infineon CoolMOS TO-247-4).
- TOLL shaves ~30% footprint and ~50% height versus D2PAK-7 while adding a 50% larger solder area against electromigration (Infineon).
- Match the second source by footprint and thermal resistance, not just by RDS(on) and voltage.
How a MOSFET package is actually defined
A MOSFET package is the die’s electrical, thermal, and mechanical interface to the board: the lead or terminal layout, the die-attach and interconnect method, and the exposed metal that carries heat out. Small-signal parts use gull-wing leads; power parts increasingly use exposed pads or tabs and a copper clip over the die.
The interconnect matters more than the outline. A wire-bonded SO-8 puts several bond wires in series with the source; a clip-bonded package replaces them with a solid copper strap, dropping both package resistance and source inductance. That single construction difference, documented in onsemi’s AND9137 power-SO8 study, is why two parts with the same die and outline can behave differently at high di/dt.
Small-signal packages: SOT-23 and the SOT family
SOT-23 (Small Outline Transistor) is the default for gate drivers, load switches, and logic-level FETs. The 3-lead body measures about 2.9 mm × 1.3 mm with a ~1.1 mm height and dissipates only a few hundred milliwatts, since its only heat path is the leads into the copper.
Infineon’s small-signal MOSFET line spans seven outlines from SOT-223 down to SOT-323, including SOT-89, SOT-363, and TSOP-6, in single, dual, and complementary configurations. Step up to SOT-223 when you need more pad area for ~1 W-class dissipation; drop to SOT-323 or SOT-363 when board space rules and currents stay in the sub-amp range.
| Package | Body (mm) | Leads | Typical use |
| SOT-323 (SC-70) | 2.0 × 1.25 | 3–6 | Sub-amp switches, dense boards |
| SOT-23 | 2.9 × 1.3 | 3–6 | Gate drivers, load switches |
| SOT-89 | 4.5 × 2.5 | 3 | ~1 W with pad heat-sinking |
| SOT-223 | 6.5 × 3.5 | 4 | Largest small-signal, ~1–2 W |
Sources: Infineon small-signal selection guide; Regent Electronics package dimensions.
Power SMD, tier one: SO-8, PowerPAK, LFPAK
The SO-8 footprint is the workhorse of low-voltage power — synchronous buck converters, battery paths, load switches. The classic wire-bonded SO-8 is now largely displaced by leadless clip-bonded versions that use the same 5 mm × 6 mm outline.
PowerPAK 5×6 replaces the leads with bottom-side terminals and an exposed drain pad, giving direct PCB heat transfer and sub-nH source inductance in a 1.0–1.75 mm profile (Vishay PowerPAK documentation). LFPAK (Nexperia) is the ruggedized version: it keeps flexible source and gate pins that absorb thermal-cycling stress, and it is the only Power-SO8 with AEC-Q101 automotive qualification called out for that ruggedness in Nexperia’s LFPAK leaflet. Where a QFN cracks under rapid ΔT, the LFPAK pin flexes.
Power SMD, tier two: DPAK and D2PAK
DPAK (TO-252) and D2PAK (TO-263) are the surface-mount descendants of TO-220. D2PAK is essentially a TO-220 with the leads formed for reflow and the tab turned into a solder pad; the copper pour under that tab is the heatsink.
The dissipation gap is real. As a rule of thumb from field practice, DPAK handles roughly 0.5 W and D2PAK roughly 1 W on typical pad areas, rising with copper. ST’s AN1703 puts the D2PAK junction-to-ambient at 62.5 °C/W in free air, matching a TO-220, and about 42 °C/W on a 120 mm² footprint. Vishay’s thermal study measured 16.6 K/W for a specific D2PAK MOSFET on a defined board — a reminder that board copper, not the package label, sets the real number.
Through-hole: TO-220 and TO-247, and the Kelvin-source TO-247-4
TO-220 remains the default for commercial and industrial power up to roughly 50 W of dissipation, prized for low thermal resistance and low cost (International Rectifier IRF640N datasheet). TO-247 is larger, handles 100 A-class currents and 600–1700 V devices, and takes a bigger heatsink more easily.
The upgrade worth knowing is the TO-247-4. Its fourth pin is a Kelvin source that separates the gate-driver return from the main source current, removing package source inductance from the gate loop. Infineon and ST both released it for CoolMOS; in a 1.2 kW CCM PFC it cut switching loss by up to 8%, worth about 5 W and 0.4% full-load efficiency versus the 3-pin TO-247. Toshiba’s TO-247-4L brings the same Kelvin benefit to its DTMOS super-junction line.
Leadless power: TOLL, TOLG, and TOLT
TOLL (TO-leadless) is the modern high-current SMD package. Infineon rates it to 300 A, with roughly 30% less footprint and 50% less height than D2PAK-7, combining to about 60% overall space saving. Its 50% larger solder contact area lowers current density and fights electromigration, and the leadless construction cuts parasitic inductance for cleaner EMI.
The numbers get specific at the part level. Diodes’ PowerDI 1012-8 TOLL MOSFETs hit typical RDS(on) of 1.3–1.68 mΩ at VGS = 10 V, occupy 20% less area than TO-263, stand just 2.4 mm tall, achieve a junction-to-case impedance of 0.65 °C/W, and handle up to 270 A — with 10 k-unit pricing quoted at $2.00–$2.36. Infineon’s OptiMOS TOLL reaches 0.4 mΩ at 30 V and 0.75 mΩ at 60 V.
Infineon splits the family three ways: TOLL (leadless, highest power density), TOLG (adds gullwing leads for ~2× better thermal-cycling-on-board robustness, good on aluminum IMS), and TOLT (top-side cooled, exposing the drain so ~95% of heat goes up to the heatsink for at least 20% better RθJA). For high-voltage super-junction parts, top-side-cooled DDPAK and QDPAK push the same idea into PFC and LLC stages.
MOSFET package comparison table
| Package | Type | Current / dissipation | RθJC or RθJA | Interconnect | Best for |
| SOT-23 | Small-signal SMD | ~0.2–0.5 W | RθJA high | Wire | Gate drivers, load switches |
| SOT-223 | Small-signal SMD | ~1–2 W | RθJA moderate | Wire | Larger small-signal |
| PowerPAK 5×6 | Leadless power SMD | tens of A | Low, <1 nH L | Clip | LV sync buck, portables |
| LFPAK | Leadless power SMD | tens of A | Low, rugged | Clip | Automotive LV, harsh ΔT |
| DPAK (TO-252) | Power SMD | ~0.5 W / mid-A | High w/o copper | Wire/clip | Cost-driven power |
| D2PAK (TO-263) | Power SMD | ~1 W / high-A | 62.5 °C/W air (ST) | Wire/clip | SMD power, big pours |
| TO-220 | Through-hole | to ~50 W diss. | Low (heatsink) | Wire | General power, easy heatsink |
| TO-247 / -4 | Through-hole | 100 A+, HV | -4 cuts loss ~8% | Wire | HV/high-I, hard-switching |
| TOLL | Leadless power SMD | up to 300 A | ~0.65 °C/W (Diodes) | Clip | High density, EV/POL |
| TOLT | Top-side cooled SMD | high-A | ≥20% better RθJA | Clip | Compact, heatsink-up |
What actually drives the choice
Thermal path first. Compute it. For a MOSFET dissipating P, the junction rise over case is P × RθJC. A TOLL at 0.65 °C/W dissipating 20 W sits about 13 °C over its case; hitting the same rise in a lead-limited SMD would need far more copper or a smaller loss budget. Then add case-to-heatsink and heatsink-to-ambient to check Tj stays under the 150–175 °C rating.
Parasitic inductance second. At high di/dt, source-lead inductance turns into a voltage that fights your gate drive and rings the switching node. Clip-bonded and leadless packages cut it structurally; a Kelvin pin removes it from the gate loop entirely. This is why hard-switching PFC and motor drives reach for TO-247-4 or 4-pin TOLL even when a 3-pin part is thermally adequate.
Then current and space. Above ~100 A, parallel D2PAKs give way to a single TOLL to cut count and RDS(on). In thin server or blade designs, TOLL’s half-height or TOLT’s heatsink-up cooling wins where a TO-247 physically will not fit.
A MOSFET package selection decision path
- Sub-amp control or switching, tight space → SOT-23 family; SOT-223 if you need ~1 W.
- Low-voltage, tens of amps, dense board (buck, battery) → PowerPAK 5×6 or LFPAK; clip-bonded for low inductance and thermal-cycling ruggedness.
- Mid-current SMD, cost-sensitive → DPAK for ~0.5 W, D2PAK for higher current with generous copper.
- High-voltage or high-current, easy heatsinking → TO-220 to ~50 W, TO-247 beyond; choose TO-247-4 for hard-switching efficiency.
- Very high current with SMD density, EMI-sensitive → TOLL; TOLG on aluminum IMS, TOLT when you can cool from the top.
Sourcing, second-source, and reliability
Match the footprint and RθJC, not just the electrical ratings. Two 60 V, 3 mΩ parts in different packages are not drop-in equivalents if one is D2PAK and the other TOLL — the pad, height, and thermal path differ.
For automotive and industrial, require AEC-Q101 qualification; TOLL and LFPAK carry it, and Diodes’ TOLL line is PPAP-capable from IATF 16949 facilities. Watch MSL on leadless power SMD (commonly MSL 3, per Vishay PowerPAK data) and bake if floor life is blown before reflow. Where JEDEC-standardized outlines exist — as Infineon notes for its top-side-cooled DDPAK/QDPAK — dual sourcing is far easier, so favor standardized packages for supply resilience.
Frequently asked questions
Which MOSFET package is best for high current?
For SMD, TOLL leads: Infineon rates it to 300 A and Diodes’ PowerDI 1012 TOLL handles up to 270 A with a 0.65 °C/W junction-to-case impedance. For through-hole, TO-247 remains the choice above 100 A where a large heatsink is available.
What is the difference between DPAK and D2PAK?
Both are surface-mount TO-derived packages. DPAK (TO-252) is smaller, about 65 mm², good for roughly 0.5 W. D2PAK (TO-263) is larger, near 150 mm², handles higher current and about 1 W, and needs a bigger copper pour to reach its rated thermal resistance.
What is a Kelvin source pin?
A fourth terminal that connects the gate driver’s return directly to the die source, bypassing the power-current path. It removes package source inductance from the gate loop, cutting switching loss — up to about 8% in a CCM PFC per Infineon’s TO-247-4 data.
Is TO-220 or TO-247 better?
TO-247 handles more current and voltage and dissipates more heat, so it wins for high-power or high-voltage stages. TO-220 is smaller and cheaper and is preferred up to roughly 50 W of dissipation where its thermal resistance and cost are the deciding factors.
What does SOT-23 stand for?
Small Outline Transistor, a 3-to-6-lead surface-mount package about 2.9 mm × 1.3 mm. It suits small-signal and logic-level MOSFETs dissipating a few hundred milliwatts, since heat leaves only through the leads into the board copper.
Bottom line
Start from the loss budget and the switching speed, not the parts catalog. If dissipation is milliwatts, a SOT package is right; if it is amps into tens of amps on a dense board, reach for a clip-bonded PowerPAK or LFPAK; if it is high current or high voltage, choose TO-247 (4-pin for hard switching) or, for SMD density and EMI, a TOLL-family part. Verify Tj with the real RθJC and your board copper, add a Kelvin pin wherever di/dt is high, and confirm AEC-Q101 and a matching-footprint second source before you release the layout.
