The HTSSOP-28 outline is standardized. Its thermal pad is not. Body size, lead pitch and lead span come from JEDEC MO-153-AET and match across vendors, but the exposed pad underneath runs from 2.24 mm to 3.10 mm wide and 4.48 mm to 6.90 mm long depending on the supplier and the drawing revision. Build the HTSSOP-28 land pattern from the wrong sheet and the thermal path you sized for is not there.
Key takeaways
- MO-153-AET fixes the 9.7 mm × 4.4 mm body, the 0.65 mm pitch and the 1.2 mm maximum height. It says nothing about the exposed pad.
- Texas Instruments ships two different 28-pin PowerPAD TSSOP drawings under the same PWP name. PWP0028C has a 5.18 mm × 3.10 mm maximum pad, PWP0028V has 5.62 mm × 2.94 mm.
- Size the solder mask opening to the maximum exposed pad on the device datasheet, not to the copper.
- Keep thermal via drills at 0.33 mm or below, and plug, fill or tent them from the component side.
- Print 50 percent to 80 percent paste coverage on the thermal land. A full-area aperture floats the part.
- Junction-to-case (bottom) on a 28-pin PowerPAD TSSOP is 1.4 °C/W. Almost everything else in the thermal budget is your board.
What MO-153-AET fixes and what it leaves open
HTSSOP is a vendor name for a thin shrink small outline package carrying an exposed die-attach pad on the bottom. Texas Instruments calls its version PowerPAD and uses the PWP package code. Renesas and Rohm reuse the HTSSOP name. Analog Devices and Microchip call the same construction a TSSOP with exposed pad. All of them point back to the same JEDEC registration.
An HTSSOP-28 has a 9.7 mm × 4.4 mm plastic body, 28 gull-wing leads on 0.65 mm pitch, a 6.4 mm nominal lead span and a 1.2 mm maximum seated height per JEDEC MO-153-AET. The exposed thermal pad on its underside is vendor specific and typically measures 4.5 mm to 6.9 mm long by 2.2 mm to 3.1 mm wide.
The rest of the dimensions are worth having in front of you. TI drawing PWP0028C gives a body 9.6 mm to 9.8 mm long and 4.3 mm to 4.5 mm wide, a lead span of 6.2 mm to 6.6 mm, lead width of 0.19 mm to 0.30 mm and foot length of 0.50 mm to 0.75 mm, with a 0.05 mm minimum seating-plane standoff. Renesas drawing M28.173C gives the same body with a 6.40 mm lead span and the same 1.20 mm maximum height.
Everything in that paragraph is interchangeable between suppliers. The pad is not.
[IMAGE 1: annotated bottom view of an HTSSOP-28 showing body outline, lead span, 0.65 mm pitch and the exposed thermal pad | alt: “HTSSOP-28 package bottom view with exposed thermal pad and land pattern dimensions labeled”]
Exposed pad size varies by vendor and by drawing revision
This is the most common HTSSOP-28 footprint error. Five current drawings for one outline specify five different pads.
Table 1. Exposed pad and thermal land geometry across five HTSSOP-28 / TSSOP-EP drawings
| Drawing | Pad length (mm) | Pad width (mm) | Mask opening (mm) | Notes |
| TI PWP0028C (4223582/A, 03-2017) | 4.48 to 5.18 | 2.40 to 3.10 | 5.18 × 3.10 | Copper in TI example is 9.7 × 3.4 |
| TI PWP0028V (4230409/A, 01-2024) | 4.92 to 5.62 | 2.24 to 2.94 | 5.62 × 2.94 | Same PWP name, different pad |
| Analog Devices RE-28-2 | 5.45 to 5.55 | 2.95 to 3.05 | Per device datasheet | Marked compliant to MO-153-AET |
| Renesas M28.173C (10-2023) | 6.80 ± 0.10 | 2.80 ± 0.10 | Land 6.80 × 2.80 ref | Largest pad of the five |
| Microchip C04-255A (28-lead TSSOP-EP) | 5.50 nominal | 3.00 nominal | 5.60 × 3.10 | Vias 0.33 mm on 1.20 mm pitch |
Two rows of that table are both Texas Instruments, both 28-pin PowerPAD TSSOP, both referenced to MO-153. PWP0028V is 0.44 mm longer and 0.16 mm narrower than PWP0028C. A footprint drawn from a 2017 datasheet and reused on a 2024 part ends up with a mask opening that overhangs the pad at the ends and undershoots it at the sides.
The fix is procedural rather than clever. Pull the mechanical drawing from the datasheet for the exact orderable part number, read the drawing number in the corner, and size the mask opening to the maximum pad on that sheet. TI states the rule plainly in SLMA002: design the solder mask defined pad to the maximum exposed pad size listed in the device datasheet.
Drawing the HTSSOP-28 land pattern
TI’s example board layout for PWP0028C gives 28 lead lands of 1.50 mm × 0.45 mm on 0.65 mm pitch, with 5.80 mm between the centres of the two rows. Those numbers hold across both PWP0028 revisions and sit close to what IPC-7351 generates for a 0.65 mm gull-wing package at nominal density.
The thermal land needs two separate geometries, and they are not the same size. Copper can be larger than the pad, and larger copper moves more heat. TI draws 9.7 mm × 3.4 mm of copper under the body and notes that the metal size may change to satisfy creepage. The solderable area is then set by a mask opening sized to the pad: 5.18 mm × 3.10 mm on PWP0028C, 5.62 mm × 2.94 mm on PWP0028V.
Use a solder mask defined thermal land with non-solder-mask defined lead lands. TI recommends the mask-defined centre pad specifically to prevent shorting between the exposed pad and the leads, which at 0.65 mm pitch sit close to the pad edge. Its example allows 0.05 mm of mask registration all around.
Add a fabrication note telling the board shop not to alter the centre mask opening. SLMA002 calls this out because a panel-level mask tweak will otherwise resize the one feature the whole thermal path depends on.
[IMAGE 2: HTSSOP-28 land pattern with the solder mask defined thermal land, NSMD lead lands and a 1.2 mm via grid | alt: “HTSSOP-28 land pattern showing solder mask defined thermal land and 0.2 mm thermal vias on a 1.2 mm grid”]
Thermal via design under the exposed pad
TI’s example pattern for the 28-pin PowerPAD TSSOP uses 0.2 mm finished vias on a 1.2 mm grid for PWP0028C and a 1.3 mm grid for PWP0028V. The drawing marks vias as optional by application and states that vias under paste should be filled, plugged or tented.
SLMA002 supplies the reasoning and the limits. A drill of 0.33 mm or smaller works with 1 oz plated copper without wicking excessive solder off the joint. For a small die, five to nine vias are adequate, and the published curves flatten quickly beyond that. Thermal relief spokes are prohibited under the pad, so connect each barrel to the plane with a full annulus.
If the vias are not plugged during plating, cap them with solder mask on the component side using an opening at least equal to the via diameter plus 0.1 mm. Tenting from the far side instead produces measurably more voiding in x-ray, because flux volatiles and trapped air have nowhere to escape.
Microchip’s land pattern C04-255A for its 28-lead TSSOP with a 5.5 mm × 3.0 mm exposed pad specifies 0.33 mm thermal vias on a 1.20 mm pitch and repeats the instruction to fill or tent them.
Stencil design and paste coverage
TI publishes aperture dimensions per stencil thickness on the HTSSOP-28 package drawing itself. Both PWP0028 revisions assume a single rectangular aperture over the thermal land and shrink it as the foil gets thicker.
Table 2. TI thermal-land stencil apertures for the 28-pin PowerPAD TSSOP
| Stencil thickness (mm) | PWP0028C aperture (mm) | PWP0028V aperture (mm) |
| 0.100 | 5.79 × 3.47 | 6.28 × 3.29 |
| 0.125 | 5.18 × 3.10 | 5.62 × 2.94 |
| 0.150 | 4.73 × 2.83 | 5.13 × 2.68 |
| 0.175 | 4.38 × 2.62 | 4.75 × 2.48 |
Paste volume, not footprint area, is what the aperture controls, which is why it shrinks as the foil thickens. At 0.125 mm the aperture equals the mask opening exactly, a 1:1 ratio.
Whether to keep that single aperture is a process decision, and TI’s assembly data supports keeping it. The company recommends a minimum solder joint area of 50 percent of the package thermal pad and reports that standard board assembly normally achieves better than 80 percent with no attempt to optimize. JEDEC standoff for TSSOP runs 0.05 mm to 0.15 mm, and that is the window a correct paste volume has to land in.
Many assemblers split the aperture into a windowpane pattern regardless, to give flux volatiles an escape path. IPC-7093 Section 6.1.5.3 treats small voids in the thermal pad region as unlikely to degrade thermal or electrical performance, and the limit the standard sets is 50 percent void area by cross section. Power designs commonly hold an internal target nearer 30 percent. Whichever number you pick, the joint is hidden under the body, so x-ray is the only inspection that tells you anything.
[IMAGE 3: windowpane stencil apertures over an HTSSOP-28 thermal land at roughly 70 percent coverage | alt: “HTSSOP-28 stencil design with segmented windowpane apertures for 70 percent paste coverage on the thermal pad”]
What soldering the pad is actually worth
Numbers beat adjectives here. TI’s LM4836 audio amplifier ships in both a plain 28-pin TSSOP (PW0028A) and a 28-pin PowerPAD TSSOP (PWP0028A). Same die, same pin count, same outline. Board-mounted junction-to-ambient thermal resistance is 80 °C/W for the pad-less version and 41 °C/W for the PowerPAD version.
For a current part, the DRV8825 stepper driver in the 28-pin PWP package reports the following on a JESD51-7 high-K board in a JESD51-2a environment.
Table 3. DRV8825 thermal metrics, HTSSOP-28 (PWP), simulated per JESD51-7 high-K board
| Metric | Value (°C/W) | What it is good for |
| RθJA junction-to-ambient | 31.6 | Rough comparison between packages only |
| RθJC(top) junction-to-case top | 15.9 | Top-side heatsink or cold plate |
| RθJB junction-to-board | 5.6 | System thermal model |
| RθJC(bot) junction-to-case bottom | 1.4 | Ceiling on what the exposed pad can deliver |
| ψJT junction-to-top parameter | 0.2 | Estimating TJ from a top-surface thermocouple |
| ψJB junction-to-board parameter | 5.5 | Estimating TJ from a board thermocouple |
The 1.4 °C/W junction-to-case (bottom) figure is the one to look at when deciding how hard to work on the via array. Almost all of the 31.6 °C/W is board and ambient, not package. Copper area buys more than a denser via grid does.
Worked example: DRV8825 at a 1.25 A full-scale setting
TI estimates dissipation for this device as four times the FET on-resistance times the RMS output current squared, where RMS current is about 0.7 times the full-scale setting.
At 1.25 A full scale the RMS current is 0.875 A. Taking the 0.25 Ω typical on-resistance quoted at 85 °C junction temperature, dissipation is 4 × 0.25 Ω × (0.875 A)² = 0.77 W.
With the pad soldered and a board sitting at 85 °C, the 5.5 °C/W junction-to-board parameter puts the junction near 89 °C. Working from the 31.6 °C/W junction-to-ambient number with 85 °C ambient instead gives roughly 109 °C. Both sit comfortably under the 150 °C typical thermal shutdown threshold.
Now substitute the 80 °C/W that TI publishes for the pad-less PW0028A outline. The same 0.77 W arrives at about 147 °C, which is thermal shutdown. That is a package-level comparison rather than a DRV8825 specification, but it sizes the margin the exposed pad is carrying.
Failure modes worth designing against
Most HTSSOP-28 assembly escapes trace back to one of five causes, and four of them are settled at layout rather than on the line.
- The part floats and tilts. Full-area paste on the thermal land melts before the lead joints and buoys the package, opening perimeter leads. Cut paste coverage.
- Solder drains into open vias. Standoff falls, the pad joint thins, and solder balls appear under the body. Plug, fill or tent from the component side.
- Mask opening drawn to the copper instead of the pad. The joint then spreads past the pad edge and can bridge to a lead at 0.65 mm pitch.
- A footprint reused across drawing revisions. Check the drawing number on the mechanical sheet whenever the orderable part number changes.
- Bridging during rework. Lead lands are 0.45 mm wide with roughly 0.20 mm of mask web between them, so rework wants flux and wick rather than more solder.
Sourcing, lifecycle and second sources
Distributor taxonomy does not match the datasheet. Digi-Key files the TI PWP-28 under a Package / Case value of 28-PowerTSSOP (0.173 inch, 4.40 mm width) and carries 28-HTSSOP only as the supplier device package string. A parametric search on HTSSOP alone will miss parts.
The package is mature and TI is steering new designs toward VQFN. The tube-packaged DRV8825PWP is flagged obsolete at Digi-Key with the tape-and-reel DRV8825PWPR named as the manufacturer-recommended replacement. Checked on 11 August 2026, the obsolete tube part listed at $6.13 in single quantity against 10,204 units of remaining stock, and the reel part at $5.61. The listed similar parts, including DRV8424ERGER at $3.97, are 24-pin VQFN. If you are choosing the package rather than inheriting it, price the QFN equivalent of your function before committing to an HTSSOP-28 land pattern.
For process planning, TI ships the PWP-28 at MSL 3 with a 260 °C peak reflow classification and 168 hour floor life, on 330 mm reels of 2000 parts, 12 mm pitch in 16 mm tape.
Frequently asked questions
What is the thermal pad size on an HTSSOP-28?
There is no single value, because the pad is vendor specific. TI PWP0028C is 4.48 mm to 5.18 mm by 2.40 mm to 3.10 mm. TI PWP0028V is 4.92 mm to 5.62 mm by 2.24 mm to 2.94 mm. Analog Devices RE-28-2 is 5.50 mm by 3.00 mm nominal. Renesas M28.173C is 6.80 mm by 2.80 mm. Read the device datasheet.
Is HTSSOP-28 the same as TSSOP-28?
The outline is the same, MO-153-AET, with identical body, pitch and lead span. HTSSOP adds an exposed die-attach pad on the underside, which changes both the land pattern and the thermal numbers. A board laid out for one is not correct for the other.
Do I have to solder the HTSSOP-28 thermal pad?
Yes, for any device that specifies it. TI states that the PowerPAD package is not designed to be used without the exposed pad soldered to the board, citing both thermal performance and mechanical integrity. On comparable parts, leaving it unsoldered costs roughly half the junction-to-ambient performance.
How many thermal vias does an HTSSOP-28 need?
Five to nine is adequate for a small die according to TI’s SLMA002 modelling, with returns flattening beyond that. TI’s own example pattern for the 28-pin PowerPAD TSSOP places 0.2 mm vias on a 1.2 mm to 1.3 mm grid across the pad, which works out near a dozen.
Should the HTSSOP-28 thermal pad connect to ground?
Usually, but confirm it per device. Most exposed pads land on ground. TI tells designers to check the product datasheet to see which signal, power or ground plane the pad should be soldered to, because the pad is electrically live on some parts and floating on others.
What stencil thickness should I use for an HTSSOP-28?
0.125 mm, or 5 mil, is the reference. TI’s aperture tables are drawn around it, and at that thickness the thermal aperture is 1:1 with the mask opening. Thinner foil needs a larger aperture to hold paste volume, thicker foil needs a smaller one.
What to do next
Open the mechanical drawing in the datasheet for the exact orderable part number, note the drawing revision, and size the mask opening to the maximum exposed pad on that sheet. Draw the copper larger if creepage allows. Place 0.2 mm to 0.3 mm vias on a 1.2 mm grid, plugged or tented from the component side, connected to a plane with full annular rings.
Below about 0.5 W a 0.125 mm stencil with a single 1:1 aperture is fine and you can skip x-ray. Above that, or in anything automotive or high-reliability, split the aperture to roughly 70 percent coverage, agree a void limit before the first build, and inspect. And if the package is still a choice rather than a constraint, price the VQFN version of the same function first.
Sources
Texas Instruments, PowerPAD Thermally Enhanced Package (SLMA002H). https://www.ti.com/lit/an/slma002h/slma002h.pdf
Texas Instruments, DRV8825 datasheet, containing PWP0028C and PWP0028V package outline drawings. https://www.ti.com/lit/ds/symlink/drv8825.pdf
Texas Instruments, LM4836 datasheet, PW0028A and PWP0028A thermal resistance. https://www.ti.com/lit/ds/symlink/lm4836.pdf
Renesas, package outline drawing M28.173C, 28-lead HTSSOP. https://www.renesas.com/en/document/psc/m28173c-28-lead-heat-sink-thin-shrink-small-outline-plastic-package-htssop
Analog Devices, package drawing RE-28-2, 28-lead TSSOP with exposed pad. https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tssop_epre/re_28_2.pdf
[INTERNAL LINK: TSSOP-28 package dimensions -> TSSOP-28 outline and footprint guide]
[INTERNAL LINK: QFN exposed pad land pattern -> QFN thermal pad, via and stencil design]
[INTERNAL LINK: IPC-7351 land pattern density levels -> IPC-7351 naming and density level selection]
[INTERNAL LINK: reading JEDEC thermal metrics -> RthetaJA, psiJB and the JESD51 test boards]
[INTERNAL LINK: moisture sensitivity level handling -> MSL ratings, floor life and reflow profiles]
