An HSOP package is a gull-wing small-outline body with a thick copper heat slug mechanically riveted to the leadframe and exposed on the underside. That is a different construction from an exposed-pad SOIC, where the paddle is part of the leadframe itself. NXP measures 0.2 °C/W from junction to the bottom of that slug, which means essentially all of the thermal resistance in a finished assembly sits outside the package.
Key takeaways
- HSOP uses a separate thick copper heat sink riveted to a pre-plated copper leadframe, not a down-set leadframe paddle.
- NXP’s HSOP is a non-JEDEC outline. Its exposed pad was widened relative to JEDEC MO-166, the plastic small outline heatslug package.
- Junction-to-case at the bottom is 0.2 °C/W on a 20-lead part. Junction-to-ambient is 19 °C/W on a four-layer board and 52 °C/W on a single-layer board.
- The published pad-width rule of 60% of pitch does not match the table printed beside it, which ranges from 51% to 75%.
- The same application note rates HSOP at MSL 1 with a 220 °C peak in its 2005 revision and MSL 3 with a 245 °C peak in its 2016 revision.
What is an HSOP package?
An HSOP package is a surface-mount small-outline integrated circuit package with gull-wing leads on two sides and a thick copper heat sink exposed at the bottom of the body. The slug is mechanically riveted to the leadframe rather than formed from it. Soldering that slug to a PCB land gives heat a direct conduction path into the board, which is why HSOP is used for motor drivers, audio amplifiers and automotive power ICs.
[IMAGE 1: cross-section diagram of an HSOP showing the riveted copper slug under the die paddle, gull-wing leads, and heat-flow arrows into the PCB | alt: “HSOP package cross-section showing the riveted copper heat slug and heat flow into the board”]
HSOP is not an exposed pad. It is a riveted slug.
The distinction gets glossed over constantly, and it changes what you are buying.
In an exposed-pad SOIC the die-attach paddle is part of the leadframe, down-set during forming so that mold compound leaves it flush with the package bottom. In an HSOP, NXP’s cross-section shows a pre-plated copper leadframe and a separate thick copper heat sink mechanically riveted together, with solder die attach, copper bond wire, and epoxy mold compound over the assembly.
Two practical consequences follow. The slug can be thicker than any leadframe paddle, which is where the 0.2 °C/W junction-to-case figure comes from. And the pad area is not constrained by leadframe geometry, which is how NXP widened it relative to the JEDEC MO-166 outline.
Lead finish differs too. NXP specifies NiPdAu as the standard lead-free finish on HSOP, against matte tin on its PQFP packages.
Body sizes and pitch
NXP publishes three HSOP variants that share a body and differ only in lead count and pitch.
| Package | Leads | Body width | Body length | Height, max | Pitch |
| HSOP 20 | 20 | 11.0 mm | 15.9 mm | 3.2 mm | 1.27 mm |
| HSOP 30 | 30 | 11.0 mm | 15.9 mm | 3.2 mm | 0.80 mm |
| HSOP 44 | 44 | 11.0 mm | 15.9 mm | 3.2 mm | 0.65 mm |
| PQFP 64 | 64 | 14.0 mm | 14.0 mm | 3.15 mm | 0.65 mm |
Table 1. NXP HSOP and PQFP offerings, per AN2388 rev 3.0 Table 1. Units corrected to mm — see note.
One caution about that table as published. NXP’s application note AN2388 rev 3.0 heads those columns in inches. The values are millimeters: an 11 inch body would be absurd, and the 1.27 mm pitch in the same row is metric. Read the column as mm.
The shared body is the useful part. All three variants drop into an 11.0 mm × 15.9 mm outline, so a design can move from 20 to 44 leads without changing the mechanical envelope or the heat slug land. On the 20-lead part, ten leads per side at 1.27 mm pitch span 11.43 mm inside a 15.90 mm body length.
Thermal: 0.2 °C/W inside, everything else outside
NXP publishes a worked thermal example for a 20-lead HSOP at 1.27 mm pitch with a die measuring roughly 5.54 mm × 4.19 mm.
| Rating | Board or condition | Symbol | Value |
| Junction to ambient, natural convection | Single layer (1s) | RθJA | 52 °C/W |
| Junction to ambient, natural convection | Four layer (2s2p) | RθJA | 19 °C/W |
| Junction to board | JESD51-8 | RθJB | 3.0 °C/W |
| Junction to case, bottom | Simulated, no interface resistance | RθJC | 0.2 °C/W |
| Junction to package top | Natural convection | ΨJT | 5.0 °C/W |
Table 2. Thermal example for a 20-lead HSOP, 1.27 mm pitch, die ≈5.54 × 4.19 mm, per NXP AN2388 rev 3.0 Table 5.
Read those five numbers together and the design conclusion writes itself. On the four-layer board, junction-to-case accounts for 0.2 of 19 °C/W, or about 1% of the total. Junction-to-board adds 3.0 °C/W, another 16%. The remaining 83% is the board getting heat into the air.
Worked example. Take a 65 °C allowable junction rise over ambient. On the 2s2p board that permits 65 ÷ 19, or 3.4 W. On the single-layer board it permits 65 ÷ 52, or 1.25 W. Moving from one copper layer to four buys a 63% reduction in thermal resistance and nearly triples the power budget, without changing the part.
Two qualifications on the 0.2 °C/W figure. NXP states it is a simulated value from junction to the exposed pad without contact resistance, measured per MIL-STD-883 method 1012.1 conventions. Real solder joints, voids and interface resistance are not in it. And ΨJT is not a thermal resistance at all; it is a characterization parameter for the temperature difference between package top and junction, useful for inferring junction temperature from a surface probe.
[IMAGE 2: stacked bar showing the 19 °C/W four-layer budget split into 0.2 junction-to-case, 2.8 case-to-board and the remaining board-to-air share | alt: “HSOP package thermal resistance budget showing junction-to-case as about one percent of the total”]
Land pattern: the rule and the table disagree
NXP’s general guidance is that pad width should be approximately 60% of the lead pitch. The table printed directly beneath that sentence says otherwise.
| Lead pitch | Published pad width | Actual ratio |
| 0.65 mm | 0.45 mm | 69% |
| 0.80 mm | 0.60 mm | 75% |
| 1.27 mm | 0.65 mm | 51% |
Table 3. NXP AN2388 Table 2 pad widths, with the pitch ratio each one actually represents.
Use the table, not the sentence. The 60% figure is an average across a range that runs from 51% to 75%, and the fine-pitch end sits well above it.
Pad length is more consistent. NXP extends the pad 0.5 mm beyond the foot at both heel and toe. For the 30-lead example, the nominal foot length is 0.95 mm with a range of 0.84 mm to 1.10 mm, so pad length is 0.95 + 0.50 + 0.50, or 1.95 mm.
Land center-to-center for that part is 13.2 mm. That equals the nominal tip-to-tip dimension of 14.20 mm less 0.50 mm on each side. The note’s own prose describes the derivation differently and quotes a tip-to-tip figure that does not match its drawing, so work from the published 13.2 mm and check it against your part’s drawing.
Two more constraints matter. Pads must not extend under the package body. And there must be at least 0.25 mm of clearance between the outer edge of the thermal land and the inner edge of the lead pads.
The thermal land, segmentation and vias
The solderable area of the thermal land, as defined by the solder mask, should be at least the same size and shape as the exposed slug. The copper underneath can be larger, smaller or a different shape; the mask opening is what governs.
Segmenting that land reduces voiding. NXP recommends a matrix of pads with an edge length between 1.0 mm and 2.0 mm. Gaps run 0.2 mm to 0.4 mm for solder-mask webbing, or 0.4 mm for copper-defined pads. Segmentation lets flux outgas during reflow and caps the size of any single void at one segment.
Thermal vias are the path from the land to the internal planes. NXP recommends an array on a 1.2 mm grid pitch, with via diameter 0.30 mm to 0.33 mm and 1 oz copper barrel plating, sized deliberately to resist solder wicking. If the plating does not plug the via, tent it with solder mask at least 0.1 mm larger in diameter than the via.
Stencil: two coverage ratios that are not the same
For a nominal 0.1 mm package standoff, NXP recommends a stencil 0.10 mm to 0.15 mm thick. On 1.27 mm pitch HSOP the starting point is 0.125 mm to 0.150 mm; on 0.65 mm pitch it drops to 0.100 mm to 0.125 mm.
The thermal aperture needs care. NXP calls for the exposed-pad aperture to be 0.25 mm smaller than the copper pad, for the aperture to be segmented with at least 0.15 mm between segments, and for the stencil opening to be roughly 50% to 80% of the total PCB thermal pad area.
Elsewhere in the same section the note says the guidelines produce a solder joint area of about 80% to 90% of the exposed pad area. Those two percentages measure different things, one against the PCB land and one against the package slug, and they are easy to conflate into a single wrong number. Set the aperture from the 50% to 80% rule and treat the 80% to 90% figure as the expected result.
[IMAGE 3: HSOP thermal land drawn with segmented copper, a 1.2 mm via grid, and the reduced segmented stencil aperture overlaid in a second colour | alt: “HSOP package thermal land with segmented pads, 1.2 mm via grid and reduced stencil aperture”]
MSL changed between revisions of the same note
Moisture sensitivity on this package is worth checking against the document date. The earlier Freescale revision of AN2388 states that all HSOP packages are rated MSL 1 at 220 °C, qualified to JEDEC J-STD-020 with 85 °C and 85% RH bias for 96 hours, 1000 cycles from −55 °C to 125 °C, and 1000 hours of storage at 150 °C.
Revision 3.0 from July 2016 lists HSOP 20, 30 and 44 at MSL 3 with a 245 °C peak package temperature. MSL 3 means 168 hours of floor life at 30 °C and 60% RH, against unlimited floor life for MSL 1.
The rating moved because the qualifying peak temperature moved. If your incoming inspection or line documentation still assumes MSL 1, the parts will sit out too long.
Board-level reliability testing on these packages runs to IPC-9701A with continuous in-situ daisy-chain monitoring: −40 °C to +125 °C on a one-hour cycle for automotive, 0 °C to 100 °C for commercial and industrial, on a 1.58 mm four-layer OSP board.
Design mistakes that cause returns
- Treating HSOP as an exposed-pad SOIC. The heat slug is a separate riveted copper part and the pad geometry is not leadframe-limited.
- Sizing pad width from the 60% rule instead of the published table, which runs 51% to 75% depending on pitch.
- Budgeting from the 0.2 °C/W junction-to-case number as though it included the solder joint. It is simulated without interface resistance.
- Specifying a single-layer board and expecting the four-layer thermal number, which is 2.7× better.
- Cutting one large stencil aperture over the thermal land instead of a segmented array, which raises voiding and invites bridging.
- Carrying an MSL 1 assumption forward from an older revision of the same application note.
Frequently asked questions
What is an HSOP package?
A heat-sink small outline package: a gull-wing SOP body with a thick copper heat slug exposed at the bottom, mechanically riveted to the leadframe. Soldering the slug to a PCB land conducts heat into the board. NXP builds it in 20, 30 and 44 lead counts on an 11.0 mm × 15.9 mm body.
What is the difference between HSOP and exposed-pad SOIC?
Construction. An exposed-pad SOIC uses a down-set portion of its own leadframe as the pad; an HSOP has a separate thick copper slug riveted to the leadframe. The slug can be thicker and larger than a leadframe paddle, which is why HSOP reaches 0.2 °C/W junction-to-case at the bottom.
Is HSOP a JEDEC package?
NXP states its HSOP is a non-JEDEC outline. The closest registered outline is JEDEC MO-166, the plastic small outline heatslug package, and NXP widened its exposed pad region relative to MO-166 for better thermal performance. Take dimensions from the vendor case outline drawing.
What is the MSL rating of an HSOP package?
It depends on the revision you are reading. NXP’s AN2388 rev 3.0, dated July 2016, lists HSOP 20, 30 and 44 at MSL 3 with a 245 °C peak. An earlier Freescale revision of the same note states MSL 1 at 220 °C. Confirm against the specific device datasheet.
How many thermal vias does an HSOP need?
NXP calls the count application specific and recommends thermal analysis, but gives a geometry: an array on a 1.2 mm grid pitch with vias of 0.30 mm to 0.33 mm diameter and 1 oz copper barrel plating. Vias must be plugged, tented or plated to stop solder wicking.
What to do next
If you are choosing between HSOP and an exposed-pad SOIC, compare junction-to-board rather than junction-to-case. Both packages will quote a small case number; what separates them in a real assembly is slug area and how much copper you can connect to it.
Then spend the design effort on the board. On the published example, the package contributes about 1% of the total junction-to-ambient resistance on a four-layer board. Going from one copper layer to four is worth more than any package choice you can make above it, so fix the stack-up and the via array first, and pick the HSOP package once you know the copper is there to feed it.
Primary sources
- NXP AN2388 rev 3.0, HSOP and PQFP PCB assembly guidelines — https://www.nxp.com/docs/en/application-note/AN2388.pdf
- Freescale AN2388 rev 1.0, Heatsink Small Outline Package (earlier MSL rating) — https://www.farnell.com/datasheets/1853267.pdf
- NXP package page SOT851-2, HSOP36 heatsink small outline package — https://www.nxp.com/packages/SOT851-2
- ROHM package information, HSOP25 — https://fscdn.rohm.com/en/techdata_basic/ic/package/Jisso_HSOP25-1-2_Rev005s_E2(MSL1).pdf
- Toshiba package catalogue listing HSOP16 and HSOP36 (SCE0020) — https://www.mouser.com/datasheet/2/408/SCE0020_catalog-25311.pdf
Proposed internal links
- [INTERNAL LINK: “exposed-pad SOIC thermal design” → eSOP package reference page]
- [INTERNAL LINK: “gull-wing lead solder joint criteria” → gull-wing lead reference page]
- [INTERNAL LINK: “thermal via arrays and stencil apertures” → PCB thermal design guide]
- [INTERNAL LINK: “reading JEDEC thermal metrics” → RθJA, RθJB and ΨJT explainer]
- [INTERNAL LINK: “MSL ratings and dry-pack handling” → moisture sensitivity guide]
