An eSOP package is a small-outline package with the die-attach paddle exposed through the bottom of the mold compound, giving heat a direct path into the board. The 8-lead version is not a new outline: Monolithic Power’s drawing and TI’s PowerPAD SOIC drawing both conform to JEDEC MS-012 variation BA, the same registration as a plain SOIC-8. What changes is the thermal path, and only if the board underneath it earns the improvement.
Key takeaways
- The exposed-pad SOIC-8 shares the standard SOIC-8 outline, MS-012 variation BA, per both MPS drawing MF-PO-D-0018 and TI drawing DDA0008D.
- On a 4 in² two-layer board, TI measured 49.6 °C/W for the exposed-pad part against 99 °C/W for the plain SOIC-8, a 50% reduction.
- On a 0.5 in square board the same comparison collapses to 240.2 against 263.7 °C/W. The copper is doing the work, not the pad.
- On a metal-core PCB the gap widens to roughly 7×, 9.8 °C/W against 70.5 °C/W board-to-junction.
- The pad is electrically live on some parts and isolated on others. Check the specific datasheet before tying it to a plane.
Search-intent note
The bare phrase “esop package” returns employee stock ownership plans, not semiconductors. Nothing on that first page concerns electronics. Component-side results appear once a pin count is attached: ESOP-8, or the descriptive terms exposed pad SOIC-8 and SOIC-8 EP. Target those, not the bare acronym.
What is an eSOP package?
An eSOP package is a plastic small-outline package whose leadframe die pad is exposed at the bottom surface instead of being fully encapsulated. Soldering that pad to a matching land connects the die to board copper through a short, low-resistance path. Lead count, pitch and body size follow the standard SOP or SOIC family; only the underside changes.
[IMAGE 1: underside macro of an 8-lead exposed-pad SOIC beside a plain SOIC-8, showing the bare metal paddle against a fully molded bottom | alt: “eSOP package exposed thermal pad compared with a plain SOIC-8 underside”]
The naming is vendor-specific. The outline usually is not.
Half the confusion around this package comes from the name. Manufacturers each coined their own, and the descriptive terms compete with the trademarked ones.
| Designation | Who uses it | Notes |
| ESOP-8, ESOP8 | Widely used in distributor catalogs and Asian-market power ICs | Descriptive, not a registered outline name |
| SOIC8E, 8-SOIC with exposed pad | Monolithic Power Systems, drawing MF-PO-D-0018 rev 1.0 | States conformance to JEDEC MS-012 variation BA |
| SO PowerPAD-8, DDA | Texas Instruments, drawing DDA0008D | PowerPAD is a TI trademark; also references MS-012 variation BA |
| SO-8EP, PSOP-8 | Diodes Incorporated, as carried in the KiCad Package_SO library | Two names for exposed-pad 8-lead small outline |
| HSOP, HTSSOP | Various; H prefix denoting a heat-sink variant | Applies the same idea to other body sizes |
Table 1. Vendor names for the same idea. Match on the MS-012 reference, not on the name.
The practical consequence is that ESOP-8 and SO PowerPAD-8 usually describe the same physical outline from different vendors. Confirm by looking for the MS-012 reference on the drawing rather than by matching names.
One caution about secondary sources. A distributor package page currently describing ESOP-8 lists a 3.0 mm × 3.0 mm body on 0.65 mm pitch with leadless bottom-mounted pads. That describes a DFN-8. The exposed-pad SOIC-8 is 4.80 mm to 5.00 mm long by 3.80 mm to 4.00 mm wide on 1.27 mm pitch, with gull-wing leads, per Monolithic Power’s own outline drawing.
Dimensions: a standard SOIC-8 with a paddle
Monolithic Power publishes the outline as MF-PO-D-0018, revision 1.0, with the note that the drawing conforms to JEDEC MS-012 variation BA. Controlling dimensions on that drawing are inches.
| Feature | Min | Max |
| Body length | 4.80 mm | 5.00 mm |
| Body width | 3.80 mm | 4.00 mm |
| Span across leads | 5.80 mm | 6.20 mm |
| Overall height | 1.30 mm | 1.70 mm |
| Standoff | 0.00 mm | 0.15 mm |
| Lead pitch | 1.27 mm BSC | 1.27 mm BSC |
| Lead width | 0.33 mm | 0.51 mm |
| Lead thickness | 0.19 mm | 0.25 mm |
| Exposed pad, width | 2.26 mm | 2.56 mm |
| Exposed pad, length | 3.15 mm | 3.45 mm |
Table 2. Exposed-pad SOIC-8 outline, per MPS drawing MF-PO-D-0018 rev 1.0 (JEDEC MS-012 variation BA).
Compare those numbers against a plain SOIC-8 and nothing outside the pad has moved. That is the point: the package drops into an existing footprint. TI states it directly for the LM3404HV, noting that the SO PowerPAD-8 version can be used on a standard SOIC-8 footprint and the SOIC-8 version can be used on the PowerPAD board, in neither case getting the thermal benefit.
Lead coplanarity on the MPS drawing is 0.10 mm maximum after forming, and the lead exit angle runs 0° to 8°, both unchanged from the standard part.
What the pad actually buys, and when it buys nothing
TI’s application report AN-1629 (SNVA238A, revised April 2013) tested and simulated one die, the LM3404HV, in both packages. The measured results used the SO PowerPAD-8 evaluation board: 1.95 in × 1.25 in, two layers of 1 oz copper on 62 mil FR-4, roughly 4 in² of total copper, no airflow.
| Condition | SOIC-8 | Exposed-pad SOIC-8 | Reduction |
| Measured, eval board, 0.5 W | 102 °C/W | 50.9 °C/W | 50% |
| Measured, eval board, 1.0 W | 99 °C/W | 49.6 °C/W | 50% |
| Measured, eval board, 1.5 W | not obtainable, TJ exceeded 125 °C | 48.4 °C/W | — |
| Simulated, 1.25 in × 1.95 in board, 1 W | 104.8 °C/W | 55.1 °C/W | 47% |
| Simulated, 1 in × 1 in board, 1 W | 120.8 °C/W | 73.0 °C/W | 40% |
| Simulated, 0.5 in × 0.5 in board, 1 W | 263.7 °C/W | 240.2 °C/W | 9% |
| Simulated on metal-core PCB, board-to-junction | 69.2–71.4 °C/W | 9.2–10.5 °C/W | ≈7× |
Table 3. One die, two packages, seven board conditions. Data from TI AN-1629 (SNVA238A).
Read the last three rows together. Shrink the board to half an inch square and the exposed pad recovers under 9%, because there is nowhere for the heat to go once it reaches the copper. Move to a metal-core board and the same pad is worth a factor of seven. The pad is a connector between the die and the heatsink; the board is the heatsink.
Worked example. TI calculates 1.14 W of dissipation for that LED driver circuit at 48 V in and 1 A of LED current. Using the measured 1 W figures, the maximum ambient temperature before the 125 °C junction limit is reached is 125 − (1.14 × 99), or 12 °C, in the plain SOIC-8. In the exposed-pad version it is 125 − (1.14 × 49.6), or 68 °C. The plain package is unusable at room temperature in that circuit; the exposed-pad version has 43 °C of headroom above a 25 °C ambient.
One more caution on comparing datasheet numbers. TI’s THS3115 datasheet gives a junction-to-ambient figure of 168 °C/W for the 8-lead SOIC on the JEDEC low-K test board, against a much lower number on the high-K board. A quoted thermal resistance without its test board is not a specification.
[IMAGE 2: chart plotting the seven θJA data points from Table 3, exposed-pad against plain SOIC-8, with board area on the x-axis | alt: “eSOP package thermal resistance versus board copper area compared with plain SOIC-8”]
The pad is not always ground
Do not assume the exposed pad is a ground connection. On TI’s THS3062 the PowerPAD is documented as electrically isolated from all other pins. On many switching regulators the same feature is the die substrate and sits at the ground or the switch node potential.
Three rules follow. Read the pin description, not the package name. If the pad is isolated, you may still solder it to a copper pour, but pick the net deliberately, because the pad forms a capacitor to whatever it faces. And if the pad carries a switching node, treat the thermal pour as a radiating surface and keep it away from sensitive analog traces.
Land pattern, vias and assembly
Monolithic Power’s recommended land pattern makes the thermal land slightly larger than the package pad: 2.62 mm × 3.51 mm against an exposed pad of 2.26 mm to 2.56 mm by 3.15 mm to 3.45 mm. That is about 9.2 mm² of land against a nominal 7.95 mm² of pad. Signal lands are 1.60 mm long by 0.61 mm wide on the same 1.27 mm pitch.
Thermal vias are what connect the land to the copper that matters. TI’s evaluation layout for this package uses a via array within the thermal land, and the report is explicit that the benefit depends on connecting the pad to a large copper area of one square inch or more.
Two assembly notes. TI’s package drawing states the package is designed to be soldered to a thermal pad on the board, so a design that leaves the pad unsoldered is outside the intended use. And stencil aperture on the thermal land should be windowpaned rather than solid, since a single large aperture deposits enough paste to float the part and open the signal joints.
[IMAGE 3: recommended land pattern drawing with the 2.62 × 3.51 mm thermal land, a via array inside it, and a windowpaned stencil aperture overlaid | alt: “eSOP package land pattern with thermal land, via array and windowpaned stencil apertures”]
Design mistakes that cause returns
- Specifying the exposed-pad version and then giving it a 0.5 in square of board. The measured gain drops to single-digit percent.
- Comparing a datasheet junction-to-ambient figure against another vendor’s without checking whether both used the same JEDEC test board.
- Assuming the pad is ground. Some are isolated, some sit at the switch node.
- Leaving the thermal land unconnected because the pad is isolated, and losing the entire thermal benefit.
- Cutting a single solid stencil aperture over the thermal land, which floats the package and lifts the signal leads.
- Reading distributor package pages for dimensions. At least one currently publishes DFN geometry under the ESOP-8 name.
Frequently asked questions
What is an eSOP package?
A small-outline package with the die-attach paddle exposed at the bottom of the body, so heat flows from the die directly into board copper. The 8-lead version keeps the standard SOIC-8 outline, JEDEC MS-012 variation BA, with a 1.27 mm lead pitch and a 4.80 mm to 5.00 mm body length.
What is the difference between ESOP-8 and SOIC-8?
Only the underside. Body size, lead pitch, span and height are the same registered outline, so an exposed-pad part fits a plain SOIC-8 footprint and vice versa. The difference is a metal pad on the bottom that must be soldered to a thermal land to deliver its benefit.
How much does an exposed pad improve thermal resistance?
It depends on the board, not the package. TI measured 49.6 °C/W against 99 °C/W on a 4 in² two-layer board, a 50% reduction. On a 0.5 in square board the same pair measured 240.2 against 263.7 °C/W, under 9%.
Is the exposed pad connected to ground?
Not always. TI documents the pad on the THS3062 as electrically isolated from all other pins, while on many regulators the same pad is the die substrate at ground or switch potential. Read the pin function table on the specific datasheet before routing it.
Do you have to solder the exposed pad?
For the thermal rating, yes. TI’s package drawing states the package is designed to be soldered to a thermal pad on the board. A part reflowed with the pad floating will still function electrically but will behave thermally like a plain SOIC-8 or worse.
What to do next
Before you commit the part, budget the thermal path rather than the package. Take the dissipation, pick the junction-to-ambient figure that matches your actual copper area, and check the maximum ambient. If the answer is comfortable in a plain SOIC-8, the exposed pad is buying you nothing.
If it is marginal, the eSOP package earns its place only alongside a thermal land, a via array and at least a square inch of connected copper. Where the board is small or crowded, spend the effort on copper area or a metal-core substrate first, then choose the package that connects to it.
Primary sources
- Monolithic Power Systems, 8-SOIC with exposed pad outline drawing MF-PO-D-0018 — https://media.monolithicpower.com/cms_document/Package%20Information/SOIC8%20EP%20POD.pdf
- Texas Instruments AN-1629, thermal performance in SOIC-8 and SO PowerPAD-8 (SNVA238A) — https://www.ti.com/lit/an/snva238a/snva238a.pdf
- Texas Instruments SLMA002, PowerPAD thermally enhanced package — https://www.ti.com/lit/slma002
- Texas Instruments THS3115 datasheet, JEDEC low-K and high-K thermal figures — https://www.ti.com/lit/ds/symlink/ths3115.pdf
- KiCad Package_SO footprint library, Diodes SO-8EP and PSOP-8 — https://kicad.github.io/footprints/Package_SO.html
Proposed internal links
- [INTERNAL LINK: “SOIC-8 dimensions and land pattern” → SOIC package reference page]
- [INTERNAL LINK: “thermal via arrays under exposed pads” → PCB thermal design guide]
- [INTERNAL LINK: “reading junction-to-ambient thermal metrics” → thermal resistance explainer]
- [INTERNAL LINK: “QFN and DFN land patterns” → QFN footprint guide]
- [INTERNAL LINK: “stencil design for thermal pads” → SMT assembly guide]
