A ceramic IC package seals a semiconductor die inside alumina or aluminum-nitride ceramic, then closes it with a hermetic lid. That construction protects the die from moisture and contamination, moves heat far better than plastic, and survives wide temperature swings — the reasons aerospace, defense, radar, and medical designs still specify ceramic long after plastic took over commercial electronics. This guide compares the four package families an engineer meets most — CDIP, CQFP, CBGA, and CPGA — with real designators, part numbers, and the reliability physics that decide which one belongs in your design.
Key takeaways
- Interconnect drives the decision. Leaded packages (CDIP, CQFP) tolerate board-level thermal cycling best; area-array packages (CBGA) pack the most I/O but stress their solder joints hardest.
- CBGA has a size ceiling. Balls become unreliable on large bodies, so high-pin-count hermetic parts move to CCGA (columns), which extends the practical body size from about 32 mm to 52.5 mm.
- Material is a thermal-versus-CTE trade. Alumina runs about 24–30 W/m·K with a CTE near 7.3 ppm/K; aluminum nitride reaches roughly 170 W/m·K but its CTE drops below ~4.5 ppm/°C.
- Hermetic means no moisture-sensitivity baking. Sealed ceramic cavities do not “popcorn,” so they sit outside the JEDEC MSL scheme that governs plastic parts.
- Screening is standardized. Hi-rel ceramic parts qualify to MIL-PRF-38535 QML flows (Class S/V) and pass MIL-STD-883 Method 1014 seal testing.
The four families at a glance
| Package | Interconnect | Typical I/O | Typical pitch | Mounting | Board-level thermal-fatigue tolerance | Cost | Best fit |
| CDIP | Dual-row leads (side-braze or glass-seal) | ~8–64 | 2.54 mm | Through-hole | High (compliant leads) | Mod. | Rugged low/mid pin count, legacy |
| CQFP | Gull-wing leads, 4 sides | ~44–352+ | 0.4–0.635 mm | Surface-mount | High (compliant gull-wing) | Mod.–high | Mid pin count, easier SMT assembly |
| CPGA | Through-hole pins on a grid | ~68–~500 | 2.54 / 1.27 mm | Through-hole / socket | High (pins + socketable) | High | Sockets, prototyping, high-pin legacy |
| CBGA | Solder balls, area array | up to ~1000+ | 1.0–1.27 mm | Surface-mount | Lower (stiff joints, CTE mismatch) | High | High I/O where body ≤ ~32 mm |
| CCGA | Solder columns, area array | 1000+ | 1.0–1.27 mm | Surface-mount | Moderate (compliant columns) | High | Highest I/O hi-rel / space |
I/O ceilings, pitch, and cost are typical industry values; verify against the specific datasheet and case outline for any part you specify. (CCGA is included because high-pin hermetic designs almost always end up there.)
CDIP: the workhorse hermetic DIP
The ceramic dual in-line package comes in two constructions that engineers often conflate. A glass-sealed ceramic DIP (often called CERDIP) differs from a side-braze ceramic DIP (CDIP SB): the side-braze version brazes metal leads to a co-fired ceramic body, while the glass-sealed version bonds a ceramic base and lid with sealing glass. Side-braze parts generally take higher assembly temperatures and rougher handling; glass-sealed parts are cheaper to build.
In the military case-outline system, CDIP outlines are enumerated explicitly. MIL-STD-1835D lists a CDIP1-T64 outline — a 64-terminal ceramic DIP on 0.900-inch row-to-row spacing with 0.100-inch (2.54 mm) terminal pitch. That coarse pitch and modest pin ceiling define where CDIP fits: rugged parts, references, and legacy logic where 64 leads is plenty and through-hole robustness matters more than density.
CDIP’s compliant leads are its quiet advantage. Because the leads flex, second-level solder joints see far less strain than a stiff area-array joint, which is why leaded hermetic parts remain the fatigue-life benchmark.
[IMAGE 1: cutaway of a side-braze CDIP showing co-fired ceramic body, brazed leads, and metal lid | alt: “Side-braze ceramic dual in-line package (CDIP) cutaway showing hermetic lid seal”]
CQFP: gull-wing leads for surface-mount density
The ceramic quad flat pack brings leads out on all four sides as gull-wing formed leads, so it reaches much higher pin counts than a DIP while staying surface-mountable. Microchip’s rad-tolerant RTG4 FPGA, for example, is offered in a CQ352 ceramic quad flat pack with 352 pins, of which 166 are 3.3 V general-purpose I/O.
CQFP earns its place on assembly economics. Microchip positions the CQFP option as easier to assemble onto the PCB than a ceramic column grid array, with well-understood assembly techniques and lower integration cost — and notably better suited to designs with frequent, severe temperature cycling, which is challenging for CCGA packages. The reason is mechanical: a compliant gull-wing lead absorbs board-to-package expansion mismatch better than a solder ball or even a column.
The trade is handling. Fine-pitch gull-wing leads (down to roughly 0.4 mm) bend easily, and lead coplanarity out of spec is a leading cause of open joints. Trim, form, and inspect leads carefully, and do not hand-straighten a bent lead on a flight part.
CPGA: pins for sockets and high-pin through-hole
The ceramic pin grid array places an array of stiff pins on the package underside for through-hole insertion or socketing. CPGA is a distinct case-outline family in the standard packaging vocabulary, historically used for processors and high-pin logic before area-array surface mount took over.
CPGA’s staying power is the socket. Being able to insert and remove a device without reflow is invaluable for engineering models, screening, and any board where a device may need replacement. Pins are mechanically robust and, like other leaded formats, forgiving of CTE mismatch. The downsides are board real estate (a coarse pin grid consumes layers and area) and pin damage — a single bent or splayed pin can scrap an expensive part or a socket.
CBGA — and why space designs jump to CCGA
The ceramic ball grid array replaces peripheral leads with an area array of solder balls, unlocking the highest I/O in the smallest footprint. But ceramic BGAs carry a reliability problem that plastic BGAs do not. Ceramic BGA solder joints live shorter lives than plastic BGA joints because the ceramic body’s CTE mismatches every common PCB laminate, whereas a plastic BGA’s internal substrate is closely CTE-matched to FR-4. As a rough envelope, NASA’s guidance puts BGA joint life between about 100 and 6,000 thermal cycles for −55 °C to +100 °C excursions, degrading fast as the temperature swing widens.
That mismatch has a hard consequence: a body-size limit. Above roughly 32 mm, ball joints cannot survive enough cycles, so high-pin-count hermetic parts switch to columns. Ceramic column grid array (CCGA) technology withstands the mismatch with high reliability and extends the practical body size from about 32 mm for CBGA to 52.5 mm. Columns are taller and more compliant than balls, so they flex under expansion instead of shearing. CCGA was introduced by IBM specifically for this improved reliability from column height and compliance, with fatigue life predicted by the Coffin-Manson model.
This is why nearly every large space-grade FPGA ships as a CCGA. AMD’s radiation-hardened Virtex-5QV part XQR5VFX130-1CF1752B uses a 1,752-column ceramic flip-chip column grid array on a 65-nm process, rated for total ionizing dose over 1 Mrad(Si) and single-event-latch-up immunity. Microchip’s RTG4 uses a 1,657-column CG1657 (“Six Sigma Columns”) package, TID-immune above 125 kRad and SEL-immune. One more tell: Microchip offers a ceramic ball version of the same die, the CB1657, explicitly for prototyping only — a direct admission that balls do not fly on a body that large.
Lead-free construction shifted the ball equation somewhat: SAC (tin-silver-copper) balls have shown better accelerated-thermal-cycling reliability than the earlier tin-lead dual-alloy CBGA joints they replaced. Columns still win above ~32 mm, and for the largest parts vendors have moved to copper columns to push electrical and fatigue performance further.
One subtlety helps ceramic here. Because a ceramic package’s CTE closely matches the silicon die, the die-to-package mismatch is negligible and ceramic parts use full (non-depopulated) arrays, unlike plastic parts that sometimes remove center balls to relieve die-edge stress.
[IMAGE 2: side-by-side of a CBGA solder ball versus a CCGA solder column on a ceramic substrate | alt: “CBGA solder ball compared with a taller, more compliant CCGA solder column”]
Alumina vs aluminum nitride: a thermal-versus-CTE trade
Package material is a real decision, not a detail. The two dominant ceramics pull in opposite directions.
| Property | 96% Alumina (Al₂O₃) | Aluminum nitride (AlN) | FR-4 (reference) |
| Thermal conductivity | ~24–30 W/m·K | ~140–180 W/m·K | ~0.3 W/m·K |
| CTE | ~6.5–8.0 ppm/°C | ~4.5 ppm/°C | ~14–18 ppm/°C |
| Role | Default hermetic substrate | High-power thermal path | PCB laminate |
Alumina conducts far better than FR-4 but far worse than AlN, and its CTE runs about 6.5–8.0 ×10⁻⁶/°C depending on purity and temperature range. AlN’s CTE sits near 4.5 ppm and is close to silicon’s, which is excellent for die stress but slightly worsens the mismatch to the board. Choose AlN when the die dumps enough heat to need it and you can absorb the cost; otherwise alumina is the sensible default. Note that a silicon die’s CTE (~2.6–3 ppm/°C) is much closer to either ceramic than to plastic, so first-level (die-to-package) stress is rarely the limiter — the board interface is.
A third ceramic worth knowing is beryllia (BeO). It conducts heat even better than alumina and shows up in legacy high-power and RF parts, but beryllium-oxide dust is a serious inhalation hazard to machine, so new designs generally choose AlN instead. If a datasheet still lists BeO, factor the handling and disposal constraints into your sourcing decision.
Hermeticity, screening, and the standards stack
Hermeticity is the property you are paying for, and it is tested, not assumed. MIL-STD-883 Method 1014 (“Seal”) determines the effectiveness of the hermetic seal on devices with an internal cavity, expressed as a standard leak rate in atm·cc/s. In practice, fine-leak detection resolves helium rates down to about 5 × 10⁻⁹ atm·cc/s, gross-leak screens catch rates of 10⁻⁵ and above, and reference packages are qualified with known hermeticity below 5 × 10⁻⁸ cc·atm/s. Why the tight numbers matter: at a marginal leak, moisture ingress is only a matter of time. A 0.9 cm³ cavity leaking at 1 × 10⁻⁸ atm·cm³/s reaches the moisture limit in about 1.08 years — which is why flight seals are specified far tighter.
That sealed, dry cavity is also why ceramic hermetic parts sidestep the moisture-sensitivity-level (MSL) baking-and-bagging that plastic surface-mount parts require: there is no organic body to absorb moisture and flash to steam during reflow. If a vendor hands you an MSL rating on a truly hermetic ceramic part, ask why.
For qualification, hi-rel ceramic microcircuits flow through the QML system. MIL-PRF-38535 defines QML flows for ceramic quad flatpack (CQFP), ceramic column grid array (CCGA), and ceramic pin grid array (CPGA), across the −55 °C to +125 °C military range, with case outlines pulled from MIL-STD-1835 descriptive type designators. Space “Class S/V” adds the tightest screening. Method 1014 is only one screen in a longer MIL-STD-883 sequence, so passing a seal test is necessary but not sufficient — a compliant part also clears mechanical, thermal, and electrical screens before it earns its flow. Assembled-part reliability is then demonstrated by test: one CCGA-1752 space evaluation ran units through 1,000-, 1,500-, 2,000-, 3,000-, and 4,000-cycle read points.
How to choose
- Pin count first. Under ~64, a CDIP or small CQFP is simplest. Into the hundreds, CQFP or an area array. Past ~1,000, you are in CBGA/CCGA territory.
- Then thermal-cycling severity. Wide swings or many cycles favor compliant leads (CQFP, CDIP) over columns, and columns over balls. If the mission cycles hard, a leaded part may beat a denser area array on lifetime.
- Then body size. If the die forces a body past ~32 mm, skip CBGA and specify CCGA.
- Then assembly capability. CQFP and CDIP assemble on ordinary lines; CCGA needs column-attach expertise and often corner staking. Match the package to your (or your assembler’s) real capability.
- Then socketing and cost. If you need removability, CPGA. If cost dominates and pin count is low, glass-sealed CDIP.
Board-level mistakes that cause returns
- Ignoring CTE mismatch on CBGA. Dropping a large ceramic BGA onto standard FR-4 with no analysis is the classic field-failure path; the joints fatigue at the die-shadow corners. Model it or move to columns.
- Wrong package for the thermal profile. Choosing a dense area array for a design that cycles hard trades lifetime for density. The RTG4 CQFP option exists precisely because high-cycle applications punish CCGA.
- Bent CQFP leads and coplanarity. Fine-pitch gull-wing leads that fall out of coplanarity open under reflow. Inspect before placement; never rework a flight lead by hand.
- Damaged CPGA pins. A single splayed pin ruins insertion. Handle in trays, not loose.
- Assuming rework is easy. Ceramic area-array parts are hard and risky to rework; failures often occur at the board-to-column or column-to-substrate interface. Design to avoid rework, not to survive it.
Second-source reality
Hi-rel ceramic parts are single- or dual-sourced, and the “same” die can appear in several packages with different suitability. Confirm the exact case outline, not just the family.
| Device family | Vendor | Ceramic package options | Notes |
| Virtex-5QV (rad-hard FPGA) | AMD/Xilinx | CCGA (e.g., CF1752, 1,752 columns) | 65-nm; TID >1 Mrad(Si); SEL-immune |
| Virtex-4QV (rad-hard FPGA) | AMD/Xilinx | CF1140 ceramic column grid array (1,140 columns) | Legacy flight parts |
| RTG4 (rad-tolerant FPGA) | Microchip | CG1657 (CCGA), LGA1657, CB1657 (CBGA, prototyping only), CQ352 (CQFP) | Same die, four footprints |
The RTG4 line is the clearest lesson here: one die, offered as columns for maximum I/O, as a CQFP for easier assembly and hard thermal cycling, and as a ball array only for the lab bench.
FAQ
What is a ceramic IC package?
It is a hermetic housing that seals a semiconductor die inside alumina or aluminum-nitride ceramic and closes it with a metal or ceramic lid. It blocks moisture and contamination, conducts heat far better than plastic, and tolerates wide temperature ranges, so it is used where reliability is non-negotiable.
What is the difference between CDIP and CERDIP?
Both are ceramic dual in-line packages. CERDIP is the glass-sealed construction; a side-braze CDIP brazes the leads to a co-fired ceramic body. Side-braze parts handle higher assembly temperatures and rougher use; glass-sealed CERDIPs are cheaper to manufacture. Electrically they are similar; the difference is mechanical robustness and cost.
What is the difference between CBGA and CCGA?
CBGA uses solder balls; CCGA uses taller solder columns. Columns are more compliant, so they survive the ceramic-to-PCB expansion mismatch on larger bodies. CCGA extends the workable body size from about 32 mm for CBGA to 52.5 mm, which is why big space-grade FPGAs are columns, not balls.
Are ceramic packages hermetic, and how is that verified?
Yes — a true ceramic package is hermetically sealed. Hermeticity is verified per MIL-STD-883 Method 1014, with fine-leak sensitivity around 5 × 10⁻⁹ atm·cc/s of helium and gross-leak screening at 10⁻⁵ and above. Because the cavity is sealed and dry, these parts do not carry a plastic-style moisture-sensitivity level.
Why are ceramic packages more expensive than plastic?
Ceramic materials and their co-fired, brazed, and hermetically sealed manufacturing cost more than molded plastic. You pay for hermeticity, temperature range, thermal performance, and the screening that hi-rel and space applications demand — not for the package alone.
When should I use CQFP instead of a column grid array?
Choose CQFP when pin count is moderate (a few hundred), when you want ordinary SMT assembly, or when the design cycles temperature hard. Its compliant gull-wing leads handle expansion mismatch better than columns, and it is easier and cheaper to integrate than a CCGA.
The bottom line
Pick the package by interconnect and mission, not by pin count alone. If your design cycles temperature hard or lives under ~64 I/O, a leaded CDIP or CQFP will outlast a denser area array and assemble on any line. If you need maximum I/O in a hermetic body, use CBGA only below ~32 mm and move to CCGA above it — and treat a ceramic ball array on a large die as a bench part, exactly as Microchip labels the CB1657. Whatever you choose, confirm the exact MIL-STD-1835 case outline, demand Method 1014 hermeticity data, and specify the QML flow your reliability target requires before you release the footprint.
External references: MIL-STD-1835D (DLA Land & Maritime); MIL-STD-883 Method 1014 (SEAL); AMD Virtex-5QV product page; Microchip/Microsemi RTG4 packaging announcement; NASA NEPP BGA selection guidelines; TI packaging terminology.
[INTERNAL LINK: hermetic sealing and MIL-STD-883 screening → hermeticity/qualification article]
[INTERNAL LINK: space-grade FPGA selection → rad-hard / rad-tolerant FPGA guide]
[INTERNAL LINK: CBGA vs QFP for high-pin designs → package-format comparison]
[INTERNAL LINK: managing CTE mismatch in PCB layout → thermal / mechanical design article]
