A ball grid array isn’t one package — it’s a family that differs mainly in substrate material and how the die attaches. The BGA package types you’ll meet on a datasheet — PBGA, FBGA, FCBGA, CBGA, TBGA, µBGA — trade cost, thermal performance, and I/O density against each other. This guide decodes each one with real numbers, shows how to read a package code, and gives you a selection path you can apply at your desk.
Key takeaways
- Substrate (plastic, ceramic, or tape) and die-attach (wire-bond vs flip-chip) define the variant. Everything else follows from those two choices.
- PBGA is the low-cost default; FCBGA is what you use when the silicon demands low inductance and high I/O density; CBGA buys thermal and reliability headroom at a price.
- Ball pitch runs from 1.27 mm down to 0.4 mm and finer — and pitch, more than type, dictates your layer count and via strategy.
- The package is usually chosen for you by the chip vendor. Your real job is to route it, cool it, and reflow it without cracking it.
- Watch moisture sensitivity level (MSL) and footprint migration early; both cause expensive surprises late.
What “BGA” actually covers
A BGA package places its connections as an array of solder balls on the underside of the part. During reflow, those balls melt and join to matching pads, forming both the electrical and the mechanical connection. Because the joints sit hidden beneath the body, they’re verified by X-ray, not by eye.
The label spans everything from a 4-ball chip-scale part to a 3,824-ball, 65 mm monster. What separates the variants is three questions: what is the substrate made of, is the die flip-chip mounted or wire-bonded, and does the part even have balls (an LGA has lands and takes its solder from the board’s paste). The outlines themselves are standardized by JEDEC JEP95, which holds over 500 registered package drawings.
The main BGA package types, decoded
PBGA — plastic ball grid array
The workhorse. The die sits on an organic laminate substrate — historically BT (bismaleimide-triazine) resin, a construction Motorola pioneered — and connects by wire bonds. PBGA is the cheapest mainstream option and dominates consumer and industrial parts. Wire-bond PBGAs in the 200–500 ball range are common. The trade-off is electrical: wire bonds add inductance, which limits high-speed performance.
FBGA — fine-pitch ball grid array
FBGA is PBGA’s dense cousin: same basic build, tighter ball spacing (typically 0.8 mm or less) to pack more I/O into a smaller footprint. It’s the go-to for DRAM and space-constrained mobile parts. In Xilinx nomenclature, an FBG or FGG code denotes a fine-pitch wire-bond array — for example the Artix-7 FBG676 (676 balls, 27×27 mm).
FCBGA — flip-chip ball grid array
The high-performance choice. The die is flipped face-down and bonded to the substrate through solder bumps (a C4-style interconnect) instead of wire bonds. That shortens the electrical path dramatically, cutting parasitic inductance and freeing the whole die face for I/O and power distribution. Nearly every large FPGA ships as an FCBGA: the Kintex UltraScale XCKU115 is a 2,104-ball FCBGA in a 47.5×47.5 mm body. FCBGA also heatsinks directly to the die backside, so it handles the highest power. The cost is substrate and board complexity — multi-layer laminate, microvias, and HDI move from optional to mandatory.
CBGA — ceramic ball grid array
A ceramic substrate replaces the organic laminate, buying thermal stability and a coefficient of thermal expansion (CTE) close to silicon — excellent for thermal cycling in mil/aero and high-reliability parts. Ceramic balls run a high-lead alloy (roughly 90/10 Sn-Pb) with a melting point above eutectic reflow, so a C4 connection is used. CBGA is reliable and expensive; reserve it for parts that earn it.
TBGA — tape ball grid array
Built on a flexible tape (flex) substrate rather than rigid laminate. TBGA shrinks package thickness and suits large ASIC and microprocessor dies with high I/O. It offers good electrical behavior but generally costs more than PBGA.
µBGA, CSP, and the successors
µBGA (micro-BGA, ball spacing under 1 mm) and chip-scale packages (CSP) push toward the die’s own footprint. At the extreme, WLCSP (wafer-level chip-scale package) is essentially a bumped die with no separate substrate, and eWLB (embedded wafer-level BGA) adds a fan-out interposer. These are where miniaturization is heading, but they demand the finest PCB features.
The close relatives: LGA and PoP
LGA (land grid array) is a BGA without the balls — flat lands take solder from the board’s stencil paste. PoP (package-on-package) stacks devices vertically, typically logic under memory, to save board area. Neither is a “BGA type” strictly, but both show up in the same selection conversations.
[IMAGE 1: cross-section comparison of PBGA wire-bond vs FCBGA flip-chip construction | alt: “BGA package types cross-section comparing PBGA wire-bond and FCBGA flip-chip die attach”]
BGA package types compared
The differences that matter to a design engineer, side by side.
| Type | Substrate | Die attach | Typical pitch | Relative cost | Thermal | Best for |
| PBGA | Organic (BT laminate) | Wire bond | 1.27–0.8 mm | Low | Moderate | Cost-driven consumer/industrial parts |
| FBGA | Organic | Wire bond | ≤0.8 mm | Low–moderate | Moderate | High I/O density in a small body |
| FCBGA | Advanced laminate / ceramic | Flip-chip (C4) | 1.0–0.8 mm+ | High | Excellent | High-speed, high-pin-count FPGAs/CPUs |
| CBGA | Ceramic | Wire bond / C4 | 1.27–1.0 mm | Very high | Excellent | Mil/aero, thermal-cycling reliability |
| TBGA | Tape (flex) | Wire bond / flip-chip | 1.0 mm | Moderate–high | Good | Large ASICs, thin profiles |
| µBGA / CSP | Minimal / none (WLCSP) | Bumped die | ≤0.5 mm | Varies | Package-dependent | Extreme miniaturization |
How to choose: a selection decision path
In practice the chip vendor picks the package family for you — you rarely get a free choice between PBGA and FCBGA for the same silicon. Where you do choose, and where you decide whether a part is buildable on your board, work through it in this order:
- Signal integrity first. Multi-gigahertz serial links or tight SSO budgets push you to FCBGA for its low inductance. Moderate-speed logic is fine on PBGA/FBGA.
- Thermal envelope next. Estimate worst-case power and junction temperature. If passive cooling can’t hold your target Tj, move to a flip-chip part with a backside lid, or to CBGA/EBGA in extreme cases.
- Mechanical and environmental. Thermal-cycling or high-vibration service favors ceramic’s CTE match, or column-grid arrays where solder-joint fatigue dominates.
- Pitch versus your PCB process. This is the sleeper constraint — a 0.4 mm part can be electrically ideal and still blow your board budget.
- Cost and second-source last. PBGA wins on price; verify a footprint-compatible alternate before you commit.
Worked example. A mid-range FPGA design needs ~200 single-ended I/O, no transceivers, moderate clock rates, and lowest board cost. On an Artix-7, the CSG324 (210 I/O, 15×15 mm, no GTP) fits — a wire-bond fine-pitch part routable on a modest stack-up. If the same design later needs two PCIe/GTP lanes, the CPG236 (10×10 mm, 0.5 mm pitch, 106 I/O, 2 GTP) delivers them, but its 0.5 mm pitch forces at least a six-layer board. Same family, very different board cost — driven by pitch, not by “BGA type.”
Reading the package code on a datasheet
A package code encodes body, pitch, and ball count. Learning to read it turns a cryptic string into design data. Using AMD/Xilinx conventions as the example, a code like XCKU040-2FFVA1156E parses as device (KU040) / speed grade (-2) / package (FFVA1156 = flip-chip fine-pitch array, 1,156 balls) / temperature (E). The “A1156” body is footprint-compatible across Kintex UltraScale and UltraScale+, so you can migrate silicon without re-laying-out the board — a genuine schedule saver.
Real Artix-7 package parametrics, from the product table:
| Package | Body size | Ball pitch | Example max I/O | Notes |
| CPG236 | 10×10 mm | 0.5 mm | 106 | Compact, includes 2 GTP; needs ≥6 layers |
| CSG324 | 15×15 mm | 0.8 mm | 210 | Max I/O, no transceivers |
| FTG256 | 17×17 mm | 1.0 mm | 170 | Easy to route |
| FGG484 | 23×23 mm | 1.0 mm | 285 | Four transceivers |
| FBG676 | 27×27 mm | 1.0 mm | 400 | High I/O wire-bond |
| FFG1156 | 35×35 mm | 1.0 mm | 500 | Flip-chip, top of family |
Flip-chip parts publish standoff and height too — for Xilinx flip-chip BGAs the FF668/672 (27×27 mm, 1.0 mm pitch) specifies a 0.50 mm ball standoff and 2.65 mm package height, while the larger BF957 (40×40 mm, 1.27 mm pitch) runs a 0.60 mm standoff and 3.25 mm height. Those numbers feed your stencil, keep-out, and mechanical clearance decisions.
Layout and assembly realities
The package type constrains three things that decide whether your board actually yields.
Escape routing scales with pitch, not type. The threshold most designers hit is around 0.5 mm pitch.
| Ball pitch | Escape method | PCB technology |
| ≥0.8 mm | Dog-bone fanout (via between four pads) | Standard through-hole |
| 0.65–0.8 mm | Dog-bone, tight; oval pads help | Standard, careful DFM |
| ≤0.5 mm | Via-in-pad, filled and capped | HDI with microvias |
Below ~0.65 mm you typically need HDI microvias; at ≤0.5 mm the via must sit in the pad, filled and planarized as a plated-over-filled-via (POFV) — an IPC-4761 Type VII structure — to stop solder wicking. A 400-pin part at 0.5 mm pitch commonly needs 8–10 layers.
Pad definition affects fatigue. Non-solder-mask-defined (NSMD) pads expose the copper sidewall so solder anchors around the pad; the pad runs roughly 20% smaller than the ball diameter, and the exposed anchor improves thermal-cycling fatigue life on the order of 15–20% versus solder-mask-defined pads. NSMD is the default for fine-pitch BGAs.
Moisture matters before reflow. Plastic BGAs are non-hermetic and absorb moisture that flashes to steam at reflow, “popcorning” the package. Per IPC/JEDEC J-STD-020, parts carry a moisture sensitivity level (MSL) from 1 (unlimited floor life) to 6. An MSL 5 part allows 48 hours of exposure at 30 °C/60% RH; MSL 5a drops that to 24 hours. Exceed it and you bake — typically 125 °C for 48 hours for a moderately sensitive part, per J-STD-033. Note that tape-and-reel carriers can’t go above 40 °C, so plan trays for high-temp bakes. Lead-free reflow peaks near 260 °C, well above the ~217 °C liquidus, which is exactly why the moisture rules exist.
[IMAGE 2: escape routing diagram showing dog-bone fanout vs via-in-pad by pitch | alt: “BGA escape routing dog-bone fanout versus via-in-pad across ball pitch”]
Lifecycle, second-sourcing and migration
Two lifecycle traps hit BGA designs hardest. First, footprint migration: within a vendor family, “like packages” often let you swap device sizes without a re-layout — Artix-7 supports device migration for like packages within the family, but not across 7-series families. Confirm the migration table before you assume a drop-in. Second, second sourcing is thin at the high end; a 2,000-ball FCBGA rarely has a true pin-compatible alternate, so treat availability as a design input, not an afterthought. For large flip-chip parts, even substrate supply can gate lead time — vendors qualify multiple substrate sources precisely because it’s a bottleneck.
Frequently asked questions
What is a BGA package?
A BGA (ball grid array) is a surface-mount IC package that carries its connections as a grid of solder balls on the underside of the part. During reflow the balls melt onto matching PCB pads, forming the electrical and mechanical joint. Because the joints are hidden, they’re inspected by X-ray rather than visually.
What’s the difference between PBGA and FCBGA?
PBGA connects the die to its substrate with wire bonds on an organic laminate; FCBGA flips the die face-down and bonds it through solder bumps. Flip-chip shortens the interconnect, cutting inductance and boosting I/O density and thermal performance — at higher substrate and board cost. PBGA is the economical default.
What does FBGA stand for?
FBGA means fine-pitch ball grid array — a BGA with tighter ball spacing (commonly 0.8 mm or finer) to fit more I/O in a smaller body. It’s widely used for DRAM and mobile parts. In some vendor nomenclatures the same letters appear in package codes like FBG676.
What is the difference between BGA and LGA?
A BGA has solder balls pre-attached to the package; an LGA (land grid array) has flat lands and takes its solder from the board’s stencil paste. LGA suits socketed or rework-friendly designs; BGA gives better standoff and is the norm for high-pin-count surface-mount parts.
What is the smallest BGA ball pitch?
Mainstream BGA pitch ranges from 1.27 mm down to about 0.4 mm, with wafer-level CSPs going finer. Below roughly 0.5 mm you need via-in-pad and HDI microvias, which is why pitch — not package type — usually sets your PCB technology and layer count.
Do BGAs need to be baked before reflow?
Only if their MSL floor life has been exceeded. Per J-STD-020/033, an MSL 1 part is unlimited, while sensitive parts (MSL 3 and higher) have floor lives from days down to 24 hours. If exposure is exceeded or the humidity indicator card reads high, bake per the datasheet — often 125 °C for 48 hours — before soldering.
The bottom line
Pick the BGA variant the way the physics forces you to, not by acronym familiarity. If your silicon runs multi-gigahertz links or dissipates real power, you’re on FCBGA — budget for HDI and tighter reflow control. If cost rules and speeds are moderate, PBGA/FBGA is right, and your effort shifts to escape routing and MSL discipline. Reserve CBGA for genuine thermal-cycling or reliability demands. In every case, read the pitch first: it decides your layer count and via strategy before any other spec does. Verify footprint migration and second-source availability while the schematic is still soft — those are the choices that are cheap now and expensive at production.
Related reading (internal):
- FPGA package selection guide → device-package trade-offs
- BGA PCB layout and escape routing → fanout and via-in-pad techniques
- Understanding FPGA part numbers → decoding device/speed/package/temperature codes
External primary sources: JEDEC JEP95 Registered Outlines (jedec.org); IPC/JEDEC J-STD-020 moisture/reflow classification; AMD/Xilinx Advanced Packaging and Artix-7 product tables (xilinx.com / docs.amd.com); TI MSL & handling application report (ti.com).
