A TSSOP-32 package carries 32 gull-wing leads on 0.65 mm pitch. The version most vendors ship measures 10.9 mm to 11.1 mm long by 6.0 mm to 6.2 mm wide, with a lead span of 7.9 mm to 8.3 mm and a maximum height of 1.1 mm without an exposed pad or 1.2 mm with one. JEDEC’s index of registered MO-153 variations contains no 32-lead entry, so the vendor drawing, not the package name, defines your land pattern.

Key takeaways

• Nominal geometry: 0.65 mm pitch, 11.0 mm by 6.1 mm body, 7.9 mm to 8.3 mm lead span. NXP (SOT487-1) and Texas Instruments (DAP0032C) publish the same numbers.
• JEDEC’s device-type index lists MO-153 lead counts from 8 to 68 and skips 32. A 32-lead TSOP Type 1 is registered, under MO-142.
• Richtek publishes a TSSOP-32 land pattern with a 7.00 mm outer span, roughly 2 mm narrower than the 6.1 mm body pattern. Same name, different board.
• The exposed pad carries the thermal story: TI rates a 32-lead HTSSOP at 42.54 mW per °C with the pad soldered and 22.56 mW per °C without it.
• A TSSOP-32 land pattern occupies about 92 mm² against about 23 mm² for the VQFN-32 option on the same die.

[IMAGE 1: dimensioned top, side and end view of a 32-lead TSSOP with pitch, lead span and height called out | alt: “TSSOP-32 package dimensions showing 0.65 mm pitch and 8.1 mm nominal lead span”]

What TSSOP-32 specifies, and what it leaves open

The name gives you three facts: a thin shrink small outline body, two rows of gull-wing leads, and 32 of them. Convention adds 0.65 mm pitch. Body width is vendor territory.

JEDEC Publication 95, in its index by device type, lists MO-153 with registered lead counts of 8, 14, 16, 20, 24, 28, 36, 40, 48, 52, 56, 60, 64 and 68. There is no 32. The same index does register 32-lead parts elsewhere: TSOP Type 1 under MO-142, and TSOP Type 2 under MO-133 and MO-135. A gap in a registration index is not a gap in the market, and vendors fill it their own way.

Both major drawings still point at the family. NXP lists MO-153 as the JEDEC outline code for SOT487-1, with an issue date of 18 February 2003. TI’s DAP0032C drawing carries the note that it references JEDEC registration MO-153. Read those as family alignment, not as a promise that two parts labelled TSSOP-32 share a footprint.

TSSOP-32 dimensions

Table 1 puts two independent drawings side by side: the plain 32-lead TSSOP from NXP and the exposed-pad version from TI.

Table 1. TSSOP-32 mechanical data from two vendor drawings, dimensions in mm

Parameter	NXP SOT487-1 (TSSOP32)	TI DAP0032C (HTSSOP-32, PowerPAD)
Leads	32	32
Lead pitch, e	0.65	0.65 (30 spaces shown)
Body length, D	10.9 to 11.1	10.9 to 11.1
Body width, E	6.0 to 6.2	6.0 to 6.2
Lead span, HE	7.9 to 8.3	7.9 to 8.3
Height, A max	1.1	1.2
Body thickness, A2	0.85 to 0.95	not dimensioned on drawing
Standoff, A1	0.05 to 0.15	0.05 to 0.15
Lead width, b	0.19 to 0.30	0.19 to 0.30
Lead thickness, c	0.09 to 0.20	not dimensioned on drawing
Foot length, Lp	0.50 to 0.75	0.50 to 0.75
Lead angle	0 to 8 degrees	0 to 8 degrees
Exposed pad	none	2.46 to 3.04 by 3.16 to 3.74
JEDEC reference	MO-153	MO-153 (reference)

The two agree to the hundredth of a millimetre on body, lead span, lead width and foot length. They part company on height. The plain package is 1.1 mm maximum; the exposed-pad version is 1.2 mm. If the enclosure gives you 1.15 mm above the board, that 0.1 mm decides the part number.

Two packages, one name: check the lead span first

Richtek’s published footprint file for TSSOP-32 specifies 0.65 mm pitch, lands 0.35 mm wide by 1.00 mm long, an outer span of 7.00 mm across the two rows, an inner span of 5.00 mm and a total row length of 10.10 mm, all to plus or minus 0.10 mm. Richtek’s TSSOP-20 footprint file carries the identical 7.00, 5.00, 1.00 and 0.35 set, and a 20-lead TSSOP is a 4.4 mm wide body. Place a 6.1 mm body part on that pattern and the toes hang off the copper by roughly a millimetre per side.

The working rule is short. Match the land pattern to the lead span dimension on the drawing for the exact orderable part number, never to the string TSSOP-32 in a library or a BOM. Distributor package fields are not specifications either: Digi-Key lists the same TLC5947 reel as 32-PowerTSSOP with a 6.10 mm width in one field and as 32-HTSSOP in another.

TSSOP-32 pinout is a device property, not a package property

There is no TSSOP-32 pinout to look up. Function assignment belongs to the silicon, and it moves when the package changes. In TI’s TLC5947, GND sits on pin 1 in the 32-pin HTSSOP and on pin 29 in the 32-pin VQFN. VCC is pin 32 in one and pin 28 in the other. Same die, same 24 outputs, different numbers.

What the package does fix is geometry. Pin 1 sits at the index feature marked on the drawing, numbering runs counterclockwise seen from the top, pins 1 to 16 fill one long side and 17 to 32 return along the other, so 16 and 17 face each other across the short end. Every device-specific pin table you use should be read against that frame.

Footprint, thermal land and stencil apertures

TI’s example land pattern for the 32-lead PowerPAD TSSOP uses 32 lands 1.5 mm long by 0.45 mm wide at 0.65 mm pitch, with the rows on 7.5 mm centres, non solder mask defined, and 0.05 mm of mask clearance all around. The thermal land is 3.04 mm by 3.74 mm with 0.2 mm vias on roughly 1.2 mm to 1.3 mm centres, filled, plugged or tented where they sit under paste.

Aperture size tracks foil thickness so that paste volume under the pad stays constant. TI publishes 3.40 mm by 4.18 mm for a 0.100 mm stencil, 3.04 mm by 3.74 mm for 0.125 mm, 2.78 mm by 3.41 mm for 0.150 mm and 2.57 mm by 3.16 mm for 0.175 mm. Carry the 0.125 mm aperture onto a 0.175 mm foil unchanged and you deposit about 40 percent more paste than the drawing intends, which is how packages float and tilt.

Board area follows from the same pattern. Along the rows, 15 spaces at 0.65 mm plus one land width gives 10.2 mm. Across the rows, 7.5 mm of centre spacing plus one land length gives 9.0 mm. That is about 92 mm². The VQFN-32 pattern for the same device measures 4.8 mm by 4.8 mm, about 23 mm², so the TSSOP costs you four times the copper for identical function.

One number worth checking with your fabricator: the gap between adjacent lands is 0.65 mm minus 0.45 mm, which is 0.20 mm. Confirm the minimum solder mask dam before specifying mask between pins.

[IMAGE 2: land pattern drawing with 32 lands, row centre spacing, thermal land and via array | alt: “TSSOP-32 footprint with 1.5 mm by 0.45 mm lands on 0.65 mm pitch and a thermal land via array”]

Thermal performance: what the exposed pad actually buys

TI’s dissipation table for the TLC5947 gives three derating factors: 42.54 mW per °C for the HTSSOP-32 with the PowerPAD soldered to copper, 22.56 mW per °C with the pad unsoldered, and 27.86 mW per °C for the VQFN-32. Invert those against a 150 °C junction limit and the effective junction-to-ambient resistances are about 23.5, 44.3 and 35.9 °C per W. Soldering the pad is worth roughly a factor of two, and it puts the 11 mm long TSSOP ahead of the 5 mm QFN.

The same datasheet also lists RthetaJA of 32.8 °C per W in its thermal information table, measured on the JEDEC board rather than the 2 oz copper condition behind the derating table. One package, two published numbers, a 40 percent spread. Budget with the JEDEC figure unless your board genuinely matches the other condition: at 85 °C ambient and a 150 °C junction limit, 32.8 °C per W allows 1.98 W, against the 2.765 W the derating table permits.

The direction of heat flow settles the layout argument. RthetaJC through the bottom is 1.3 °C per W; through the top it is 17.1 °C per W. The path down through the pad is roughly 13 times better, so a clip-on heatsink on the plastic does little. The copper under the package is the heatsink.

Table 2. Same die, two package options, from the TLC5947 datasheet and TI package drawings

Attribute	HTSSOP-32 (DAP)	VQFN-32 (RHB)
Body size	11.0 by 6.2 mm	5.0 by 5.0 mm
Lead pitch	0.65 mm	0.5 mm
Height, max	1.2 mm	1.0 mm
Land pattern area	about 92 mm²	about 23 mm²
Derating factor	42.54 mW/°C pad soldered, 22.56 mW/°C unsoldered	27.86 mW/°C
Implied junction-to-ambient	about 23.5 °C/W soldered, 44.3 °C/W unsoldered	about 35.9 °C/W
Rated power at 85 °C	2765 mW soldered, 1466 mW unsoldered	1811 mW
Moisture sensitivity	Level 3, 260 °C, 168 h floor life	Level 2, 260 °C, 1 year
Tape and reel	24 mm tape, 12 mm pocket pitch, 2000 per 330 mm reel	12 mm tape, 8 mm pocket pitch, 3000 per 330 mm reel
Tube option	46 per tube	none listed
Joint inspection	visible fillets, optical inspection	bottom terminated, X-ray or endoscope

Assembly, moisture sensitivity and sourcing checks

The packaging addendum for the TLC5947 rates the HTSSOP-32 at Level 3 with a 260 °C peak and a 168 hour floor life, while the VQFN-32 version of the same device is Level 2 with one year. The leaded package is the more moisture-sensitive of the two here, which is the opposite of what most engineers assume. Classification follows IPC/JEDEC J-STD-020; handling and rebake rules follow J-STD-033. On a line that opens a reel on Monday and finishes the build on Friday, that difference is a real bake cycle.

Feeder and packing details matter at ramp. The 32-lead HTSSOP ships in 24 mm tape at 12 mm pocket pitch, 2000 per 330 mm reel, with a 46-piece tube for prototypes. The QFN version ships in 12 mm tape at 8 mm pitch, 3000 per reel. Check that the line has 24 mm feeders free before committing.

On price and lifecycle, Arrow listed the TLC5947DAPR at 1.801 US dollars each in 2000-piece increments with a quoted six-week factory lead time when checked in August 2026, while Digi-Key showed the TLC5947DAPRG4 order code as discontinued at that distributor even though the base part is active at TI. Order-code suffixes carry their own lifecycles. Verify the exact suffix on your BOM rather than the base part number.

One more lifecycle signal: NXP’s TSSOP32 outline page lists two associated products, TDA6509TT and TDA6509ATT. At that vendor, 32-lead TSSOP is a legacy body carrying legacy silicon. If you need a second source, plan for a QFN-32 or a different lead count rather than expecting a drop-in TSSOP-32 alternative.

Five mistakes that send TSSOP-32 boards back

1. Pulling a library footprint named TSSOP-32 without checking its span against the drawing. The two published patterns differ by roughly 2 mm across the rows.
2. Leaving the thermal land without vias, or floating. The rated dissipation falls from 42.54 to 22.56 mW per °C, and the part reaches thermal shutdown at half the expected load.
3. Reusing one stencil aperture across foil thicknesses, which changes paste volume under the pad by tens of percent and produces tilt and open leads.
4. Budgeting 1.1 mm of z-height and then buying the exposed-pad version at 1.2 mm maximum.
5. Carrying pin numbers between package options of the same device, when GND can move from pin 1 to pin 29.

TSSOP-32 package FAQ

What are the dimensions of a TSSOP-32 package?

Body length runs 10.9 mm to 11.1 mm and body width 6.0 mm to 6.2 mm, with a lead span of 7.9 mm to 8.3 mm on 0.65 mm pitch. Height is 1.1 mm maximum without an exposed pad and 1.2 mm with one. Lead width is 0.19 mm to 0.30 mm and foot length 0.50 mm to 0.75 mm, per the NXP SOT487-1 and TI DAP0032C drawings.

What is the pitch of a TSSOP-32 package?

Every 32-lead TSSOP drawing checked here uses 0.65 mm: NXP SOT487-1, TI DAP0032C and the Richtek footprint file. The wider TSSOP family also appears at 0.5 mm pitch on higher lead counts, so read the pitch off the drawing for your orderable part instead of assuming 0.65 mm.

Is TSSOP-32 the same as TSOP-32?

No. TSOP is a separate family with its own JEDEC registrations, and unlike TSSOP it does register 32 leads, under MO-142 for Type 1 and MO-133 and MO-135 for Type 2. Memory TSOP bodies are commonly 8 mm wide, against 6.1 mm for TSSOP-32, and pitch and land pattern differ.

What is the difference between TSSOP-32 and HTSSOP-32?

HTSSOP is TI’s name for a TSSOP carrying an exposed thermal pad underneath. Lead geometry matches, maximum height grows from 1.1 mm to 1.2 mm, and the board needs a thermal land with vias. In return, rated dissipation nearly doubles once that pad is soldered down.

Can a TSSOP-32 be hand soldered?

The 0.65 mm pitch drag-solders acceptably with flux and a fine tip, which keeps TSSOP alive in prototypes. The exposed pad is the obstacle, since an iron cannot reach it from above. Reflow from below with a hot plate or hot air, or accept the unsoldered-pad rating of 22.56 mW per °C.

What to do next

Open the package outline drawing for the exact orderable part number and check three numbers before routing: lead span, maximum height, and whether an exposed pad exists. If the lead span reads 7.9 mm to 8.3 mm, draw 1.5 mm by 0.45 mm lands on 0.65 mm pitch with the rows on 7.5 mm centres. If the part carries a pad, take the thermal land and via array from the same drawing and size the stencil aperture to your actual foil thickness.

Change packages when the numbers say so, not out of habit. Below roughly 50 mm² of available board area, or above about 2 W of dissipation at 85 °C ambient, the QFN-32 option on the same die is the better engineering answer, and the price is X-ray inspection instead of visible fillets. Above 1.2 mm of z-height headroom and with hand rework in the plan, TSSOP-32 remains the easier package to build and to debug.

[IMAGE 3: side-by-side land patterns, TSSOP-32 against a 5 mm VQFN-32, drawn to the same scale | alt: “TSSOP-32 footprint area compared with a 5 mm QFN-32 land pattern”]

Internal links

• [INTERNAL LINK: QFN-32 package -> QFN versus TSSOP thermal and assembly comparison]
• [INTERNAL LINK: exposed pad thermal via design -> PowerPAD and thermal land layout guide]
• [INTERNAL LINK: moisture sensitivity level -> MSL floor life, baking and dry pack handling]
• [INTERNAL LINK: SSOP versus TSSOP -> small outline package family selection guide]
• [INTERNAL LINK: solder paste stencil design -> aperture sizing for fine-pitch and exposed-pad parts]

External references

• NXP SOT487-1 package information (TSSOP32): https://www.nxp.com/docs/en/package-information/SOT487-1.pdf
• Texas Instruments TLC5947 datasheet, drawings DAP0032C and RHB0032E: https://www.ti.com/lit/ds/symlink/tlc5947.pdf
• JEDEC Publication 95 index by device type: https://www.jedec.org/sites/default/files/MOIND_DT.pdf
• Richtek TSSOP-32 footprint file: https://www.richtek.com/assets/podfiles/Footprint-TSSOP-32.pdf
• Microchip (SST) application note S72015 on TSOP land patterns: https://ww1.microchip.com/downloads/en/Appnotes/S72015.pdf