TSOP Type I puts its gull-wing leads on the two shorter edges of a rectangular thin package. JEDEC registers the outline as MO-142 at 24, 32, 40, 48 and 56 leads. That one geometric choice sets the pitch, the body size progression and the way every signal has to leave the part. Below are the sizes, the scaling rule behind them, and the routing arithmetic that decides whether you can escape the footprint on one layer.
Key takeaways
- JEDEC’s own dictionary defines TSOP1 as the variant with leads on the ends or short edges; TSOP2 has them on the long edges.
- Type I scales lead count by widening the short edge while holding 0.50 mm pitch, leaving a consistent 0.25 mm margin at each end of the lead row.
- The long axis stays at roughly 20 mm across the 32, 48 and 56-lead sizes. Only the width changes.
- At 0.50 mm pitch with an IPC-nominal pad you cannot fit a track between adjacent pads. Every net escapes outward or drops to an inner layer.
- On parallel NOR flash the two lead rows split cleanly: address bus at one end, data bus at the other.
[IMAGE 1: TSOP Type I 48-lead outline with the short-edge lead rows, lead span and pitch dimensioned | alt: “TSOP Type I package showing leads on the short edges, 20 mm lead span and 0.5 mm pitch”]
What TSOP Type I means
TSOP Type I is a thin small outline package whose gull-wing leads emerge from the two shorter edges of the body. JEDEC’s dictionary defines TSOP1 as having leads on the ends or short edges, against TSOP2 with leads on the long edges, and notes the pitch is often finer than a standard small-outline package.
Three JEDEC registrations cover it. MO-142 is the main one, titled Thin Small Outline Package (Type I), registering 24, 32, 40, 48 and 56 leads. MO-183 covers a 0.55 mm pitch Type I at 28 leads. MO-259 covers a very very thin Type I at 48 leads. Revision D of MO-142 exists to correct one number: the minimum lead length L, from 0.05 mm to 0.50 mm.
One warning if you go looking. JEDEC’s master index labels the MO-142 entry with a TSOPII descriptor, which is an index error rather than a description of the package. The registration itself is Type I.
How Type I scales: fixed pitch, growing short edge
Here is the rule the ranking pages omit. Type I adds leads by widening the short edge, not by shrinking the pitch and not by lengthening the body. Pitch stays at 0.50 mm across the mainstream sizes, and the long axis stays near 20 mm.
Run the arithmetic on the lead row. Half the leads sit on each short edge, so the row spans (n/2 − 1) × 0.50 mm:
32 leads: 16 per edge, 15 × 0.50 mm = 7.5 mm row in an 8 mm body
40 leads: 20 per edge, 19 × 0.50 mm = 9.5 mm row in a 10 mm body
48 leads: 24 per edge, 23 × 0.50 mm = 11.5 mm row in a 12 mm body
56 leads: 28 per edge, 27 × 0.50 mm = 13.5 mm row in a 14 mm body
Every size leaves exactly 0.25 mm of body at each end of the row. That is not coincidence; it is the constraint the family was drawn around. It also tells you the pin count from a caliper reading: measure the short edge in millimetres, subtract 0.5, divide by 0.5, add 1, then double.
The contrast with Type II is exact and opposite. Type II holds one body and one lead span and shrinks the pitch to add leads. Type I holds the pitch and grows the body. Neither approach is better; they solve different board problems.
TSOP Type I sizes and dimensions
| Leads | Body (mm) | Pitch | Registration | Sourced from |
| 24 | 6 × 16 | 0.50 mm | MO-142 | Renesas drawing PTSA0024KA |
| 28 | see drawing | 0.55 mm | MO-183 | JEDEC JEP95 index |
| 32 | 8 × 20 | 0.50 mm | MO-142 | onsemi CAT28F010H distributor record |
| 40 | 10 × 20 (derived) | 0.50 mm | MO-142 | Lead-row arithmetic above |
| 48 | 12 × 20 | 0.50 mm | MO-142 | Renesas PTSA0048KF, Microchip C04-177, JCET |
| 56 | 14 × 20 | 0.50 mm | MO-142 | Infineon S29GL TS056 outline, JCET |
The 40-lead row is marked as derived because I did not open a drawing for it. The registration exists and the arithmetic gives 10 mm, but confirm against the part you are buying.
For the 48-lead size, Renesas drawing PTSA0048KF gives body 12.0 ± 0.1 mm × 18.4 ± 0.1 mm, lead span 20.0 ± 0.2 mm, 1.20 mm maximum height and 1.00 ± 0.05 mm body thickness. Note the body length and the lead span differ by 1.6 mm. Cypress’s TS056 outline for the 56-lead version repeats the same A1 standoff of 0.05 mm to 0.15 mm and A2 body thickness of 0.95 mm to 1.05 mm on a 14 × 20 mm envelope.
What short-side leads cost you in routing
Every net on a Type I part leaves through one of two narrow ends. On a 48-lead device that is 24 nets escaping through a 12 mm channel at each end, and none escaping sideways.
The question that decides your layer count is whether a track fits between adjacent pads. At 0.50 mm pitch with an IPC-7351B nominal pad width of 0.35 mm, the gap is 0.15 mm. To pass one track you need clearance, track, clearance:
4 mil rules (0.102 mm): 0.102 + 0.102 + 0.102 = 0.305 mm needed
3 mil rules (0.076 mm): 0.076 + 0.076 + 0.076 = 0.229 mm needed
Available with a 0.35 mm pad: 0.150 mm
Neither fits. You cannot route between adjacent pads on a 0.50 mm pitch TSOP Type I with a nominal pad. To get one 3 mil track through, the pad has to come down to about 0.27 mm, which gives 0.23 mm of gap and costs side fillet on every joint.
The practical consequence is a layer decision, not a trace-width decision. Either you fan every net outward from the end of the package, which needs 12 mm of clear board beyond each short edge, or you place a via per net inside the pad row and escape on layer 2. Most parallel flash designs do the second. Budget 24 fanout vias per end on a 48-lead part, and check that your fabricator’s minimum annular ring survives on a 0.5 mm grid.
Address on one end, data on the other
The short-side layout has a pinout consequence that makes the routing easier than it sounds. On parallel NOR flash the two lead rows split by function.
In the Infineon and Cypress S29GL128P through S29GL01GP family, one 28-lead row carries A1 through A23 plus WE#, RESET#, WP#/ACC and RY/BY#. The other carries DQ0 through DQ15 plus BYTE#, OE#, CE#, VIO and the high address lines. The address bus and the data bus leave the package at opposite ends.
That is a gift for floorplanning. Put the controller on the axis of the part, run the data bus off one end and the address bus off the other, and the two never cross. Rotating the flash 180 degrees to suit your controller costs nothing electrically, so decide the orientation from the bus geometry rather than from the silkscreen.
[IMAGE 2: TSOP Type I 48-lead footprint with fanout vias and the two end escape channels marked | alt: “TSOP Type I escape routing with fanout vias at both short-edge lead rows”]
Handling notes specific to Type I flash
Two constraints show up in manufacturer documents rather than package drawings.
Spansion’s S29GL-M datasheet warns that flash memory in molded packages, TSOP included, can have its package or data integrity compromised by exposure above 150 °C for prolonged periods. That is a tighter and more specific limit than a general moisture-sensitivity rule, and it applies to rework and bake cycles, not just reflow. If you bake a populated board to recover floor life, the flash contents are part of what you are risking.
The same datasheet records that SnBi is used for the lead-free TSOP plating. Confirm compatibility with your solder alloy before mixing that finish with a tin-lead process.
JCET, which assembles the 12 × 20 mm and 14 × 20 mm Type I bodies, rates them at JEDEC moisture sensitivity level 3, which is a 168-hour floor life once the dry pack opens.
Second-sourcing Type I flash
The 56-lead and 48-lead Type I footprints have real cross-vendor compatibility, which is unusual and worth exploiting. Macronix’s application note AN0240 states that the 56-TSOP and 64-LFBGA packages of its MX29GL-G are pin compatible with Cypress’s S29GL-S.
Its published cross-reference guide, dated April 2020, names direct replacements:
| Original part | Package options | Recommended replacement |
| S29GL01GT | 56-TSOP, 64-FBGA | MX68GL1G0G |
| AM29SL800D | 48-TSOP, 48-LFBGA, 48-TFBGA | MX29SL800C |
| S29AS008J | 48-TSOP, 48-LFBGA, KGD | MX29SL800C |
| S29AS016J | 48-TSOP, 48-LFBGA, 48-TFBGA, KGD | Contact Macronix |
Availability is thinning at the distribution end even where the silicon is current. RS no longer stocks the Macronix MX29GL256EHT2I-90Q in 56-pin TSOP. Check two authorized sources before you assume a Type I part is a safe long-term choice.
Five mistakes specific to Type I
- Reading the body as the footprint. The 48-lead body is 18.4 mm long; the lead span is 20.0 mm. Your land pattern needs the second number.
- Leaving no escape room. Twenty-four nets per end need either 12 mm of clear board or a via per net. Decide before placement, not after.
- Confusing it with Type II. A 54-lead SDRAM and a 48-lead flash are both TSOP and share no dimension.
- Baking populated boards without checking the flash limit. 150 °C for prolonged periods puts stored data at risk, not just the package.
- Assuming the 40-lead size from a summary table. It is registered in MO-142, but confirm the body against a drawing.
TSOP Type I FAQ
What is TSOP Type I?
A thin small outline package with gull-wing leads on the two shorter edges of the body. JEDEC registers it as MO-142 at 24, 32, 40, 48 and 56 leads, at 0.50 mm pitch, with a 1.20 mm maximum seated height. A separate registration, MO-183, covers a 28-lead Type I at 0.55 mm pitch.
What is the difference between TSOP Type I and Type II?
Lead placement, and what follows from it. Type I has leads on the short edges and adds pin count by widening the body at constant 0.50 mm pitch. Type II has leads on the long edges and adds pin count by shrinking the pitch on a fixed body. They share no footprint at any lead count.
Is TSOP-48 Type I or Type II?
Type I. The 48-lead TSOP used for parallel NOR and NAND flash has 24 leads on each 12 mm short edge, a 20.0 mm lead span and 0.50 mm pitch. Distributors often list it as “48-TSOP I”. A 48-lead Type II exists in some catalogs, so confirm the drawing if the listing is ambiguous.
What is the pitch of a TSOP Type I?
0.50 mm across the mainstream sizes from 32 to 56 leads. The 28-lead variant registered under MO-183 uses 0.55 mm. Some family overviews also list 0.60 mm. Pitch alone does not identify the size, because every mainstream Type I shares 0.50 mm.
How many pins does a TSOP Type I have?
JEDEC MO-142 registers 24, 32, 40, 48 and 56. MO-183 adds a 28-lead variant and MO-259 a very very thin 48-lead variant. Pages claiming the family stops at 48 are wrong; 56-lead Type I parallel NOR flash is a standard product.
When Type I is the right choice
Choose Type I when the device you need only ships in it, which covers most parallel NOR and NAND flash, and when you can give the part 12 mm of routing room at each end or an inner layer to escape onto. The cross-vendor footprint compatibility on 48 and 56 leads is a genuine second-sourcing advantage that no BGA flash offers.
Choose Type II or a BGA when the board is wide and short rather than long, or when signal integrity rules the decision.
Before you place the footprint, do three things: take the lead span off the drawing rather than a body table, decide the escape strategy from the pad-gap arithmetic above, and orient the package so the data bus faces your controller. The first prevents a respin, the second prevents a layer count surprise, and the third saves a routing layer for free.
[IMAGE 3: comparison of Type I and Type II lead placement on the same board outline | alt: “TSOP Type I short-side leads compared with Type II long-side leads”]
Internal links to add
- [INTERNAL LINK: TSOP package → the full TSOP family, registrations and land patterns]
- [INTERNAL LINK: TSOP Type II → long-side lead layout and the 400-mil family]
- [INTERNAL LINK: SSOP-56 package → SSOP dimensions at high pin count]
- [INTERNAL LINK: IPC-7351 land pattern density levels → choosing Most, Nominal or Least]
- [INTERNAL LINK: BGA fanout → via-in-pad and escape strategies at 0.5 mm pitch]
