An SSOP-56 package is a 56-lead plastic gull-wing package on 0.635 mm pitch, with a 7.5 mm body, a 10.03 mm to 10.67 mm lead span and an 18.42 mm nominal body length. JEDEC registers the outline as MO-118. Below are the full dimension table, a worked land pattern, measured thermal numbers against TSSOP-56, and the lifecycle position you should confirm before you commit the footprint.

Key takeaways

• Pitch is 0.635 mm (0.025 in), not the 0.65 mm most SSOP articles quote. The 0.015 mm difference accumulates to 0.41 mm across 28 leads.
• JEDEC MO-118 covers the 0.300 in body, 0.025 in pitch SSOP family in 28, 48, 56 and 64 leads.
• Nominal-density IPC-7351B land pattern works out to 0.42 mm × 2.04 mm pads on a 9.33 mm row centreline.
• Measured junction-to-ambient resistance is roughly 80 K/W to 84 K/W, about 10 K/W to 15 K/W better than a TSSOP-56 carrying the same die.
• DigiKey files this package as “56-BSSOP”, so searching “SSOP-56” on that site returns almost nothing.
• Several flagship SSOP-56 parts are now obsolete or out of stock. Check status before you draw the footprint, not after.

[IMAGE 1: top and side view of a 56-lead SSOP with lead span, body width and pitch dimensioned | alt: “SSOP-56 package dimensions showing 0.635 mm pitch, 7.5 mm body and 10.3 mm lead span”]

What an SSOP-56 package is

An SSOP-56 package is a 56-lead shrink small outline package: a plastic body carrying 28 gull-wing leads per side on 0.635 mm pitch. Body width is 7.5 mm, body length 18.42 mm nominal, and seated height around 2.59 mm. JEDEC registers this outline under MO-118, the 0.300 in body width, 0.025 in pitch SSOP family.

That MO-118 entry matters more than it looks. It lists exactly four lead counts: 28, 48, 56 and 64. Anything else calling itself a 300-mil SSOP sits outside the registered outline. The neighbouring registrations describe genuinely different parts: MO-137 is the 0.150 in body SSOP, and MO-150 is the 5.3 mm body, 0.65 mm pitch SSOP that most tutorials describe when they say “SSOP”.

The lead form is a standard gull wing. Infineon notes that the gull-wing foot lands on a plane below the package body, so the standoff has to be accounted for when a design puts copper or a component under the part.

Vendor names for the same outline

Package naming is where SSOP-56 designs go wrong. The same outline appears under at least six labels, and two vendors use “SSOP 56” for physically different drawings.

Source	Designation	Notes
JEDEC	MO-118	Registered outline, 0.300 in body, 0.025 in pitch
JEDEC descriptive code	R-PDSO-G56	Rectangular, plastic, dual small outline, gull wing, 56
Infineon	PG-SSOP-56-800, drawing 51-85062	Body length 18.415 mm, body width 7.62 mm, pitch 0.635 mm
Cypress legacy	O56, order suffix PV	Same 51-85062 drawing
Texas Instruments	DL (R-PDSO-G56)	Also used for the 48-lead variant
Renesas	PV56 and PVG56	Two separate outlines, both labelled “SSOP 56”
DigiKey	56-BSSOP (0.295 in, 7.50 mm width)	The search term that actually returns parts
Mouser	SSOP-56	Parametric filter value

Two practical consequences. First, if a BOM line says only “SSOP-56”, ask for the drawing number before you trust a library footprint. Second, if a DigiKey search for SSOP-56 comes back empty, search 56-BSSOP instead. That single string is why sourcing engineers conclude the package is unavailable when it is not.

SSOP-56 dimensions

Values below are the 300-mil SSOP-56 outline as published by Holtek, cross-checked against Infineon’s parametric record (18.415 mm body length, 7.62 mm body width, 0.635 mm minimum terminal pitch) and against distributor mechanical data for the same lead frame family (2.59 mm seated height).

Symbol	Parameter	Min	Nom	Max	Unit
E	Overall lead span	10.03	—	10.67	mm
E1	Body width	7.39	7.49	7.59	mm
D	Body length	18.29	18.42	18.54	mm
A	Overall height	2.41	2.59	2.79	mm
A1	Standoff	0.20	0.30	0.41	mm
e	Lead pitch	—	0.635 BSC	—	mm
b	Lead width	0.20	—	0.34	mm
c	Lead thickness	0.13	—	0.25	mm
L	Foot length	0.51	—	1.02	mm
θ	Lead angle	0	—	8	degrees

Derived figures an engineer usually needs next. Maximum outline area is 10.67 mm × 18.54 mm, or 197.8 mm². Cypress’s drawing note for 51-85062 gives package mass as 0.162 g, which matters if you are computing shock and vibration loading on a long two-sided package. And the plastic body at 18.54 mm max is longer than the pad array at 17.57 mm, so the body sets the courtyard length rather than the copper.

SSOP-56 vs TSSOP-56, SOIC-56 and QFN-56

Attribute	SSOP-56	TSSOP-56	SOIC-56	QFN-56 (8 × 8 mm)
Pitch	0.635 mm	0.5 mm	1.27 mm	0.5 mm
Body	7.5 × 18.42 mm	6.1 × 14.0 mm	Not a practical outline	8 × 8 mm
Lead span	10.03–10.67 mm	7.9–8.3 mm	—	8 mm
Max height	2.79 mm	1.20 mm	—	~1.0 mm
Outline area	197.8 mm²	~117 mm²	—	64 mm²
Rth(j-a), low-K board	80–84 K/W	90–98 K/W	—	Package dependent
Hand rework	Practical	Difficult	—	Hot air and stencil

Two observations worth acting on.

SOIC-56 is not a real option. At 1.27 mm pitch, 28 leads per side needs roughly 35 mm of body length. No one builds it. If a search result offers you a SOIC-56, it is a mislabelled SSOP or TSSOP.

The bigger package runs cooler. Philips Semiconductors’ thermal handbook measured Rth(j-a) for SSOP56 at the 7.5 mm body at roughly 80 K/W to 84 K/W across die sizes to 15 mm², against 90 K/W to 98 K/W for TSSOP56 at 6.1 mm body. Values are still-air, low-K test board, accurate to about ±15%, so treat them as a comparison rather than an absolute. For a 0.5 W die that difference is 5 °C to 9 °C of junction temperature, free, in exchange for board area.

The same handbook contains a useful counter-example: VSO56 on an 11 mm body measures 96 K/W to 108 K/W, worse than the smaller SSOP-56, because it uses an FeNi lead frame instead of copper alloy. Lead frame alloy beats body size. Do not assume a physically larger package dissipates better.

SSOP-56 pinout

There is no standard SSOP-56 pin map. Unlike 56-lead TSOP flash, where a de-facto memory pinout exists, SSOP-56 is a general-purpose outline used by clock generators, bus transceivers, USB controllers and FIFOs, each with its own assignment.

What is standard is the numbering. Pin 1 sits at the lower left in the top view marked by the pin-1 identifier, which on this family is usually a moulded dimple or a chamfered corner. Pins 1 to 28 run down one side; pin 29 sits opposite pin 28, and 29 to 56 run back up the other side. Pin 1 and pin 56 are therefore diagonal neighbours across the short end of the package.

Two real examples show how differently the same 56 pins get used:

• Cypress CY28158, a clock generator: pin 1 is GND_REF, pin 5 and pin 6 are the crystal pins X1 and X2, and pin 56 is VDD_IOAPIC. Supplies are scattered deliberately so each output bank has local return.
• Infineon CY7C68013A (EZ-USB FX2LP), a USB 2.0 peripheral controller: the same outline carries 24 GPIO plus USB, I²C and USART interfaces at 3.0 V to 3.6 V.

Design consequence: on an 18.4 mm package with 28 pins per side, the supply and ground pins are rarely adjacent. Plan for decoupling at each supply pin individually. Cypress’s own test circuit for the CY28158 specifies 0.1 µF on every supply pin, placed as close to the pin as physically possible.

[IMAGE 2: SSOP-56 top view with pin 1 identifier and numbering direction annotated | alt: “SSOP-56 pinout numbering with pin 1 identifier, pins 1 to 28 and 29 to 56”]

SSOP-56 footprint: a worked IPC-7351B land pattern

Component packages fall under IPC-7353 within IPC-7351B, the gullwing-leads-on-two-sides family. Using Nominal density (Level B) fillet goals of Jt = 0.35 mm, Jh = 0.35 mm and Js = 0.03 mm, and assuming 0.05 mm fabrication allowance and 0.05 mm placement accuracy:

Inputs. Lead span L = 10.03 to 10.67 mm, so Ltol = 0.64 mm. Inner lead separation S runs from 10.03 − 2(1.02) = 7.99 mm to 10.67 − 2(0.51) = 9.65 mm, so Stol = 1.66 mm. Lead width W = 0.20 to 0.34 mm, Wtol = 0.14 mm.

Outer pad extent

  Z = Lmin + 2Jt + √(Ltol² + F² + P²)

    = 10.03 + 0.70 + 0.644  =  11.37 mm

Inner pad gap

  G = Smax − 2Jh − √(Stol² + F² + P²)

    =  9.65 − 0.70 − 1.662  =   7.29 mm

Pad width

  X = Wmin + 2Js + √(Wtol² + F² + P²)

    =  0.20 + 0.06 + 0.157  =   0.42 mm

Land pattern parameter	Value
Pad size	0.42 mm × 2.04 mm
Row centreline spacing	9.33 mm
Outer pad extent (Z)	11.37 mm
Inner gap (G)	7.29 mm
Pad pitch	0.635 mm
Pad-to-pad clearance	0.215 mm
Pad array length	17.57 mm
Courtyard length driver	Body, 18.54 mm max

The 0.215 mm clearance is comfortable for a Class 2 fabricator but leaves nothing for a solder-mask web at 0.10 mm minimum dam width. Specify mask-defined relief or gang relief across each row rather than individual mask apertures.

The dominant tolerance here is the foot length, at 0.51 mm to 1.02 mm. That single 0.51 mm spread contributes 1.66 mm to Stol and pushes the inner gap out by more than 1.6 mm. If your specific part’s datasheet quotes a tighter L, rerun the heel term. You will recover pad length.

Reflow, stencil and handling

Infineon’s parametric record for the SSOP-56 EZ-USB parts specifies a peak reflow temperature of 260 °C, consistent with J-STD-020 for this body thickness. Cypress rated the O56 package at 1 W maximum package power dissipation and a maximum soldering temperature of 260 °C for 10 seconds. Moisture sensitivity varies by part rather than by package: TI’s SN74ACT7804-20DL in this outline is classified MSL 1, while other devices in the same outline ship at MSL 3. Read the label on the dry pack, not the package family page.

Stencil: at 0.42 mm pad width and 0.635 mm pitch, a 0.12 mm foil with a 1:1 aperture gives an area ratio above 0.66 and releases reliably. Chamfer the aperture corners rather than reducing width; narrowing the aperture on this pitch invites open joints at the package ends where coplanarity is worst.

Standoff runs 0.20 mm to 0.41 mm. That is enough clearance for solder mask and via tenting under the body, and not enough for a 0201 or a test pad. Keep the area under the body free of anything taller than mask.

Packing quantities from Infineon for PG-SSOP-56-800: tape and reel at 1,000 pieces, or tubes at 520 pieces per box in 20 tubes, which is 26 parts per tube. That tube quantity is the one to check against your line’s minimum, because 26-piece tubes make small builds awkward.

Lifecycle and sourcing

This is the section the manufacturer package pages will not give you.

SSOP-56 is a legacy outline. It was current when Intel was shipping 16-Mbit FlashFile memory in it, and most new silicon at this pin count now launches in QFN or BGA. The consequences are visible in distributor data right now.

DigiKey lists CY7C68013A-56PVXCT, the tape-and-reel EZ-USB FX2LP in this package, with part status Obsolete and the note that the product is no longer manufactured. Infineon shows the industrial-grade CY7C68013A-56PVXI as out of stock with a replacement pointer. The same silicon remains available in 56-pin QFN and 56-ball BFVGA.

That gives you three honest paths:

1. Existing board, existing part. Buy through authorised channels and verify date codes. Broker stock on obsolete USB controllers is a known counterfeit target.
2. Existing board, new build. Check whether the QFN version is pin-compatible in function. It will not be footprint-compatible, so budget a board spin.
3. New design. Choose SSOP-56 only for a specific reason: field rework, thermal headroom, or a socket. Otherwise start at QFN or TSSOP.

For prototyping, SSOP-56 to DIP-56 adapters exist at the exact 0.635 mm pitch, 7.5 mm body geometry, along with matching stencils, which makes this one of the easier fine-pitch packages to bring up on the bench.

Five mistakes that send SSOP-56 boards back

• Using a 0.65 mm library part. Over 27 lead spacings the error reaches 0.41 mm, more than a full pad width. End leads land off copper.
• Trusting the name. Renesas publishes two different outlines both called SSOP 56. Always match the drawing number.
• Copying a TSSOP-56 land pattern. Different pitch, different span, and the article ranking above you for this query is a TSSOP drawing.
• Under-decoupling. Supply pins are spread across 18.4 mm of package. One bulk capacitor per rail is not enough.
• Committing the footprint before checking part status. On this package that check now fails often enough to matter.

SSOP-56 FAQ

What is the pitch of an SSOP-56 package?

0.635 mm, which is exactly 0.025 inches. This is an imperial-origin pitch, and it is not the same as the 0.65 mm pitch used by the 5.3 mm body SSOP family registered under JEDEC MO-150. Libraries that round 0.635 to 0.65 will misplace the end leads of a 56-pin part.

Is SSOP-56 the same as TSSOP-56?

No. SSOP-56 is 0.635 mm pitch on a 7.5 mm body, 2.79 mm maximum height. TSSOP-56 is 0.5 mm pitch on a 6.1 mm body, 1.20 mm maximum height, registered separately. The footprints are not interchangeable. TSSOP-56 saves roughly 40% of the outline area and costs about 10 K/W in thermal resistance.

What are SSOP-56 dimensions in millimetres?

Body 7.49 mm × 18.42 mm nominal, lead span 10.03 mm to 10.67 mm, overall height 2.41 mm to 2.79 mm, standoff 0.20 mm to 0.41 mm, lead pitch 0.635 mm, lead width 0.20 mm to 0.34 mm. Maximum outline area is 197.8 mm² and package mass is about 0.162 g.

Can you hand solder an SSOP-56?

Yes. At 0.635 mm pitch with 0.42 mm pads and 0.215 mm clearance, drag soldering with flux and braid is routine for anyone who has done SOIC work. It is markedly easier than the 0.5 mm TSSOP-56, and unlike QFN-56 the joints are visible for inspection.

Why can’t I find SSOP-56 parts on DigiKey?

DigiKey classifies this outline as “56-BSSOP (0.295 in, 7.50 mm width)” rather than SSOP-56, so a keyword search on SSOP-56 returns almost nothing. Search 56-BSSOP, or filter by supplier device package “56-SSOP”. Mouser uses SSOP-56 directly.

Choosing SSOP-56 today

Specify SSOP-56 when you need the thermal margin, when the board must be field-serviceable, or when you are maintaining an existing design and a footprint change is more expensive than the package penalty. In those cases the numbers in this article are sufficient to draw the land pattern and release the board.

Avoid it on any new design where board area matters and the silicon you want also exists in QFN or TSSOP. The outline is legacy, the part availability is thinning, and you will be re-spinning within a product generation.

Whichever way you go, do the sequence in this order: confirm the drawing number on the datasheet, confirm the part is still active at an authorised distributor, then draw the footprint. Reversing the last two steps is what turns a package decision into a board spin.

[IMAGE 3: IPC-7351B nominal-density land pattern for SSOP-56 with pad dimensions and row spacing called out | alt: “SSOP-56 footprint land pattern with 0.42 mm by 2.04 mm pads on 9.33 mm row spacing”]

Internal links to add

• [INTERNAL LINK: SOIC-20 package → SOIC-20 dimensions and footprint guide]
• [INTERNAL LINK: SOIC-16W package → wide-body SOIC land pattern reference]
• [INTERNAL LINK: SOIC-18 package → SOIC family pitch and body comparison]
• [INTERNAL LINK: IPC-7351 land pattern density levels → how to choose Most, Nominal or Least]
• [INTERNAL LINK: package thermal resistance → reading Rth(j-a) numbers correctly]