A SOIC-28 package measures 17.9 mm long and 7.5 mm across the molded body, stands 2.65 mm tall at most, and carries 28 gull-wing leads on 1.27 mm pitch. Almost every part sold as SOIC-28 is the wide-body 300 mil variant registered under JEDEC MS-013AE. Below are the drawing limits, the pinout convention, a land pattern you can build a footprint from, and the numbers that decide SOIC-28 against SSOP-28, TSSOP-28 and QFN-28.
Key takeaways
- SOIC-28 is wide-body by default: 7.391 mm to 7.595 mm molded width, 10.007 mm to 10.643 mm lead span.
- Pitch is 1.270 mm BSC. Build the footprint in metric, never by converting 0.050 in.
- JEDEC registration is MS-013AE. The matching IPC-7351B footprint name is SOIC127P1030X265-28N.
- Land pattern spacing converges on 9.28 mm to 9.40 mm center to center, with 0.60 mm to 0.76 mm pads.
- Junction-to-ambient thermal resistance is about 55 °C/W on a JEDEC four-layer board, roughly 31 % better than a 28-lead SSOP.
- The same die in TSSOP-28 or QFN-28 saves 66 % to 90 % of the board area, yet often costs more and ships slower.
[IMAGE 1: annotated SOIC-28 top view and side view with D, E, E1, A, A1, b, c and e callouts | alt: “SOIC-28 package dimensions diagram showing 17.9 mm body length, 7.5 mm body width and 1.27 mm lead pitch”]
SOIC-28 dimensions
These limits come from the Analog Devices S28 wide-body drawing, reference 05-08-1620, converted from its controlling inch dimensions.
| Dimension | Min (mm) | Nominal | Max (mm) | Note |
| Molded body length, D | 17.70 | 17.89 | 18.08 | Excludes mold flash |
| Molded body width, E1 | 7.391 | 7.493 | 7.595 | The 300 mil body |
| Lead span tip to tip, E | 10.007 | 10.325 | 10.643 | Drives pad spacing |
| Overall height, A | 2.362 | 2.502 | 2.642 | Seated |
| Standoff, A1 | 0.102 | 0.204 | 0.305 | Body to board |
| Lead pitch, e | — | 1.270 BSC | — | Basic dimension |
| Foot length, L | 0.940 | 1.042 | 1.143 | Contact length |
| Lead width, b | 0.356 | 0.419 | 0.482 | At the foot |
| Lead thickness, c | 0.229 | 0.280 | 0.330 | |
| Foot angle | 0° | — | 8° | |
| Mold flash allowance | — | — | 0.15 | Per side |
Texas Instruments quotes its DW variant at 17.78 mm to 18.03 mm long, 7.4 mm to 7.6 mm wide, with a 10.15 mm to 10.63 mm span under a 2.65 mm height cap. NXP rounds its SOIC 28W to 7.5 mm by 17.9 mm. Three vendors agree inside a tenth of a millimetre.
Watch the 0.15 mm mold flash allowance per side. It is excluded from the body dimensions, so a courtyard drawn tight to 7.595 mm can be violated by a legal part.
Which SOIC-28 do you actually have?
The name is ambiguous for historical reasons. JEDEC defines a 3.9 mm narrow body and a 7.5 mm wide body. JEITA, formerly EIAJ, defines a 5.3 mm Type II body that several vendors print as SOP. Texas Instruments and Fairchild reserve SOIC for the JEDEC widths and SOP for the 5.3 mm part.
At 28 leads the ambiguity mostly resolves itself, because the wide 7.5 mm body is what ships. Wide-body SOIC is registered under JEDEC MS-013 and IEC 075E03, and the variant letter tracks lead count: AA at 16 leads, AD at 24, AE at 28.
| Name on the page | Issued by | What it means |
| SOIC-28, SOIC28W, SOICW 28 | JEDEC MS-013AE | 7.50 mm body, 1.27 mm pitch |
| SO-28, SOL-28, S28 (WIDE) | Vendor legacy codes | Normally the same wide body |
| SOP-28 | JEITA / EIAJ ED-7300 | May be a 5.3 mm body. Verify the span |
| SOIC127P1030X265-28N | IPC-7351B | Footprint name, maps to MS-013AE |
| DW, SW, RW, SO, PE28, OI | TI, ADI, Microchip, Renesas | Vendor case outline codes |
Trust the case outline code on the datasheet, not the marketing name. A part listed as SOP-28 by a catalog distributor may carry a 5.3 mm body, and its leads will land on solder mask if you build a 300 mil footprint.
SOIC-28 pinout and pin 1 identification
Pin numbering follows the DIP convention. With the marking upright, pin 1 sits at the upper left, numbering runs down the left side to pin 14, then continues up the right side from pin 15 to pin 28. Pin 14 and pin 15 face each other across the short end.
Manufacturers mark pin 1 three ways: a molded dot, a half-moon notch at the pin 1 end, or a beveled edge along the pin 1 side. Some parts carry none of these and rely on text orientation alone.
SOIC-28 has no fixed function pinout; it is only a carrier. Microchip’s MCP23017-E/SO and TI’s TLC7135CDW both ship in it and share no pin assignments.
[IMAGE 2: SOIC-28 pin numbering diagram, pin 1 at upper left, 1 to 14 down the left side, 15 to 28 up the right side | alt: “SOIC-28 pinout numbering with pin 1 dot, notch and beveled edge markings”]
Building the SOIC-28 land pattern
Two routes exist, and they do not produce the same answer.
Route 1, the published layout. The Analog Devices S28 drawing specifies pads 0.045 ±0.005 in (1.143 mm) long and 0.030 ±0.005 in (0.762 mm) wide on 0.050 in pitch, with 0.325 ±0.005 in (8.255 mm) across the inner edges of the pattern. That places the pads near 9.40 mm center to center.
Route 2, construct it per IPC-7351B, which is the method NXP walks through in its SOIC application note. Two rules do most of the work: pad width runs about 60 % of pitch, and the pad extends 0.5 mm past the foot at both heel and toe.
| Step | Input | Result |
| Nominal lead span | (10.007 + 10.643) ÷ 2 | 10.325 mm |
| Nominal foot length | (0.940 + 1.143) ÷ 2 | 1.042 mm |
| Pad length, Y | 1.042 + 0.5 toe + 0.5 heel | 2.04 mm |
| Pad width, X | 0.60 × 1.27 mm pitch | 0.60 mm |
| Land center to center, C | 10.325 − 1.042 | 9.28 mm |
| Row length, pad 1 to pad 14 | 13 × 1.27 | 16.51 mm |
That 9.28 mm result sits alongside the 9.30 mm center-to-center spacing used in a published TI wide-body SOIC geometry and the roughly 9.40 mm implied by the Analog Devices layout. Anything inside that band solders.
Pad length is where the two routes separate. The legacy layout uses 1.14 mm pads; the IPC construction produces 2.04 mm. The longer pad buys a visible toe fillet for optical inspection and a stronger joint under thermal cycling. The shorter one saves room next to a connector. If the datasheet publishes a recommended layout, build that one and note the deviation.
Never let a pad run under the body. NXP flags it as an assembly problem, and the 0.15 mm mold flash allowance consumes what margin remains.
[IMAGE 3: SOIC-28 land pattern drawing with pad length, pad width and center-to-center callouts | alt: “SOIC-28 land pattern with 2.04 mm by 0.60 mm pads on 1.27 mm pitch and 9.28 mm center-to-center spacing”]
Stencil, moisture and rework limits
Every figure below is from NXP application note AN2409 rev. 3.0, October 2014.
| Parameter | Value | Why it matters |
| Stencil thickness at 1.27 mm pitch | 0.125 mm to 0.150 mm | Paste volume for a gull-wing fillet |
| Pad width rule of thumb | 60 % of pitch, so 0.60 mm | Bridging margin between leads |
| MSL rating, SOIC 28W | Level 3, 260 °C peak | 168 h floor life at 30 °C / 60 % RH |
| Qualified reflow passes | 3 | Covers double-sided plus one rework |
| Prebake before rework | 125 °C for 16 h to 24 h | Prevents package cracking |
| Max temperature at the pad during site dressing | 245 °C | Above it, PCB pads peel |
| Dry pack shelf life | 12 months below 40 °C / 90 % RH | From the seal date on the bag |
Moisture sensitivity is a device property, not a package property. NXP rates its SOIC 28W at Level 3, which allows 168 hours out of the bag. Microchip’s MCP23017-E/SO, in the same 7.50 mm package, is rated Level 2, which allows a year. Read the label on the moisture barrier bag rather than a generic package table.
SOIC-28 vs SSOP-28, TSSOP-28 and QFN-28
All four hold 28 leads. The rows below come from one vendor, the Texas Instruments analog packaging guide, so they share a measurement basis.
| Parameter | SOIC-28 (DW) | SSOP-28 (DB) | TSSOP-28 (PW) | WQFN-28 (RHR) |
| Body length (mm) | 17.78 to 18.03 | 9.9 to 10.5 | 9.6 to 9.8 | 5.40 to 5.60 |
| Body width (mm) | 7.4 to 7.6 | 5.0 to 5.6 | 4.3 to 4.5 | 3.40 to 3.60 |
| Lead pitch (mm) | 1.27 | 0.65 | 0.65 | 0.50 |
| Lead span (mm) | 10.15 to 10.63 | 7.4 to 8.2 | 6.2 to 6.6 | No leads |
| Max height (mm) | 2.65 | 2.00 | 1.20 | 0.80 |
| Lead width (mm) | 0.35 to 0.51 | 0.22 to 0.38 | 0.19 to 0.30 | 0.20 to 0.30 |
| Max envelope area (mm²) | ≈ 192 | ≈ 86 | ≈ 65 | ≈ 20 |
The area column drives most decisions. A SOIC-28 claims roughly three times the area of a TSSOP-28 and nearly ten times a 28-lead WQFN. In exchange, its 1.27 mm pitch gives the widest paste-printing window of the four.
[IMAGE 4: to-scale outlines of SOIC-28, SSOP-28, TSSOP-28 and QFN-28 overlaid | alt: “SOIC-28 vs SSOP-28 vs TSSOP-28 vs QFN-28 footprint area comparison at 28 leads”]
Thermal headroom, with the arithmetic
Analog Devices publishes package thermal resistances measured on a JEDEC four-layer board. At 28 leads the ranking defies package size.
| 28-lead package (ADI code) | θJC (°C/W) | θJA (°C/W) |
| SOIC wide, 300 mil (SW28) | 20 | 55 |
| SSOP, 5.3 mm (G28) | 25 | 80 |
| SSOP narrow, 150 mil (GN28) | 25 | 80 |
| TSSOP 4.4 mm, exposed pad (FE28) | 5 to 10 | 30 |
| PDIP, 300 mil (N28) | 30 | 59 |
Among leaded plastic packages with no exposed pad, SOIC-28 has the best junction-to-ambient path of the group at 55 °C/W. The lead frame is larger and the leads are wider, so more heat leaves through board copper. An exposed-pad TSSOP beats it at 30 °C/W, but that requires a thermal land, a via array and a stencil aperture strategy.
Worked example. Maximum dissipation is (TJ max − TA) ÷ θJA. With a 150 °C junction limit and an 85 °C ambient, a SOIC-28 gives 65 ÷ 55 = 1.18 W. The same die in a 5.3 mm SSOP-28 gives 65 ÷ 80 = 0.81 W. Shrinking the package costs about a third of the power budget.
Treat those numbers as a ranking, not a prediction. JEDEC standard JESD51-3 states plainly that values measured on its test boards cannot be used to predict performance in a particular system; they exist to compare packages. Rank options with them, then measure on your board.
Cost and availability: the result that surprises people
Microchip ships the MCP23017 I/O expander as the same die in SOIC-28, SSOP-28, SPDIP-28 and QFN-28. That makes it a clean control for package cost.
| Part number | Package | Unit price at 1 | Unit price at 100 | DigiKey stock | Factory lead time |
| MCP23017-E/SO | 28-SOIC, 7.50 mm | $1.62 | $1.247 | 7,853 | 4 weeks |
| MCP23017-E/ML | 28-QFN, 6 × 6 mm | $1.90 | $1.44 | 7,852 | 7 weeks |
The larger package is the cheaper one and the faster one, by 15 % and three weeks. Package area is not a proxy for unit cost at moderate lead counts.
Package choice stops mattering financially on low-runner parts. TI’s TLC7135CDW, also a SOIC-28, lists at $33.47 for one unit with seven in stock and a 12-week factory lead time. Die cost and demand dominate; the plastic is noise.
Five mistakes that send SOIC-28 boards back for rework
- Building the footprint in inches. NXP is explicit that pitch must be designed in metric using the exact 1.27 mm figure. Converted 0.050 in values accumulate error across 13 spans.
- Reusing a narrow-body pattern. A 3.9 mm SOIC land pattern under a 7.50 mm body leaves every foot sitting on solder mask.
- Treating SOP-28 as interchangeable. The EIAJ 5.3 mm body carries a different span and a different footprint.
- Extending pads under the body. Flux cannot escape, and automated optical inspection cannot see the joint it needs to grade.
- Ignoring floor life. An MSL 3 part has 168 hours out of the bag before it needs a bake, and it will see 260 °C at reflow.
SOIC-28 package FAQ
Is SOIC-28 the same as SO-28?
In practice, yes. SO-28, SOL-28 and S28 are vendor legacy names for the same 28-lead wide-body outline registered as JEDEC MS-013AE. The exception is SOP-28, which under the JEITA and EIAJ standards may carry a 5.3 mm body instead of 7.50 mm. Check the lead span on the drawing before reusing a footprint.
How wide is a SOIC-28 package?
The molded body runs 7.391 mm to 7.595 mm wide, which is the 300 mil wide-body dimension. Measured lead tip to lead tip, the span is 10.007 mm to 10.643 mm, and that span is the number your land pattern has to match. Overall length is 17.70 mm to 18.08 mm.
What is the pin pitch of a SOIC-28?
1.270 mm, listed as a basic dimension, equal to 0.050 in. It is the coarsest pitch in common surface-mount small-outline packages, roughly double the 0.65 mm used by SSOP-28 and TSSOP-28. That margin is why SOIC-28 tolerates a wider paste-printing and placement window.
Can you hand-solder a SOIC-28?
Yes. At 1.27 mm pitch, drag-soldering with flux and wick is routine. The practical limits are the 28 joints themselves and the risk of overheating a moisture-sensitive part. If the reel has been open past its floor life, bake before reworking, and keep the iron off the plastic body.
What is the difference between SOIC-28 and SSOP-28?
Pitch and area. SOIC-28 uses 1.27 mm pitch in a 7.50 mm body; SSOP-28 uses 0.65 mm pitch in a 5.0 mm to 5.6 mm body, cutting the envelope from roughly 192 mm² to 86 mm². SOIC-28 gives back better heat flow, 55 °C/W against 80 °C/W on a four-layer board.
What JEDEC standard covers the SOIC-28 package?
JEDEC MS-013, with variant AE for 28 leads. IEC 075E03 covers the same wide-body family. The IPC-7351B footprint name that maps to MS-013AE is SOIC127P1030X265-28N, which decodes as 1.27 mm pitch, 10.30 mm nominal lead span, 2.65 mm height, 28 pins, no thermal pad.
Which package to specify
Specify SOIC-28 when board area is not the binding constraint. You get the widest assembly process window of the four options, the best junction-to-ambient path available without an exposed pad, and, at moderate volume, the lowest unit cost and shortest lead time.
Move to TSSOP-28 or SSOP-28 when the roughly 192 mm² envelope will not fit, and accept the thermal penalty and the finer stencil. Move to QFN-28 only if X-ray or equivalent inspection is already in your process, since the joints are hidden.
Before releasing the footprint, do three things. Pull the case outline for your exact part number rather than a family drawing. Compare the vendor’s recommended layout against an IPC-7351B construction and record which one you built. Confirm the moisture sensitivity level from the bag label, not from a package table.
Internal links to place:
- [INTERNAL LINK: SSOP vs TSSOP package selection → fine-pitch small-outline package comparison]
- [INTERNAL LINK: IPC-7351B land pattern basics → footprint construction and density levels]
- [INTERNAL LINK: moisture sensitivity levels explained → MSL ratings, floor life and baking]
