The TO-243 package is what JEDEC calls the package the rest of the industry calls SOT-89, and JEITA calls SC-62. It is a 4.5 mm × 2.5 mm plastic surface-mount outline with three gull-wing leads on 1.5 mm pitch and a large exposed tab underneath. What it dissipates depends almost entirely on the copper you give it, and the headline current on some SOT-89 datasheets is unreachable.
Key takeaways
- One package, three codes: SOT-89 industry, TO-243AA JEDEC, SC-62 JEITA. NXP’s package sheet lists all three.
- The JEDEC registration is TO-243, Variation AA, Issue C, July 1986 — nearly forty years unrevised.
- Analog Devices and Microchip both declare conformance “with exception” and flag different dimensions.
- NXP publishes separate reflow and wave land patterns. The wave pattern’s largest dimension is 7.6 mm against 4.85 mm for reflow.
- Copper moves junction-to-ambient from about 250 °C/W to roughly 91 °C/W on a 1 in² FR4 board.
What the TO-243 package is
TO-243 is a three-lead plastic surface-mount transistor outline with an exposed die pad for heat transfer. NXP’s package information sheet gives the industry code SOT89, the JEDEC package outline code TO-243, the JEITA code SC-62 and mounting method S for surface mount. Body is 4.4 to 4.6 mm long by 2.4 to 2.6 mm wide.
The naming fragments in catalogs rather than in standards. JEDEC’s JESD30 descriptive designation table maps SOT-89 to TO-243AA. Analog Devices calls its drawing RK-3. Microchip uses MB for the three-lead version and MT for the five-lead. DigiKey splits the catalog into SOT-89-3 and SOT-89-5/6.
[IMAGE 1: Top, side and bottom views of a SOT-89 with lead pitch, body size and the exposed tab dimensioned | alt: “TO-243 package dimensions showing three gull-wing leads on 1.5 mm pitch and the exposed thermal tab”]
TO-243 package dimensions across three vendor drawings
| Dimension | NXP SOT89, 8 Feb 2016 | ADI RK-3, PKG-003480 | Microchip N8 |
| Package length | 4.4–4.6 mm | 4.40–4.60 mm | 4.40–4.60 mm |
| Package width | 2.4–2.6 mm | 2.30–2.60 mm | 2.29–2.60 mm |
| Seated height | 1.4–1.6 mm | 1.40–1.60 mm | 1.40–1.60 mm |
| Lead pitch | 1.5 mm nominal | 1.50 mm BSC | 1.50 mm BSC |
| Outer-lead span | 3.0 mm | 3.00 mm BSC | 3.00 mm BSC |
| Overall span including leads | 3.75–4.25 mm | 3.94–4.25 mm | 3.94–4.25 mm |
| Foot length | 0.8–1.2 mm | 0.75–1.20 mm | 0.73–1.20 mm |
| Coplanarity | — | 0.076 mm max | — |
| JEDEC conformance | Cites TO-243 | “Compliant to JEDEC standards TO-243-AA with exception to dimensions indicated by an asterisk” — four flagged | “This dimension differs from the JEDEC drawing” — two flagged |
Pitch and length agree everywhere, so the footprint transfers. Three other things do not.
Two vendors publicly deviate from the registration. Analog Devices asterisks four dimensions on RK-3; Microchip daggers two on N8, including a 2.00 mm minimum where the JEDEC drawing differs. Neither states what the JEDEC value is. If a mechanical fit matters, you need the vendor drawing, not the registration.
The width band is not common. NXP stops at 2.4 mm minimum while ADI goes to 2.30 and Microchip to 2.29. A pick-and-place vision model tuned to one may reject the other.
NXP allows a narrower overall span, 3.75 mm minimum against 3.94 mm from the other two. That is 0.19 mm of lead reach you may not get.
The land pattern: reflow and wave are not the same footprint
SOT-89 is one of the few surface-mount power packages routinely wave-soldered, and NXP publishes a separate footprint for each process.
The reflow pattern is compact: its largest published dimension is 4.85 mm, with three 0.7 mm lands and a 1.7 mm tab land. The wave pattern is materially bigger — 7.6 mm at its largest, with 1.8 mm and 1.5 mm land pairs and wider spacing, and NXP marks a preferred transport direction on the drawing.
Copying the reflow pattern into a wave-soldered board is a shadowing problem, not a fit problem. Use the process-specific figure, and honor the transport direction.
[IMAGE 2: NXP reflow and wave land patterns for SOT-89 side by side at the same scale | alt: “TO-243 package reflow and wave soldering land patterns compared at the same scale”]
What a SOT-89 actually dissipates
| Device and source | Quoted rating | Stated condition |
| IXYS CPC3703, 250 V depletion FET | 1.1 W total package dissipation | Mounted on 1 in × 1 in × 0.062 in FR4; TJ max 125 °C |
| D882H, commodity SOT-89-3L BJT | 500 mW; RθJA 250 °C/W | TJ max 150 °C |
| TL431U shunt reference in SOT-89 | RθJA 250 °C/W | TJ max 150 °C |
The two RθJA figures are self-consistent: at 250 °C/W with TJ 150 °C and TA 25 °C, the package supports (150 − 25) / 250 = 0.5 W, which is the 500 mW quoted.
The IXYS number implies something very different. A 1.1 W rating at TJ 125 °C and TA 25 °C works back to roughly 91 °C/W — an implied figure from the stated rating, not a published RθJA. The difference between the two is one square inch of copper.
Design to the copper, not to the package. A SOT-89 on minimal land is a 500 mW part. The same outline on a proper pour is a 1 W part. Nothing about the plastic changed.
Worked example: why a 1 A SOT-89 regulator is not a 1 A regulator
DigiKey lists an AMS1117-3.3 in SOT-89 rated 1 A. Take it at 5 V in, 3.3 V out, 1 A load:
Dissipation (5 − 3.3) × 1 = 1.7 W
At 250 °C/W rise = 425 °C not physical
At 91 °C/W rise = 155 °C still past a 125 °C junction limit
Needed for TJ ≤ 125 °C at TA = 40 °C: RθJA ≤ (125 − 40) / 1.7 = 50 °C/W
No SOT-89 board reaches 50 °C/W. Turned around, at 91 °C/W and TA = 40 °C the package supports (125 − 40) / 91 = 0.93 W. Across a 1.7 V drop that is 550 mA, not 1 A.
The 1 A figure is a silicon rating. The package rating is whatever your copper delivers, and it is roughly half that here.
[IMAGE 3: Thermal path from junction through the tab into the PCB copper pour, annotated with the worked example values | alt: “TO-243 package thermal path from junction through the exposed tab into PCB copper”]
Sourcing: what SOT-89 costs and what the cheap ones leave out
DigiKey listings, checked August 2026:
| Part | Function | Supplier package | Unit price | Note |
| UMW HT7533-1 | 3.3 V, 100 mA LDO | SOT-89-3 | $0.25 | |
| UMW HT7550-1 | 5 V, 100 mA LDO | SOT-89-3 | $0.25 | |
| GOODWORK HT7533-1 | 3.3 V, 100 mA LDO | SOT-89 | $0.04228 | Same function, roughly six times cheaper |
| TI TLV709A33PKR | 3.3 V, 150 mA LDO | SOT-89-3 | — | Branded alternative, full characterization |
| Nisshinbo RP170H301B-T1-FE | 3 V, 300 mA LDO | SOT-89-5 | $0.21307 at 1,000 | Not stocked; 12-week lead time; 1,000-piece minimum |
Two things fall out. The six-to-one price spread for the same nominal function buys you characterization and traceability, not silicon. And SOT-89-5 is a different supply picture entirely: the five-lead parts on DigiKey are frequently non-stocked with quarter-year lead times and four-figure minimums, which is a schedule risk a three-lead part does not carry.
Five mistakes that reach the field
- Sizing the copper after the schematic. RθJA moves by a factor of about 2.7 between minimal land and a 1 in² pour. That is a layout decision, not a component choice.
- Reusing the reflow land pattern on a wave-soldered board. NXP publishes two footprints for a reason, and the wave one is over 50% larger at its widest.
- Trusting a headline current rating. Check dissipation against your own board before believing 1 A in a 4.5 mm package.
- Assuming the vendor drawings match. Two of three declare exceptions to TO-243AA and flag different dimensions.
- Swapping SOT-89-3 for SOT-89-5 late. Different footprint, different pinout, and often a very different lead time.
Frequently asked questions
Is TO-243 the same as SOT-89?
Yes. NXP’s SOT89 package information sheet lists the JEDEC package outline code as TO-243 and the industry code as SOT89, and JEDEC’s JESD30 designation table maps SOT-89 to TO-243AA. Treat them as one package, then check the specific vendor drawing, because two major vendors declare exceptions to the registration.
What is the SC-62 package?
SC-62 is the JEITA outline code for the same package. NXP lists it alongside the JEDEC code TO-243 on the SOT89 sheet, and Japanese datasheets often use SC-62 where Western ones use SOT-89. It carries no separate dimensions; it is a third name for one outline.
How much power can a SOT-89 dissipate?
It depends on the board. Commodity SOT-89 datasheets quote 500 mW at 250 °C/W junction-to-ambient with a 150 °C junction limit. IXYS rates the CPC3703 at 1.1 W in the same outline when mounted on a 1 in × 1 in × 0.062 in FR4 board, which implies roughly 91 °C/W.
Is SOT-89 wave solderable?
Yes, and NXP publishes a dedicated wave-soldering footprint for it, separate from the reflow footprint. The wave pattern is substantially larger — 7.6 mm at its widest against 4.85 mm — and the drawing marks a preferred transport direction through the solder wave.
What is the difference between SOT-89-3 and SOT-89-5?
Lead count and, in practice, availability. Microchip designates them MB and MT respectively. DigiKey catalogs the five-lead version under SOT-89-5/6, and the parts there are often non-stocked with 12-week lead times and 1,000-piece minimums, against same-day stock for common three-lead devices.
What to do next
Before you place the footprint: pull the vendor drawing tied to your order code, not a generic TO-243AA reference. Analog Devices and Microchip both except dimensions from the registration, and they except different ones.
Before you finish the copper: decide the pour area from a dissipation calculation, not from what fits. One square inch is the difference between a 500 mW part and a 1 W part.
If the board is wave-soldered: use NXP’s wave land pattern and its transport direction. The reflow pattern will shadow.
If a datasheet quotes an ampere-class current in this package: work the dissipation before you believe it. In the AMS1117 case above, the honest number is about 550 mA.
If you are considering SOT-89-5: check stock and lead time before the schematic freezes. A twelve-week non-stocked part is a program risk, not a purchasing detail.
