An SPGA package is a pin grid array whose pins sit on two interleaved square grids, each offset from the other by half a pitch in both directions. The base pitch stays 2.54 mm, but nearest neighbors end up 1.80 mm apart. That single change roughly doubles pin density and is why Intel’s Socket 5, Socket 7, and Socket 8 look denser than the 486-era sockets beside them.

Key takeaways

• Staggering does not change the 2.54 mm grid. It adds a second grid in the gaps, so nearest-neighbor spacing drops to 1.80 mm.
• JEDEC registers the layout as MO-128, “2.54 mm (.100 in) Ceramic Staggered Pins.” The string SPGA does not appear in the JEP95 index.
• The registered pin counts follow N = n² + (n − 1)², which is why the same socket is documented as both 19 × 19 and 37 × 37.
• The density is paid for in escape routing, not in board area: usable channel width falls from about 1.5 mm to about 0.8 mm.
• SPGA is read as Shrink Pin Grid Array in some package taxonomies. Confirm from the layout, not the acronym.

[IMAGE 1: underside of an SPGA package showing the two interleaved grids in different colors, with 2.54 mm pitch and 1.80 mm nearest-neighbor spacing marked | alt: “SPGA package staggered pin grid array showing 2.54 mm pitch and 1.80 mm nearest-neighbor spacing”]

What an SPGA package is

An SPGA package is a pin grid array in which the pins form two square lattices offset from each other by half the pin spacing in both axes. Within the package boundary the pins read as a diagonal lattice. Most SPGA parts leave a depopulated region at the center of the array.

The purpose is density. A matrix PGA on 2.54 mm centers gives one pin per 6.45 mm² of package underside. Interleaving a second grid halves that to 3.23 mm² per pin without changing the drill grid the board still works on.

The geometry: two interleaved grids

Take an outer grid of n × n positions. The interstitial grid that fits inside it is (n − 1) × (n − 1). Total pins:

N = n² + (n − 1)²

For n = 19 that gives 361 + 324 = 685 pins. Index the same package on the half-step grid instead, and you get (2n − 1) × (2n − 1), or 37 × 37 positions.

This resolves a contradiction that runs through the socket reference tables. Socket 5 and Socket 7 appear as 19 × 19 SPGA in some charts and 37 × 37 SPGA in others. Both are right. One counts the underlying 2.54 mm matrix, the other counts half-step positions on a 1.27 mm index grid. Neither number is the pin count, because the arrays are not fully populated: Socket 7 carries 321 pins, Socket 5 carries 320, and the 296-pin LIF variant of Socket 7 sits in a body measuring 1.95 in (49.5 mm) square.

Nearest-neighbor spacing follows from the offset. Diagonal neighbors sit at:

2.54 mm ÷ √2 = 1.796 mm

Orthogonal neighbors remain 2.54 mm apart, but an interstitial pin sits at the center of every cell, so no straight channel between them stays clear.

Where SPGA sits in the JEDEC index

The JEP95 index by device type, updated March 2026, lists the staggered layout under the grid array family as MO-128. The registered pin counts are not arbitrary, since every one satisfies the formula above.

Registered pins (MO-128)	Outer grid n	Half-step index (2n − 1)
145	9	17 × 17
221	11	21 × 21
313	13	25 × 25
421	15	29 × 29
545	17	33 × 33
685	19	37 × 37
841	21	41 × 41
1013	23	45 × 45
1301	26	51 × 51

The full registration also covers 181, 265, 365, 481, 613, and 761 pins, filling in the even values of n. Note what is missing: n = 22, 24, and 25 were never registered, so the series jumps from 841 to 1013 to 1301.

Compare that with the matrix PGA families in the same index. MO-066 (ceramic small outline), MO-067 (ceramic large outline, S-CPGA-P, rev B, June 1993), and MO-083 (plastic) all register perfect squares from 81 to 400 pins. The staggered family starts where the matrix family runs out.

[INTERNAL LINK: JEDEC package outline numbering -> JEP95 outline reference]

SPGA, IPGA, shrink PGA: three names, two meanings

The acronym is not safe on its own.

Term	Reading in PC hardware	Reading in package taxonomies
SPGA	Staggered Pin Grid Array	Shrink Pin Grid Array, a PGA with reduced pitch
IPGA	Rarely used	Interstitial Pin Grid Array, the staggered layout
CPGA	Ceramic PGA	Ceramic PGA
PPGA / FCPGA	Plastic PGA / flip-chip PGA	Same

Intel-era documentation and every socket chart use SPGA for staggered. At least one widely read package-type reference assigns the staggered layout to IPGA and reserves SPGA for shrunk pitch. JEDEC sidesteps both by writing “staggered pins” in plain words.

Practical rule: if the pin count matches n² + (n − 1)², the layout is staggered regardless of what the abbreviation claims.

What staggering costs in escape routing

Density on the package does not come free on the board. Assume a 0.5 mm finished hole, a 1.0 mm annular pad, and 0.2 mm trace and space rules, which are ordinary numbers for a through-hole PGA footprint.

Layout	Nearest neighbors	Clear channel between pads	0.2 mm traces per channel
Matrix PGA, 2.54 mm	2.54 mm	1.54 mm	3
SPGA, 2.54 mm base	1.80 mm	0.80 mm	1

The channel narrows because the interstitial pin blocks the straight path. Three traces per channel becomes one, while the pin count doubles. Layer count rises accordingly, which is why SPGA parts landed on motherboards with more layers than their matrix predecessors, and why the format did not migrate to cost-sensitive boards.

Mechanically, the cost is pin strength. Closer neighbors mean thinner pins are attractive and bent-pin recovery is harder, since a neighbor sits 1.80 mm away in the direction you want to lever toward.

[IMAGE 2: overlay of matrix and staggered footprints with routing channels shaded and trace counts annotated | alt: “Escape routing channel width for an SPGA package compared with a matrix pin grid array”]

Where the staggered lattice went next

The pins disappeared; the lattice did not. The same JEP95 index registers a thin profile interstitial fine-pitch BGA (MO-295) whose ball counts include 313, 421, 545, 685, and 1105.

The first four are exactly MO-128 numbers. The interstitial ball array is the staggered pin array with solder balls substituted and the pitch shrunk. When BGA and LGA displaced PGA for high pin counts, the geometry survived the change of terminal type.

Two other paths in the index are worth knowing. MO-145 registers a 1.27 mm ceramic surface-mount PGA family from 288 to 783 pins, which reached similar counts by halving the pitch rather than interleaving. And MO-247 and MO-257 apply staggered multi-row terminals to QFN, showing the same trick used at the package periphery.

Working on legacy SPGA hardware

Sockets are not interchangeable by pin count. Socket 8 pairs a matrix region with a staggered region in one rectangular body of 387 pins. A socket that accepts one region correctly will not accept the other.

Extraction damages pins. Levering a package out of a ZIF socket with the lever still closed bends pins toward their nearest neighbor, which on this layout is 1.80 mm away rather than 2.54 mm. Open the lever fully and lift straight.

Sourcing is a used-parts market. Ceramic SPGA processors and their sockets have been out of production for decades. Treat any purchase as unverified: check for reworked pins, relabeled tops, and mismatched date codes.

Pin 1 is keyed, not marked. Socket 7 adds a key pin at one corner that is electrically unconnected. Orientation comes from the missing or extra corner position, not from a dot.

SPGA package FAQ

What does SPGA stand for?

In PC hardware it stands for staggered pin grid array: a PGA whose pins sit on two square grids offset by half a pitch. Some package-type references instead read SPGA as shrink pin grid array, meaning reduced pitch. Confirm from the layout rather than the abbreviation.

What is the difference between PGA and SPGA?

A matrix PGA places pins on a single square grid, usually at 2.54 mm. An SPGA adds a second grid in the gaps, so nearest neighbors sit 1.80 mm apart and pin density roughly doubles. The board still drills on a 2.54 mm matrix, but the routing channels between pins narrow sharply.

Which CPU sockets used SPGA?

Intel’s Socket 5 (320 pins) and Socket 7 (321 pins) both used it, as did the Pentium Pro’s Socket 8, which combined a matrix region and a staggered region across 387 pins. Socket 7 also hosted AMD K5 and K6 and Cyrix 6×86 processors.

Why is SPGA described as both 19 × 19 and 37 × 37?

Because both describe the same package. The 19 × 19 figure counts positions on the underlying 2.54 mm matrix; 37 × 37 counts half-step positions on the 1.27 mm index grid, which is 2n − 1 for n = 19. Neither number is the populated pin count.

What is the pin pitch of an SPGA package?

The base grid is 2.54 mm (0.100 in), which is what JEDEC registers under MO-128. Nearest-neighbor spacing is smaller: diagonal neighbors sit at 2.54 mm divided by the square root of two, or 1.80 mm. Footprint drilling follows the 2.54 mm matrix.

Is SPGA still used today?

Not for new designs. High pin counts moved to BGA and LGA. The lattice itself survives in JEDEC’s interstitial fine-pitch BGA family, MO-295, whose ball counts of 313, 421, 545, and 685 match the MO-128 staggered pin counts exactly.

What to do next

If you are identifying a part, count the array rather than trusting the label. A pin count matching n² + (n − 1)² confirms a staggered layout; a perfect square confirms a matrix one.

If you are drawing a footprint for a staggered part, budget layers before board area. The pins fit on a 2.54 mm drill grid, but each channel carries one trace instead of three, so the escape needs roughly three times the layer resources of a matrix PGA with the same pin count.

If you are choosing a modern package that needs this density, go to the interstitial BGA family rather than reviving pins. It is the same lattice, registered under MO-295, at a pitch the assembly line already handles.

[IMAGE 3: JEDEC lattice progression from matrix PGA to staggered PGA to interstitial BGA with the shared pin-count series | alt: “SPGA package lattice compared with matrix PGA and interstitial BGA pin count series”]

Primary sources

• JEDEC Publication 95, Index by Device Type of Registered Microelectronic Outlines (MO), updated 03/26 — https://www.jedec.org/sites/default/files/MOIND_DT.pdf
• JEDEC Publication 95, master index of registered outlines — https://www.jedec.org/sites/default/files/Master.pdf
• Wikipedia, Pin grid array (SPGA lattice description) — https://en.wikipedia.org/wiki/Pin_grid_array
• Wikipedia, Socket 5 and Socket 7 (pin counts and body size, cited to Intel’s Pentium Processor Family Developer’s Manual) — https://en.wikipedia.org/wiki/Socket_7
• Wikipedia, Socket 8 (hybrid matrix and staggered layout) — https://en.wikipedia.org/wiki/Socket_8