The CERDIP package (also written CerDIP) is a hermetically sealed ceramic dual in-line package in which a pressed-ceramic lid is bonded to a pressed-ceramic base using lead-oxide solder glass, with the lead frame embedded in the glass seal. This glass-sealed construction distinguishes CerDIP from side-brazed ceramic DIP, which uses a solder or braze joint for the lid and leads. CerDIP delivers hermetic protection at lower cost than side-brazed packages, making it the historically dominant ceramic DIP variant for military, aerospace, and EPROM applications. This guide covers how CerDIP is built, how it compares to side-brazed and plastic alternatives, its known failure modes, and when it remains the right specification.
Key Takeaways
CerDIP’s defining feature is its glass-frit seal, formed at approximately 450–500 °C (per US Patent 4,025,716 and IEEE IRPS 1978). The lead frame sits inside the glass, and the seal is the mechanically weakest element of the package.
The glass seal is the primary failure mode: lead flexure during handling transmits stress into the glass, causing cracking. US Patent 4,761,518 documents that CERDIP has a larger seal area but smaller die cavity than a side-brazed package of equal size.
CerDIP body material is 92% alumina (Al₂O₃), pressed in a single firing for both base and lid. Lead frame material is Kovar or Alloy 42, typically with solder-dip or gold-plated finish.
JEDEC MS-015 covers CerDIP outlines. Pin counts range from 8 to 42 (per multiple sources) or up to 64 in extended configurations. Lead pitch is 2.54 mm (100 mil). Row spacings: 300, 400, 600, and 900 mil.
CerDIP costs roughly 2–5× less than equivalent side-brazed ceramic DIP but 5–20× more than PDIP. It is increasingly legacy-only; most semiconductor companies have moved new hermetic designs to side-brazed CDIP, CQFP, or ceramic LCC.
What Is a CERDIP Package?
A CERDIP (Ceramic Dual In-Line Package, glass-sealed variant) consists of two dry-pressed alumina ceramic sections—a base with a die cavity and a flat lid—joined by a continuous glass-frit seal ring. The IC die is bonded to the base cavity floor, wire-bonded to the lead frame, and then the lid is placed over the assembly. The entire stack is heated to 450–500 °C, melting the lead-oxide glass frit into a continuous hermetic barrier that encases the lead frame between the base and lid.
This construction earned the alternative name “G-DIP” (glass-sealed DIP) in the JEITA package code system. In Japan, CerDIP is formally coded as DIP-G. The hermetic seal, once cooled and solidified, prevents moisture and ionic contaminants from reaching the die surface, which is why CerDIP was the standard hermetic IC package from the late 1960s through the 1990s.
[IMAGE 1: Exploded cross-section of a CERDIP package showing ceramic base, die attach, wire bonds, lead frame embedded in glass frit, and ceramic lid | alt: “CERDIP package cross-section showing glass-frit seal and lead frame between ceramic base and lid”]
CERDIP vs Side-Brazed Ceramic DIP vs PDIP
Engineers often conflate CerDIP with all ceramic DIP packages, but the glass-sealed and side-brazed variants differ structurally in ways that affect die cavity size, seal reliability, and cost.
| Property | CERDIP (Glass-Sealed) | Side-Brazed Ceramic DIP | PDIP |
| Seal method | Lead-oxide glass frit (≈470 °C) | Solder or seam weld to metal lid | Non-hermetic epoxy mold |
| Body construction | Two pressed ceramic pieces | Single ceramic body + metal lid | Molded plastic |
| Lead attachment | Embedded in glass seal | Brazed to ceramic sidewalls | Molded into plastic |
| Die cavity size | Smaller (seal area reduces it) | Larger for same package footprint | N/A (die encapsulated) |
| Seal reliability | Glass is weakest element | Solder/braze stronger than glass | No hermetic seal |
| Hermeticity | Hermetic (≤10⁻⁸ cc He/s) | Hermetic (≤10⁻⁸ cc He/s) | Non-hermetic |
| Temperature range | −55 to +175 °C (mil) | −55 to +175 °C (mil) | −40 to +85 °C (comm.) |
| Ceramic material | 92% Al₂O₃ (pressed) | 96–99% Al₂O₃ (multilayer co-fired) | N/A |
| Lead finish | Solder-dip or Au-plated | Au-plated (Kovar) | Sn or Sn/Pb |
| Relative cost | 2–5× PDIP | 10–30× PDIP | 1× (baseline) |
| JEDEC standard | MS-015 | MO-036 (JEDEC) | MS-001 / MS-011 |
| Availability | Legacy; declining | Active for mil/aero | Widely available |
Sources: US Patent 4,761,518 (die cavity comparison), eesemi.com (sidebraze vs CerDIP), TI SNOA280 (hermetic package configurations), JEDEC JEP-95.
The key trade-off: CerDIP is cheaper than side-brazed because the glass-seal process is simpler (single firing step, no metallization of ceramic sidewalls). However, the glass seal is mechanically weaker. Side-brazed packages allow a larger die cavity in the same footprint because the seal occupies less area along the package perimeter.
Glass-Seal Failure Modes
Seal glass cracking is the dominant CERDIP failure mechanism, documented by eesemi.com’s failure mechanism reference. Fractures anywhere in the glass seal compromise hermeticity. Root causes include lead flexure during handling (the lead frame transmits bending stress directly into the glass), thermal cycling that exceeds the CTE mismatch tolerance between glass and ceramic, and mechanical shock during insertion into sockets.
Moisture in the sealed cavity was identified as a concern in the IEEE International Reliability Physics Symposium (IRPS) as early as 1978. The paper “A Reliable Dry Ceramic Dual In-Line Package (CERDIP)” documented that high moisture content in the sealed cavity had “simultaneously widely deployed [CerDIP] for packaging ICs and condemned [it] for many high reliability applications.” Modern manufacturing processes (lower-moisture-content glass frits, nitrogen-atmosphere sealing) have largely mitigated this, but incoming inspection should include internal moisture measurement per MIL-STD-883 Method 1018 for space and mil programs.
Die-attach voiding can occur because the glass-seal firing temperature (450–500 °C) subjects the die attach to a second thermal excursion. If the die-attach adhesive outgasses during this step, voids form under the die, degrading thermal conductivity. Proper process control uses a die-attach material rated for the seal temperature and a bake-out step before lid seal.
Where CERDIP Packages Remain in Use
CerDIP’s primary remaining application is legacy sustaining programs. Military avionics, radar systems, and ground-based defense electronics designed in the 1970s–1990s used CerDIP ICs extensively. These systems require form-fit-function replacement parts, and CERDIP remains the specified package.
Windowed CERDIP (WDIP) housed UV-erasable EPROMs throughout the 1980s and early 1990s. Devices like the Intel 2716 and 27C256 used a quartz window in the ceramic lid to allow 253.7 nm UV light to reach the floating-gate array. Flash memory has eliminated the need for windowed packages in new designs, but legacy avionics and industrial controllers still require them.
Manufacturers offering CERDIP assemblies include Spectrum Semiconductor Materials, Golden Altos, and Kyocera (through its NTK Technologies division). Aftermarket remanufacturers like Rochester Electronics supply legacy CERDIP ICs from original die.
[IMAGE 2: Photo of a windowed CERDIP EPROM and an opaque CERDIP side by side, with glass-seal line visible around the perimeter | alt: “Windowed and opaque CERDIP packages showing glass-frit seal line around ceramic body”]
Sourcing, Obsolescence, and Counterfeit Risk
Most semiconductor IDMs (TI, ADI, Microchip) list CerDIP packages as NRND or discontinued for new designs. New hermetic programs typically specify side-brazed ceramic DIP, ceramic QFP (CQFP), or ceramic LCC. CerDIP production continues at specialty ceramic package houses and contract assembly facilities (Golden Altos, Spectrum Semi) serving defense and aerospace sustaining demand.
Counterfeit risk is high for CerDIP ICs. The combination of high unit prices, long production histories, and standardized outlines makes remarking straightforward. Mitigation: purchase from OCM-authorized or DLA-listed sources. For broker purchases, require testing per SAE AS6171 and AS6081. X-ray fluorescence (XRF) verifies lead finish compliance; acetone-wipe tests catch ink-over-laser remarking. Decapsulation reveals die markings that confirm the actual manufacturer and date code.
Frequently Asked Questions
What is a CERDIP package?
A CERDIP (Ceramic Dual In-Line Package) is a hermetically sealed IC housing made from two pressed alumina ceramic pieces joined by a lead-oxide glass-frit seal. The lead frame is embedded within the glass between the base and lid. It provides hermetic protection for military, aerospace, and high-reliability ICs while costing less than side-brazed ceramic alternatives.
What is the difference between CERDIP and side-brazed DIP?
CerDIP uses a glass-frit seal with the lead frame embedded in the glass. Side-brazed DIP uses a single ceramic body with leads brazed to the sidewalls and a metal lid sealed by solder or seam welding. Side-brazed packages offer a larger die cavity and stronger seal but cost significantly more. Both are hermetic and meet MIL-PRF-38535 requirements.
Why was CERDIP used for EPROM chips?
UV-erasable EPROMs required a transparent window to expose the floating-gate array to 253.7 nm ultraviolet light. The CERDIP lid was modified to include a quartz or UV-transparent glass window sealed with the same glass-frit process. This “windowed CERDIP” (WDIP) was the standard EPROM housing until flash memory replaced UV-erasable devices in the mid-1990s.
Is CERDIP still manufactured?
CerDIP ceramic packages are still produced by specialty houses (Spectrum Semiconductor, Golden Altos, Kyocera/NTK Technologies) for defense and aerospace sustaining programs. However, most IC manufacturers no longer offer new designs in CerDIP. Legacy replacement ICs in CerDIP can be sourced from aftermarket suppliers like Rochester Electronics.
Specifying CERDIP — Decision Rules
Specify CerDIP when the program mandates hermetic packaging per MIL-PRF-38535 and the design requires form-fit-function compatibility with an existing CerDIP board layout. CerDIP is the lowest-cost hermetic ceramic DIP option, and its footprint (JEDEC MS-015) is interchangeable with side-brazed and PDIP.
For new designs requiring hermeticity, evaluate side-brazed CDIP (larger die cavity, stronger seal), ceramic flatpack (CQFP for higher pin counts), or ceramic LCC (surface-mount hermetic). CerDIP’s glass-seal weakness under lead flexure makes it less suitable than side-brazed for designs subjected to repeated socket insertion or heavy handling. Confirm the glass-seal integrity specification in MIL-STD-883 Method 1014 (seal test) and Method 1018 (internal moisture) for any CERDIP IC entering a hi-rel program.
