Every SOP package type is the same basic idea — a rectangular, surface-mount IC with gull-wing leads on two sides — pushed along one of three axes. SOP, SSOP, TSSOP, and MSOP were each designed to reduce size, increase density, and lower cost, usually in that order. SSOP shrinks the lead pitch. TSSOP shrinks the height. MSOP shrinks the whole footprint. Get those three axes straight and the rest of this family stops being an acronym soup and becomes a set of deliberate trade-offs you can design around.
Key takeaways
- SOP/SOIC uses 1.27 mm pitch; the “shrink” variants tighten it to 0.65 mm or 0.5 mm.
- SSOP = narrower pitch, TSSOP = ≤1.1 mm height, MSOP = ~3 mm × 3 mm footprint.
- “SOP” (EIAJ, 5.3 mm body) and “SOIC” (JEDEC, 3.9 or 7.5 mm body) are not automatically interchangeable — check the drawing, not the name.
- Smaller packages run hotter for the same die; a plain SOIC-8 can beat a VSSOP-8 by ~50% on θJA.
- Package identity lives in the JEDEC outline number (MS-012, MO-150, MO-153, MO-187), not the marketing label.
What an “SOP package” actually is (and the SOP-vs-SOIC trap)
An SOP (small outline package) is a family of gull-wing, surface-mount IC packages with leads on two opposing sides. The variants differ by one axis each: SSOP tightens lead pitch to about 0.65 mm, TSSOP cuts seated height to roughly 1.1 mm or less, and MSOP shrinks the body to about 3 mm × 3 mm. All descend from the through-hole DIP.
Here is the trap that burns sourcing engineers. “SOP” and “SOIC” get used interchangeably, but the underlying standards differ. Texas Instruments and Fairchild consistently call the JEDEC 3.9 mm and 7.5 mm width parts “SOIC” and the EIAJ Type II 5.3 mm width part “SOP.” The EIAJ Type II body is 5.3 mm wide and slightly thicker and longer than the JEDEC MS-012 outline, so “SOIC” alone is not specific enough to guarantee two parts are interchangeable. An “SOP-8” and a “SOIC-8” can carry different lead spans and land on different footprints. Treat the package name as a hint and the mechanical drawing as the contract.
[IMAGE 1: Line drawing of a gull-wing SOP lead cross-section showing pitch (e), lead span (E), and seated height (A) | alt: “SOP package types gull-wing lead cross-section labeled with pitch, lead span, and seated height”]
The four packages at a glance
All figures below are nominal for common low-pin-count parts at 25 °C; always confirm against the device datasheet and its referenced JEDEC outline.
| Package | Full name | JEDEC outline | Lead pitch | Body width | Typical seated height | Typical pins |
| SOP / SOIC | Small Outline (Integrated Circuit) | MS-012 (narrow), MS-013 (wide) | 1.27 mm | 3.9 mm / 7.5 mm | up to ~1.75 mm | 8–28 |
| SSOP | Shrink Small Outline Package | MO-150 (5.3 mm body) | 0.65 mm | ~5.3 mm | up to ~2.0 mm | 8–30 |
| TSSOP | Thin Shrink Small Outline Package | MO-153 | 0.65 mm (0.5 mm at high pin count) | 4.4 mm (also 6.1 mm) | ~1.1 mm | 8–64 |
| MSOP | Mini Small Outline Package | MO-187 | 0.65 mm (0.5 mm for 10/16-pin) | ~3.0 mm | ~0.85–1.1 mm | 8–16 |
Sources: JEDEC MS-012 defines the SOIC at 1.27 mm pitch and 3.9 mm (0.150 in) body width, with MS-013 the wider 7.5 mm variant. MO-150 is the plastic SSOP at 5.3 mm body width and MO-153 is the plastic thin SSOP/TSSOP. MSOP is registered under MO-187, with the 8- and 10-pin versions measuring 3 mm × 3 mm.
Three ways to shrink: pitch, height, footprint
SSOP — shrinking the pitch
SSOP keeps a moderate footprint but pulls the leads closer together. SOP normally uses 1.27 mm pitch; SSOP reduces it to roughly 0.65 mm, so more leads fit across the same body edge. The catch is that “SSOP” is overloaded: SSOP appears with pitches of 1.0, 0.8, 0.65, and 0.5 mm, so you must confirm the pitch from the datasheet every time. A close cousin, the QSOP, uses a 0.635 mm (25 mil) pitch — visually similar, mechanically not identical. SSOP suits mid-density logic, data converters, and interface ICs where you want density without going to the thinnest profile. In TI’s catalog the SSOP appears as the DB suffix; the tighter-pitch QSOP-class part as DBQ.
TSSOP — shrinking the height
TSSOP is the answer when vertical clearance, not board area, is the constraint. The distinguishing feature is thickness: package height drops to roughly 0.9–1.2 mm, about half that of a standard SOIC or SSOP, while lead pitch stays near 0.65 mm (0.5 mm variants exist for higher density). Body widths come in 3.0, 4.4, and 6.1 mm, and pin counts run from 8 to 80. That low stack height is why TSSOP dominates memory, portable, and card-form-factor designs. TI’s TSSOP is the PW suffix; the thermally enhanced version with an exposed pad is PWP (HTSSOP), used for parts that need good thermal conductivity such as half-bridges and switching regulators.
MSOP — shrinking the footprint
MSOP is the density play. It exists for one reason — board area — and is significantly smaller than SOIC and TSSOP, with pitches as tight as 0.5 mm. Body width is nominally 3 mm and thickness runs about 0.85 mm to 1.1 mm, with lead pitch typically 0.65 mm or 0.50 mm. The naming is a minefield across vendors: TI calls this form factor VSSOP (and equates VSSOP with MSOP), while Analog Devices historically used “micro SOIC,” Maxim used µMAX, and National Semiconductor used MiniSO. Same body, four names. MSOP fits sensor front-ends, low-power analog, and space-limited consumer boards — but it gives back thermal headroom, which the next section quantifies.
[IMAGE 2: Side-by-side top view of SOIC-8, SSOP-8, TSSOP-8, and MSOP-8 at true relative scale | alt: “Relative size comparison of SOIC, SSOP, TSSOP, and MSOP eight-pin packages”]
Thermal reality: your package sets your power budget
The specs most comparison pages skip are the ones that decide whether your part survives. Junction-to-ambient thermal resistance (θJA) rises as the package shrinks, because a smaller body has less metal and less board coupling to move heat out. This is measurable on a single die offered in multiple packages.
| Device (same die) | Package | Pins | θJA (°C/W) |
| OPA2388 | SOIC (D) | 8 | 116 |
| OPA2388 | VSSOP/MSOP (DGK) | 8 | 177 |
| OPA4192 | SOIC (D) | 14 | 86.4 |
| OPA4192 | TSSOP (PW) | 14 | 92.6 |
For the OPA2388, TI’s datasheet lists θJA at 116 °C/W in the SOIC and 177 °C/W in the VSSOP — the same silicon runs about 53% hotter per watt in the smaller package. For the 14-pin OPA4192, the SOIC comes in at 86.4 °C/W versus 92.6 °C/W for the TSSOP. Note that θJA is board-dependent, not a pure package constant, so treat these as design guidance and use the datasheet’s ψ parameters for your own copper.
Worked example. Take the OPA2388 VSSOP at 177 °C/W dissipating 150 mW. Rise above ambient ≈ 0.177 °C/mW × 150 mW ≈ 26.6 °C. At 85 °C ambient the junction sits near 112 °C. Move the same die to the SOIC at 116 °C/W and the rise drops to ≈ 17.4 °C — a ~9 °C junction saving for free, just from the package choice.
When you truly need power in a small outline, the fix is an exposed thermal pad. TI’s PowerPAD data makes the case bluntly: a PowerPAD version of the 20-pin SSOP handles 3.25 W, while the standard version handles only 0.75 W. The pad-bearing variants carry their own names — TI’s DGN is the HVSSOP, which is the MSOP-PowerPAD; “MSOP” is the industry name and “HVSSOP” is the TI name — and they require a soldered thermal land with vias to be worth anything.
Decoding the part number and the footprint
Two naming systems matter: the vendor’s package suffix and the IPC land-pattern name.
| TI suffix | Package family | Exposed pad? |
| D | SOIC | No |
| DB | SSOP | No |
| PW | TSSOP | No |
| PWP | HTSSOP | Yes |
| DGK | VSSOP (MSOP) | No |
| DGN | HVSSOP (MSOP-PowerPAD) | Yes |
On the PCB side, IPC-7351B names the footprint from geometry, not marketing. The convention builds the land-pattern name as the package family plus pitch, body length, lead span, and height — for SOP-class parts, “SOP + pin count + P pitch _ body length X lead span X height.” The trailing letter encodes the density level: M (most material, level A), N (nominal, level B), or L (least material, level C). A representative 14-lead, 0.65 mm-pitch TSSOP with a 6.4 mm span therefore resolves to a name in the form SOP65P640X110-14N. Match the library footprint to the datasheet dimensions, not to a part that merely shares the acronym.
Assembly imposes one more constraint. Under IPC/JEDEC J-STD-020, the peak reflow classification temperature depends on package thickness and volume, and your reflow peak must not exceed that classification temperature. Because every package here is thin and low-volume, they typically classify at the 260 °C Pb-free ceiling — but the moisture-sensitivity level (MSL) still dictates floor life and whether a pre-reflow bake is required. Honor the reel’s MSL label or you will grow internal delamination you cannot see.
How to choose: a decision path
Work the constraints in this order:
- Vertical clearance limited (under a shield, in a card slot)? Go TSSOP first; its ~1.1 mm height is the defining advantage.
- Board area is the hard limit and power is low (<~200 mW)? Go MSOP/VSSOP — the smallest footprint, accepting higher θJA.
- Dissipating real power in a small outline? Use an exposed-pad variant (HTSSOP/HVSSOP/PowerPAD) with a via-stitched thermal land, not a bare fine-pitch part.
- Prototyping, hand assembly, or rework expected? Prefer SOIC/SOP at 1.27 mm pitch; 0.5 mm-pitch MSOP is unforgiving with an iron.
- Need multi-vendor second sourcing? Anchor the requirement to the JEDEC outline number (e.g., MO-153 for TSSOP) so alternates drop in on the same footprint.
- Only decoding an existing part? Read the suffix and confirm against the datasheet drawing and its referenced outline.
Design mistakes that cause returns
- Swapping “SOP” for “SOIC” on the footprint. The EIAJ 5.3 mm body and JEDEC 3.9/7.5 mm bodies land differently; a name-based swap produces heel or toe misregistration.
- Reusing an SSOP footprint for a QSOP. 0.65 mm and 0.635 mm pitch look identical on a screen and diverge over 20+ pins.
- Ignoring θJA when downsizing. Moving a warm die from SOIC to VSSOP to save space can push the junction past its limit at high ambient — model it before you commit.
- Specifying an exposed-pad part without the thermal land and vias. The pad must be soldered to copper to do anything; leave it floating and you get the small-package θJA with none of the benefit.
- Skipping MSL handling. Fine-pitch, thin packages are moisture-sensitive; reflowing a part past its floor life invites popcorn cracking.
Frequently asked questions
What is the difference between SOP and SOIC?
They overlap but are not guaranteed identical. “SOIC” usually refers to the JEDEC outline (3.9 mm narrow or 7.5 mm wide body), while some vendors reserve “SOP” for the EIAJ Type II 5.3 mm body. Both use 1.27 mm pitch, but lead spans and footprints can differ, so verify the mechanical drawing before treating them as drop-in equivalents.
Is MSOP the same as VSSOP?
For most purposes, yes. TI and several other vendors treat VSSOP and MSOP as the same 3 mm-body form factor, registered under JEDEC MO-187. Historic vendor names for the same package include Analog Devices’ µMAX/micro SOIC, Maxim’s µMAX, and National’s MiniSO. Always confirm pitch (0.65 mm or 0.5 mm) from the datasheet.
What is the difference between TSSOP and SSOP?
Mainly height. SSOP keeps a taller profile (up to ~2 mm) with a moderate body, while TSSOP is the “thin” version at roughly 1.1 mm seated height. Both commonly use 0.65 mm pitch. If your constraint is vertical clearance, TSSOP wins; if it is simply pin density at a standard height, SSOP is enough.
Which is smaller, TSSOP or MSOP?
MSOP has the smaller footprint — about 3 mm × 3 mm for 8 and 10 pins — while a comparable TSSOP body is 4.4 mm wide. MSOP is also slightly thinner. TSSOP scales to far higher pin counts (up to 64–80), so “smaller” only holds at low pin counts; above ~16 pins TSSOP is usually the practical choice.
What is the lead pitch of a TSSOP package?
Typically 0.65 mm, dropping to 0.5 mm on higher pin-count variants to keep the body length in check. The pitch is the center-to-center spacing between adjacent leads and directly sets your stencil aperture and minimum trace/space. Confirm it on the datasheet drawing, since “TSSOP” alone does not fix the pitch.
Can I hand-solder TSSOP and MSOP packages?
TSSOP at 0.65 mm is hand-solderable with flux, a fine tip, and drag-soldering technique. MSOP at 0.5 mm is possible but frustrating and error-prone; reflow or hot-air is strongly preferred. For prototyping where an iron is the only tool, choose SOIC/SOP at 1.27 mm pitch and move to the fine-pitch package for production.
The bottom line
Pick by your binding constraint, not by the smallest number. If vertical space is tight, start at TSSOP. If board area rules and power is low, take MSOP/VSSOP and accept the thermal penalty. If you are pushing more than a few hundred milliwatts into a small outline, specify an exposed-pad HTSSOP or HVSSOP with a proper thermal land. And whenever a second source or a footprint reuse is on the line, write the JEDEC outline number into the requirement — that, not the acronym on the label, is what makes two parts truly interchangeable.
