Gowin Semiconductor makes flash-based and SRAM-based FPGAs spanning 1K to 138K LUTs, covering the low-to-mid-density space that AMD and Intel largely ignore. If you need a Gowin FPGA for a production board—or just want to prototype on a $20 Tang Nano 9K—this page gives you the complete product breakdown, real pricing context, authorized distributor options, and the PCB design considerations that the spec sheets leave out. FPGA.IO stocks Gowin devices and handles the board fabrication and assembly side, so you can go from part selection to populated boards in a single workflow.
Key Takeaways
– Three main families: LittleBee (1K–9K LUTs, flash, instant-on), Arora (18K–55K LUTs, SRAM), Arora V (15K–138K LUTs, 22nm, SerDes up to 12.5 Gbps).
– Typical lead times: 10–12 weeks for scheduled production. Mouser and Edge Electronics carry shelf stock on popular SKUs.
– Pin-compatible options: GW1N-2 and GW2AN-18 offer direct drop-in replacements for Lattice MachXO2 and MachXO3 packages.
– Price advantage: Unit pricing on LittleBee parts can run 30–50% below comparable Lattice iCE40 devices at 1K-piece quantities.
– 2026 expansion: New Arora I (GW1AN) and Arora III (GW3A) families rolling out with hybrid LUT4/LUT6 fabric and enhanced ADC.
What Makes Gowin FPGAs Different from AMD and Lattice
Gowin Semiconductor was founded in 2014 by Jason Zhu and Ning Song, both former senior design managers at Lattice Semiconductor. They spotted an opening: the major FPGA vendors were chasing high-end data-center silicon, while the low-density market—everything under about 50K LUTs—was underserved and overpriced. Gowin’s first silicon taped out in 2015 on a 55nm process, and revenue began in 2017.
Today, the Gowin FPGA portfolio covers three technology generations. The LittleBee family (55nm, flash-based) handles the 1K–9K LUT range. The Arora family (55nm, SRAM-based) covers 18K–55K LUTs. And the Arora V family (22nm, SRAM-based) pushes into the 15K–138K LUT range with integrated SerDes transceivers running up to 12.5 Gbps, PCIe 2.1 hard cores, and MIPI D-PHY/C-PHY hard IP. That puts the top end of the lineup in the same territory as mid-range Lattice ECP5 or Xilinx Spartan-7 parts—at meaningfully lower unit cost.
The practical advantage for procurement teams: Gowin’s scheduled production lead times typically run 10–12 weeks, versus the 26–52-week lead times that plagued AMD and Intel FPGA lines during recent allocation cycles. For teams that got burned by allocation games in 2021–2023, that difference is not trivial.
Here’s a trade-off worth knowing up front: Gowin’s documentation is thinner than what you get from AMD or Lattice. Pinout tables occasionally conflict between documents (one user reported I/O bank assignments differing between UG166 and UG114 for the same device), and FAE support response times can vary by region. The Gowin EDA toolchain downloads at around 600 MB and starts in seconds—a welcome contrast to Vivado’s 50 GB installer—but the IP library is smaller, and high-level synthesis support is less mature. You trade ecosystem depth for cost and lead-time advantage.
Complete Gowin FPGA Series — Every Family and Specification Compared
The Gowin FPGA list spans five distinct families as of mid-2026, plus several sub-families with integrated peripherals. The table below is the comparison that most distributor pages skip—every family, side by side, with the numbers that actually drive part selection.
| Family | Process | LUT Range | Memory Type | Config | I/O Voltage | Key Feature |
| LittleBee GW1N | 55nm | 1K–9K | Flash (NV) | Instant-on | 1.2/2.5/3.3V | Packages from 2.4×2.3 mm CSP |
| LittleBee GW1NS | 55nm | 4K–9K | Flash (NV) | Instant-on | 1.2/2.5/3.3V | ARM Cortex-M3 hard core |
| LittleBee GW1NRF | 55nm | 4K | Flash (NV) | Instant-on | 1.2/2.5/3.3V | Bluetooth LE radio |
| LittleBee GW1NSE | 55nm | 2K–4K | Flash (NV) | Instant-on | 1.2/2.5/3.3V | SRAM PUF security |
| Arora GW2A | 55nm | 18K–55K | SRAM | Ext. flash | 1.2/2.5/3.3V | Embedded SDRAM option (GW2AR) |
| Arora V GW5A/T | 22nm | 15K–138K | SRAM | Ext. flash | Multi-rail | SerDes 12.5 Gbps, PCIe 2.1, MIPI |
| Arora V GW5AS | 22nm | 25K | SRAM | Ext. flash | Multi-rail | Cortex-M4 @ 288 MHz + FPGA |
| Arora I GW1AN | TBD | Small | Flash (NV) | Instant-on | 3.3V direct | Pin-compatible to Lattice; 2026 |
| Arora III GW3A | TBD | Medium | SRAM | Ext. flash | Multi-rail | Hybrid LUT4/LUT6 fabric; 2026 |
LittleBee (GW1N) — The Go-To for Cost-Sensitive, Instant-On Designs
LittleBee parts use embedded flash, so they retain their configuration across power cycles and boot within milliseconds—no external SPI flash chip needed. That saves you one BOM line, one layout footprint, and eliminates a failure mode. The GW1N-9 in a QFN48 package gives you 8,640 LUTs, 17,280 flip-flops, and up to 116 user I/Os for around $3–5 at 1,000-piece pricing on Mouser, depending on speed grade. The smallest LittleBee devices ship in a chip-scale package measuring just 2.4 × 2.3 mm—genuinely impressive for an FPGA. That form factor has landed Gowin wins in wearables and IoT sensor nodes where board space is measured in single-digit square centimeters.
The sub-families add specific hard IP: the GW1NS embeds an ARM Cortex-M3 for combined FPGA+MCU designs, the GW1NRF integrates a Bluetooth LE radio, and the GW1NSE provides an SRAM PUF-based security root of trust for IoT authentication. The GW1NR variants integrate PSRAM, removing another external component.
Arora and Arora V — Mid-Range Performance with Integrated High-Speed Interfaces
The original Arora (GW2A) family is SRAM-based and covers 18K to 55K LUTs on a 55nm process. The GW2AR variant integrates SDRAM on-package, which is valuable for video buffering and display bridging applications where external DDR would add layout complexity and BOM cost.
The Arora V (GW5A/GW5AT/GW5AS/GW5AST) family is where Gowin competes against Lattice ECP5 and Xilinx Spartan-7 head-to-head. Built on 22nm SRAM technology, the flagship GW5AT-138 packs 138K LUTs, 6.4 MB of block RAM, 1.1 MB of distributed SRAM, and CDR-based SerDes transceivers from 270 Mbps to 12.5 Gbps. It also integrates a PCIe 2.1 hard core supporting x1, x2, and x8 modes, plus MIPI hard IP running at up to 2.5 Gbps per lane. DDR3 interfacing reaches 1,333 Mbps. The GW5AS variant embeds an ARM Cortex-M4 running at up to 288 MHz, giving designers a single-chip FPGA+MCU platform for industrial motor control (the FOC demo running at Embedded World 2025 used this exact device).
A counterintuitive point about Arora V: despite the 22nm process shrink, these parts are not targeting ultra-low power in the way Lattice iCE40 UltraPlus does. The SerDes transceivers and DDR3 interfaces burn real power. If your design is battery-operated and needs sub-milliwatt standby, LittleBee GW1NZ is the right pick, not Arora V.
Where to Buy Gowin FPGAs — Authorized Distributors and Sourcing Options
Finding a reliable Gowin distributor depends on your volume and geography. Here are the primary channels as of mid-2026:
Mouser Electronics is Gowin’s best-stocked authorized distributor globally. Mouser carries 77+ Gowin FPGA SKUs with real-time stock visibility, datasheets, and parametric search. For prototype quantities (1–100 pieces), Mouser is typically the fastest path to parts on your bench.
Edge Electronics is one of the few authorized Gowin distributors in the USA and carries both LittleBee and Arora V families along with development boards. Edge offers engineering support and can help with volume pricing discussions.
Rutronik covers the European market as an authorized franchise distributor. If your supply chain is Euro-centric, Rutronik can handle scheduling agreements and buffer stock programs.
JLCPCB / LCSC entered the picture in April 2026 through a collaboration with Gowin. Selected Gowin FPGA devices are becoming available within JLCPCB’s component ecosystem, allowing developers to source FPGAs alongside PCB fabrication and SMT assembly services. This channel makes the most sense for makers, educators, and small-run production where you want a single PO covering boards and parts.
Direct from Gowin: for volume production (10K+ units), contact Gowin’s regional sales offices directly. Gowin lists distributors and sales representatives by region on their website, covering the Americas (9 contacts in the US alone), Europe, and Asia-Pacific.
FPGA.IO stocks popular Gowin FPGAs and can source the full lineup through authorized channels. The advantage: you get FPGA procurement bundled with PCB fabrication and BGA assembly, so one supplier handles component sourcing, board manufacturing, and inspection under a single quality system.
Gowin FPGA Price Ranges, Lead Times, and Stock Realities
If you want to buy Gowin FPGA parts for production, pricing and availability matter more than datasheet specs. Here is what the market actually looks like.
Pricing benchmarks (approximate, 1K-piece quantities, commercial temp, 2026): LittleBee GW1N-1 in QFN32 runs around $1.00–$1.50. The popular GW1N-9 in QFN48 or LQ144 sits at roughly $3–$5. Arora GW2A-18 in BGA256 prices at approximately $8–$12. Arora V GW5AT-138 in a BGA676 package is in the $25–$40 range depending on volume and speed grade. These are directional—actual pricing depends on your volume commitment, distributor, and whether you are buying from shelf stock or scheduling a production lot.
Lead times: Gowin’s scheduled production lead times are 10–12 weeks. That is a significant advantage. During 2022–2023, comparable Lattice and AMD FPGA parts were quoting 40–52 weeks. Gowin’s shorter cycle partly reflects its fab partnerships and partly the lower overall demand on its production lines. Mouser and Edge carry buffer stock on high-runner SKUs, so prototype quantities of popular LittleBee parts often ship same-day.
The CCMC factor: Gowin Semiconductor was placed on the Chinese Military Company (CCMC) list by the U.S. government. For most commercial and hobbyist applications, this has no practical impact—parts remain freely available through Mouser, Edge, and other distributors. However, if your end-use involves U.S. government contracts, defense programs, or falls under ITAR/EAR restrictions, check with your compliance team before designing in Gowin parts. Several engineers on public forums have reported that certain institutional customers have blanket policies against CCMC-listed companies regardless of the actual regulatory requirement. This is a sourcing reality, not a technical one.
How to Select the Right Gowin FPGA for Your Design
Choosing a Gowin FPGA comes down to four questions: how many LUTs do you actually need, which interfaces does the silicon need to provide in hardware, what package can your PCB handle, and does the application require non-volatile (instant-on) configuration?
By application type: For MIPI camera-to-display bridging, sensor aggregation, or HDMI/DisplayPort conversion, start with GW2AR-18 (integrated SDRAM for frame buffering) or GW5AT-60 (if you need SerDes or higher throughput). For industrial motor control with FOC, the GW5AS-25K with its embedded Cortex-M4 at 288 MHz gives you a single-chip solution. For simple I/O expansion, protocol bridging, or LED control in consumer electronics, LittleBee GW1N-4 or GW1N-9 is the sweet spot. For IoT edge devices needing secure boot, the GW1NSE with SRAM PUF handles device authentication without an external secure element.
By package: This is where procurement and PCB design intersect. LittleBee parts come in QFN32, QFN48, LQ100 (LQFP100), and LQ144 packages—all of which can be assembled on standard 4-layer PCBs with conventional SMT processes. Arora and Arora V parts use BGA packages (PG256, PG484, FC676) with ball pitches ranging from 0.8 mm to 1.0 mm. A 1.0 mm pitch BGA breaks out comfortably on a 4-layer board with standard 6/6 mil trace/space rules. Drop to 0.8 mm pitch and you may need 4/4 mil rules or a 6-layer stack-up, which increases PCB fabrication cost by 30–60%. A 0.5 mm CSP pitch demands HDI with microvias—an entirely different cost tier.
One non-obvious selection criterion: if you need 3.3V-direct I/O drive without an external regulator for V_core, the LittleBee GW1N and the new Arora I GW1AN support it. The original Arora and Arora V require separate core voltage rails (typically 1.0V or 1.2V), adding voltage regulators and sequencing requirements to your BOM.
PCB Design and Assembly Checklist for Gowin FPGA Boards
Most Gowin distributor pages stop at the datasheet. The board-level design and assembly decisions are where production success or failure actually happens. Here is the checklist your fab and assembly partner needs to see.
1. Layer count vs. package pitch. For LittleBee in QFN or LQFP, a 4-layer stack-up with standard 6/6 mil trace/space is sufficient. For Arora V in a 1.0 mm pitch BGA, 4 layers still work—two signal layers and two reference planes. At 0.8 mm pitch (e.g., the PG484 or FC676 packages), plan for 6 layers minimum. Gowin’s own DDR3 hardware design guide (TN662E) recommends a minimum of six layers for any design using DDR3 memory interfaces, with eight layers preferred for signal integrity.
2. BGA breakout routing. A 1.0 mm pitch BGA with depopulated center rows (common on Gowin’s smaller BGA packages) can typically escape on two signal layers using 5 mil traces with 5 mil spacing and 10 mil via drills. The outer two rows route on the top layer; inner rows escape through vias to the inner signal layer. For 0.8 mm pitch, you need 4 mil traces, 4 mil spacing, and 8 mil via drills—confirm your fab supports this before committing the layout.
3. QFN thermal pad. LittleBee QFN packages have an exposed thermal pad on the underside. Per IPC-7093 guidelines, use 50–75% solder paste coverage on the thermal pad (hatched pattern on the stencil, not a solid aperture), and include at least 4–6 thermal vias (10–12 mil drill) in the pad to conduct heat to inner ground planes. Insufficient paste coverage reduces standoff height, which causes inner-row bridging on the signal pads.
4. Controlled impedance for LVDS and MIPI. Gowin’s LVDS I/Os and MIPI D-PHY interfaces need 100Ω differential impedance (50Ω single-ended). Specify controlled impedance on your fabrication drawing and run the stack-up calculator. On a standard 1.6 mm, 4-layer FR-4 board (Dk ≈ 4.2 at 1 GHz), a 5 mil trace width with 5 mil gap on an outer layer referenced to a ground plane at 10 mil spacing gives you roughly 100Ω differential. Verify with your fab’s actual prepreg Dk values; Shengyi S1000-2 and Isola 370HR run slightly different numbers.
5. Power supply sequencing. Arora V parts require specific power-up sequencing: V_CCINT (core) first, then V_CCAUX, then V_CCO (I/O banks). Violating the sequence can latch up the device or cause configuration failure. LittleBee parts are more forgiving—most can run from a single 3.3V rail with internal regulation—but always check the datasheet for your specific part number.
6. Reflow profile for BGA packages. Gowin’s BGA packages use SAC305 (lead-free) solder balls per J-STD-020. Standard IPC/JEDEC reflow profiles apply: peak temperature 245±5°C, time above liquidus (217°C) of 60–90 seconds, ramp rate 1–3°C/second. For mixed boards with both BGA and fine-pitch QFN components, X-ray inspection post-reflow is required per IPC-A-610 Class 2 or Class 3 to verify solder ball coalescence and catch voiding. FPGA.IO runs X-ray inspection as standard procedure on all BGA assemblies.
7. DFM review before order. Send your Gerber files, BOM, and pick-and-place data to your assembly house for a DFM review before committing to fabrication. The review catches mismatches between land patterns and actual package dimensions, stencil aperture issues, and insufficient clearances under BGA devices. A 30-minute review avoids a $5,000 respin.
Common Mistakes When Sourcing and Designing with Gowin FPGAs
These are the errors that show up repeatedly in forum threads, FAE conversations, and production debugging sessions:
1. Ignoring CCMC restrictions on defense-adjacent contracts. The technical merits are irrelevant if your end customer’s procurement policy blocks CCMC-listed vendors. Verify compliance requirements before the design phase, not during production ramp.
2. Selecting a BGA package without confirming your PCB fab’s minimum via drill. A 0.8 mm pitch BGA needs 8 mil (0.2 mm) via drills or smaller. Not every budget fab supports this. Ask for their capability sheet before you finalize the footprint.
3. Overlooking I/O bank voltage grouping. Gowin FPGAs assign I/Os to banks with shared voltage rails. If you need 1.8V LVDS on one set of pins and 3.3V LVCMOS on another, they must be in different banks. Gowin’s pinout documents (UG103, UG114, UG166) define the bank assignments, but as noted earlier, cross-check between documents—discrepancies have been reported.
4. Skipping the DFM review for fine-pitch QFN. LittleBee QFN48 pads are small. A stencil that is 0.05 mm oversized on the thermal pad opening can cause solder bridging to the inner row of signal pads during reflow. The fix is a segmented stencil aperture, but your assembler needs to know the package specifics in advance.
5. Single-sourcing without evaluating pin-compatible alternatives. Gowin offers pin-for-pin replacements for certain Lattice MachXO2 and MachXO3 devices (GW1N-2 for LQ100/LQ144, GW2AN-18 for MG132). Use this to build a dual-source strategy: qualify the Lattice part and the Gowin part on the same board. If one vendor hits allocation, you switch without a respin.
6. Underspecifying power delivery for Arora V SerDes. The 12.5 Gbps SerDes transceivers on the GW5AT-138 draw significant transient current. A single 0402 decoupling capacitor per power pin is not enough. Follow Gowin’s power integrity guidelines (check the GW5AT datasheet) and add bulk decoupling (10–47 µF ceramic) near the BGA. Signal integrity simulation of the power delivery network (PDN) is worth the effort on these designs.
Frequently Asked Questions About Gowin FPGAs
Are Gowin FPGAs reliable enough for production boards?
Yes. Gowin FPGAs are used in volume production across automotive (BOE and LG have adopted them for display applications), industrial automation, and consumer electronics. Gowin achieved ISO 26262 certification for its FPGA design environment in 2024, and the automotive-grade GW1N-A line carries full AEC-Q100 Grade 2 qualification (operating up to 105°C).
What is the cheapest Gowin FPGA available?
The GW1N-1 (LittleBee, 1,152 LUTs) in a QFN32 package is the lowest-cost entry point, running roughly $1.00–$1.50 at 1,000-piece quantities. For development, the Sipeed Tang Nano 1K board using this chip costs about $5 retail.
Does Gowin support both Verilog and VHDL?
Gowin EDA supports Verilog, Verilog-2001, SystemVerilog subsets, and VHDL. The open-source Apicula project (via Yosys + nextpnr) provides an alternative synthesis and place-and-route flow for LittleBee devices, though it currently uses Verilog only.
Can I use a Gowin FPGA as a drop-in replacement for Lattice?
For certain packages, yes. The Gowin GW1N-2 and GW2AN-18 offer pin-for-pin compatibility with Lattice MachXO2 and MachXO3 devices in LQ100, LQ144, and MG132 packages. You still need to resynthesize your HDL under Gowin EDA—the bitstream format is different—but the PCB does not change.
What development boards exist for Gowin FPGAs?
Sipeed’s Tang series is the main ecosystem: Tang Nano 1K (~$5), Tang Nano 9K (~$20, GW1NR-9, HDMI output), Tang Primer 25K (GW5A-25K), and Tang Mega 138K Pro (GW5AST-138K). Gowin also sells its own starter kits (DK-START-GW1N4, DK-START-GW1N9) through authorized distributors.
Are Gowin FPGAs RoHS and REACH compliant?
Gowin’s commercial and automotive product lines are RoHS compliant with SAC305 lead-free solder balls. Confirm REACH compliance status for specific part numbers through your distributor, as material declarations can update between production lots.
How does Gowin FPGA pricing compare to Lattice and AMD?
At the low end (1K–9K LUTs), Gowin LittleBee parts run 30–50% below comparable Lattice iCE40 or MachXO3 devices. In the mid-range (25K–60K LUTs), the pricing gap narrows but Gowin’s Arora V parts still undercut Lattice ECP5 and AMD Spartan-7 parts, particularly when factoring in the shorter lead times that reduce inventory carrying cost.
Start Your Gowin FPGA Project — From Part Selection to Assembled Boards
Gowin FPGAs fill a genuine gap in the market: real production-grade programmable logic at price points and lead times that the major vendors struggle to match in the low-to-mid-density range. The trade-off is a smaller IP ecosystem and thinner documentation, but for applications in display bridging, sensor interfacing, industrial control, and IoT edge devices, that trade-off works.
An anonymized case worth noting: a robotics startup designed their motor control board around a GW5AS-25K, combining FOC control logic in the FPGA fabric with supervisory code on the embedded Cortex-M4. By sourcing the Gowin FPGA through the same supplier handling their 6-layer PCB fabrication and BGA assembly, they cut their prototype cycle from 8 weeks to 4—no separate component POs, no freight coordination, no incoming inspection on their end. That kind of workflow compression is where the real cost savings happen, beyond the unit price of the FPGA itself.
If you are evaluating Gowin FPGAs for an upcoming design, send your BOM and Gerber files to FPGA.IO for a combined component sourcing and assembly quote. We handle DFM review, FPGA procurement, board fabrication, and SMT/BGA assembly under one roof.
