An HLQFP package is a low-profile quad flat package with the leadframe die pad exposed on the bottom, soldered to the board as a thermal and electrical connection. NXP defines it as a thermal enhanced low profile quad flat package, and the H stands for heat sink. The pad can cut junction-to-case resistance by more than an order of magnitude — but only if you solder it, and only if the land, vias and stencil are right.
Key takeaways
- The exposed pad is a down-set leadframe die pad, not an added heat slug or spreader.
- Measured on the same board, soldering the pad nearly halves θJA on a 144-lead LQFP.
- Package stand-off is nominally 100 µm ± 50 µm, which is why thermal pad print reduction is milder than on leadless packages.
- NSMD pads are recommended, and the board pad should be at least congruent with the package pad.
- The pad is not connected to the die circuitry; if you tie it to a net, it must be ground.
- The joint under the pad is invisible to AOI. Budget for X-ray.
What an HLQFP package is
An HLQFP is a plastic LQFP whose leadframe die pad is down-set far enough to sit flush with the bottom of the molded body. That exposed metal is soldered to a matching land on the PCB, giving heat a direct path from the die into the board instead of a long path out through the leads.
[IMAGE 1: cross-section of an HLQFP showing the down-set die pad exposed at the package bottom, die attach, wire bonds and gull-wing leads | alt: “HLQFP package cross-section showing the exposed die pad soldered to the PCB thermal land”]
Two naming conventions are stacked in the acronym. The H prefix denotes a heat sink, so HLQFP means an LQFP with a thermal pad on the board-mount side, and the L denotes an installation height above 1.20 mm and up to 1.70 mm.
Real outlines confirm the geometry. NXP’s SOT1571-6 is an HLQFP48 at 0.5 mm pitch, 7 mm × 7 mm × 1.5 mm body, with a 4.4 mm × 4.4 mm exposed pad and a seated height of 1.5 mm against a 1.4 mm package height. SOT1510-2 is an HLQFP64 at 10 mm × 10 mm × 1.4 mm; SOT1570-1 an HLQFP100 at 14 mm × 14 mm × 1.6 mm.
The same package under six names
This is where searches go wrong. Every major supplier has its own label for the same construction.
| Name | Who uses it | Notes |
| HLQFP | NXP, Renesas | Thermal enhanced LQFP; HTQFP is the thin-body version |
| ExposedPad LQFP/TQFP | Amkor | Marketed on low loop inductance using the paddle as a ground path, to 2.4 GHz |
| PowerPAD LQFP | Texas Instruments | Deep down-set exposed die pad, chip-up and chip-down variants |
| QFP with exposed die pad | Infineon | Created by an appropriate leadframe down-set |
| Thermal pad / power pad | Generic | TI treats thermal pad, exposed pad and power pad as the same thing |
| MO-204 | JEDEC | Registered outline “Plastic Quad Flat Package Outline With Exposed Heat Sink,” Issue B, May 2001 |
JEDEC also allows the feature inside the main LQFP family: MS-026 is titled “Low/Thin Profile Plastic Quad Flat Package, 2.00 mm Footprint, Optional Heat Slug,” Issue D, January 2001. Search on the construction, not the acronym.
What the exposed pad is actually worth
The exposed pad changes where the heat goes. In a standard plastic quad flatpack, 80% of heat leaves by conduction through the leads and 20% by convection from the body. With a leadframe-attached heat slug, that becomes 76% and 24%. With an exposed die pad it becomes 87% conduction — 77% into the board and 10% through the leads — against 13% convection.
Numbers below are TI’s modeled data for exposed-pad LQFP and TQFP packages on the TI recommended board, which has the properties of the JEDEC high thermal conductivity PCB. The final column is a standard package on a JEDEC low-conductivity board with 1 oz trace — a different board, not a like-for-like control.
| Package | Designator | θJA, pad soldered | θJA, not soldered | θJC, exposed pad | Standard pkg θJA / θJC |
| LQFP 144 | PRP | 15.68 °C/W | 27.52 °C/W | 0.13 °C/W | 47.34 / 4.62 °C/W |
| LQFP 160 | PSP | 11.14 °C/W | 22.40 °C/W | 0.10 °C/W | 43.93 / 3.70 °C/W |
| LQFP 176 | PTP | 14.52 °C/W | 24.46 °C/W | 0.10 °C/W | 42.95 / 3.67 °C/W |
| LQFP 208 | PYP | 10.96 °C/W | 21.48 °C/W | 0.10 °C/W | 39.18 / 3.66 °C/W |
| TQFP 100 | PZP | 17.28 °C/W | 27.32 °C/W | 0.12 °C/W | 49.17 / 3.11 °C/W |
| TQFP 48 | PHP | 29.11 °C/W | 64.42 °C/W | 1.14 °C/W | 108.71 / 18.18 °C/W |
The θJC column is the headline. On a 144-lead LQFP it falls from 4.62 °C/W to 0.13 °C/W. The die is effectively touching the board.
Suppliers publish a designator cross-reference for the swap. TI’s 20 × 20 mm LQFP144 is PGE144 as standard, PRP144 as chip-up exposed pad, PRD144 as chip-down; the LQFP208 runs PDV208, PYP208, PYD208. Same body, same leads, same assembly process.
Worked example: the cost of not soldering the pad
Take the LQFP144 above, a 2 W device, and an 85 °C ambient. Junction temperature is TJ = TA + P × θJA.
- Pad soldered: 85 + (2 × 15.68) = 116.4 °C
- Pad on the same board but not soldered: 85 + (2 × 27.52) = 140.0 °C
Against a 125 °C maximum junction temperature, one build passes with 9 °C of margin and the other fails by 15 °C. Nothing about the package or the board changed — only whether the assembler put paste under the pad.
That 23.6 °C answers “do we need the thermal land.” TI notes that significant improvement is still present with solder joint areas as small as 16%, and that above a certain joint area θJC and θJA converge within measurement error. Partial coverage helps; zero coverage costs most of the package.
Land pattern rules that are not optional
[IMAGE 2: PCB land pattern for an HLQFP showing the congruent thermal land, segmented stencil apertures and a thermal via array positioned between apertures | alt: “HLQFP package land pattern with segmented stencil apertures and thermal via array”]
Infineon recommends NSMD pads for QFP components, applied to the peripheral terminations and the exposed pad alike, and advises against mixing solder-mask-defined and non-solder-mask-defined types within one footprint.
Size the thermal land from the package, not from habit. The board pad should be congruent with the package pad at minimum; matching it exactly also improves solder joint reliability and, in some applications, electrical performance. Renesas states the same rule for HLQFP and HTQFP: match the die pad dimensions D2 × E2.
One detail catches people out. Exposed pads can carry an anti-flash profile — meander structures around the outline that taper off mold flash — and the outer extension including that profile is the reference for the PCB pad. Measure to the outside of the meander.
Finally, a placement rule: exposed-pad packages should not sit opposite each other on the two sides of a double-sided board, because this stiffens the assembly and makes solder joints fatigue earlier than an offset arrangement.
Thermal vias without wrecking the solder joint
Vias carry heat from the thermal land to inner or bottom copper. A typical hole diameter is 0.2 mm to 0.5 mm, and a 1.0 mm to 1.2 mm pitch array is a reasonable starting point. TI’s own example uses a 1.5 mm via pitch.
Do not assume more is better. A constant increase in the number of vias does not translate into a constant decrease in the thermal resistance of the assembly. Model or measure before adding a fifth row.
The bigger risk is solder wicking down the holes, which reduces stand-off, increases voiding, and can push surplus solder through to the far side of the board. Three defenses, in order of preference:
- Position the vias under the beam intersections of the segmented stencil aperture, so paste is never printed directly over a hole. Done well, this allows a good joint with vias left open on both sides.
- Plug the vias with epoxy and overplate. Vias 100 µm in diameter or smaller should be copper-filled and overplated. In both cases specify a planar fill, or trapped gas will form voids during reflow.
- Tent with solder mask — but tenting only on the opposite side of the board increases the voiding rate significantly.
If the pad does not need a direct connection to inner layers, put the vias next to the footprint and cover them with solder mask.
Stencil design and the 100 µm stand-off
Here is the constraint that separates exposed-pad LQFP from QFN work. The package stand-off — the distance between the I/O lead seating plane and the exposed pad landing area — is nominally 100 µm and varies by ±50 µm. The leads sit above the pad plane, so paste under the pad can lift the part and starve the lead joints.
| Parameter | Starting value |
| Stencil thickness, 0.5 mm pitch | 130–150 µm (5–6 mil) |
| Stencil thickness, 0.4 mm pitch | 130 µm (5 mil) maximum |
| Thermal pad print reduction | approx. 70–80% of pad area |
| Aperture size before segmenting | segment above approx. 5 mm |
| Spacing between aperture segments | 0.15 mm or more |
| Solder paste type | Type 4 recommended, typically SAC305 |
| Placement accuracy | ±50 µm on modern vision-equipped machines |
The 70–80% reduction is deliberately less aggressive than on leadless packages, where terminations and pad sit in one plane. Large single apertures also get scooped by the squeegee, the second reason to segment. NXP adds a compatible rule: keep 0.15 mm or more between segments, since narrower spacing becomes a manufacturing problem.
What to connect the pad to
The exposed pad is a mechanical and thermal feature first. There is no electrical connection between the die pins and the flag: the epoxy bonds the die substrate to the pad but provides no external connection for the circuitry on the die.
That does not make the net a free choice. If the pad land is tied to a potential, that potential must be device ground, and EMC improves when the pad is soldered and grounded. NXP allows one exception: at tens of milliwatts and ambients no higher than about 60 °C the pad may not need soldering, though a soldered joint remains the more reliable mechanical connection.
Inspection, rework and five mistakes that cause returns
[IMAGE 3: X-ray image of a soldered HLQFP showing lead joints, the exposed pad joint and vias in pad | alt: “X-ray inspection of an HLQFP package exposed pad solder joint with vias in pad”]
AOI handles the gull-wing joints, but exposed pads need automated X-ray, which catches bridging, voiding and missing parts — though broken joints stay hard to see. Expect voids: large exposed pads increase voiding because the volume-to-surface ratio is poor for outgassing during reflow, and the extent depends on pad size, via and stencil layout, paste and profile.
- Leaving the thermal land off the footprint. On the worked example above that is 23.6 °C of junction temperature.
- Printing the pad aperture at 100%. With a 100 µm stand-off, excess paste lifts the package and starves the lead heels.
- Open vias under a solid aperture. Paste flows down the hole, the stand-off drops and voids grow.
- Tying the pad to a non-ground net. It has to be ground or nothing.
- Placing exposed-pad parts back-to-back across the board. The stiffened assembly fatigues joints early under temperature cycling.
On rework, QFP components are reworkable in general, but single-joint repair on fine-pitch terminations is not recommended, and completely de-soldered components should be replaced rather than reused. Dry the board and part per J-STD-033 first.
HLQFP FAQ
What does HLQFP stand for?
HLQFP stands for heat sink low-profile quad flat package, which NXP describes as a thermal enhanced low profile quad flat package. It is an LQFP with the leadframe die pad exposed on the bottom of the body so it can be soldered to a matching land on the board. The H denotes the heat sink feature; the L denotes the low-profile body height.
Do you have to solder the exposed pad?
Almost always, yes. On a 144-lead exposed-pad LQFP, leaving the pad unsoldered raises junction-to-ambient resistance from about 15.7 °C/W to about 27.5 °C/W on the same board. NXP allows an exception for devices dissipating only tens of milliwatts at ambients no higher than roughly 60 °C, where the pad may be left unattached.
What should the HLQFP thermal pad be connected to?
Ground, or nothing. There is no electrical connection between the die circuitry and the pad inside the package, but if the land is tied to any potential, NXP requires that potential to be device ground. Soldering the pad to a ground land also improves EMC performance and gives the package a more reliable mechanical connection to the board.
How many thermal vias does an HLQFP need?
Start with a 0.2 mm to 0.5 mm diameter array on a 1.0 mm to 1.2 mm pitch, then optimize. Adding vias gives diminishing returns — thermal resistance does not fall in proportion to via count — so model or measure rather than filling the land. Place the vias where the segmented stencil apertures are not printing paste.
Is HLQFP the same as PowerPAD or ePad LQFP?
Functionally, yes. HLQFP is NXP’s and Renesas’ name, PowerPAD is TI’s, ExposedPad LQFP/TQFP is Amkor’s, and Infineon simply calls it a QFP with an exposed die pad. All describe a down-set leadframe die pad exposed at the package bottom. JEDEC registers the outline family as MO-204, and MS-026 covers the optional heat slug variant.
What to do next
Specify an HLQFP when lead conduction alone will not hold junction temperature, and when you can commit board area for a thermal land and via array. Before layout, do four things: take θJA for the soldered and unsoldered cases from the datasheet and run the junction-temperature arithmetic at worst-case ambient; size the thermal land from the package drawing including the anti-flash profile; agree the print reduction and via closure method with your assembly house; and confirm X-ray coverage is in the test plan. If the calculation shows margin either way, use a plain LQFP and keep the routing channel.
Internal links
- [INTERNAL LINK: LQFP package guide → body thickness, pitch and land pattern basics]
- [INTERNAL LINK: thermal via design → diameter, pitch, plugging and tenting trade-offs]
- [INTERNAL LINK: θJA, θJC and ΨJT explained → reading thermal metrics on a datasheet]
- [INTERNAL LINK: QFN vs exposed-pad QFP → choosing between leadless and leaded thermal packages]
- [INTERNAL LINK: stencil design for mixed-technology boards → thickness, area ratio and segmentation]
Sources
- NXP, SOT1571-6 package information (HLQFP48): https://www.nxp.com/docs/en/package-information/SOT1571-6.pdf
- NXP, SOT1570-1 package page (HLQFP100): https://www.nxp.com/packages/SOT1570-1
- Infineon, Recommendations for Board Assembly of Infineon Quad Flat Packages, Rev. 6.0: https://www.infineon.com/dgdl/Infineon-Board_Assembly_Recommendations-QFP-Package-v06_00-EN.pdf
- Texas Instruments, SNOA921, PowerPAD thermally enhanced plastic packages: https://www.ti.com/lit/an/snoa921/snoa921.pdf
- JEDEC, Master Index for JEDEC Publication No. 95: https://www.jedec.org/sites/default/files/Master.pdf
