A TSSOP-56 package measures 13.9 mm to 14.1 mm long by 6.0 mm to 6.2 mm wide, with 56 leads on 0.5 mm pitch, a 7.9 mm to 8.3 mm lead span and a 1.2 mm maximum height. The catch at this lead count is that two versions share that outline: a plain one used for 16-bit logic, and an exposed-pad version with a 57th terminal underneath that changes both the footprint and the thermal budget.

Key takeaways

• TSSOP-56 dimensions per TI drawing DGG0056A: body 13.9 mm to 14.1 mm by 6.0 mm to 6.2 mm, lead span 7.9 mm to 8.3 mm, pitch 0.5 mm, height 1.2 mm max.
• Check whether your part is the plain DGG outline or the exposed-pad DCA HTSSOP. Same length and pitch, but the DCA adds a bottom pad numbered as terminal 57.
• That pad is worth 2.7 times: TI lists 81 °C/W for the plain 56-pin TSSOP and 30.3 °C/W for the 56-pin HTSSOP.
• Moisture handling splits the same way: Level 1 with unlimited floor life on plain logic, Level 3 with 168 hours on the exposed-pad gate driver.
• At 14 mm long this is one of the biggest packages in the family, and TI’s own rework note calls out 56-pin TSSOP as a case needing local preheat around 160 °C.

[IMAGE 1: dimensioned top, side and end view of a 56-lead TSSOP with pitch, lead span and height called out | alt: “TSSOP-56 package dimensions showing 0.5 mm pitch and 8.1 mm nominal lead span”]

Two packages share the TSSOP-56 outline

The lead count itself is settled. JEDEC Publication 95, in its index by device type, lists 56 among the registered MO-153 variations, alongside 48, 52, 60 and 64, and TI references MO-153 on the DGG0056A drawing. What is not settled is what sits underneath the package.

TI ships two 56-lead TSSOPs. The DGG outline carries 16-bit logic such as the SN74ALVCH16543 and has no pad. The DCA outline is a PowerPAD HTSSOP used by gate drivers such as the DRV8301, and its exposed pad appears in the pin table as terminal 57, described as a ground pin that must be soldered to the ground plane and connected to the bottom side through vias.

Read manufacturer summary fields carefully. The DRV8301 device information table gives a body size of 14.00 mm by 8.10 mm, which is length by lead span rather than length by body width; distributor listings for the same part show 14.1 mm by 6.2 mm by 1.05 mm. Both describe the same package, and only the drawing settles which number is which.

TSSOP-56 dimensions

Table 1 lists the controlled dimensions from TI drawing DGG0056A, revision 4222167/A dated July 2015.

Table 1. TSSOP-56 mechanical data, dimensions in mm

Parameter	Value	Note
Leads	56, 28 per side	54 spaces at 0.5 mm
Lead pitch	0.5	13.5 mm lead row per side
Body length	13.9 to 14.1	excludes mold flash up to 0.15 mm per side
Body width	6.0 to 6.2	the 6.1 mm TSSOP body
Lead span	7.9 to 8.3 typ	identical to the 48-lead version
Height	1.2 max	same 1.2 mm ceiling across the family
Standoff	0.05 to 0.15	the JEDEC range quoted in SLMA002
Lead width	0.17 to 0.27	against a 0.3 mm land
Foot length	0.50 to 0.75	gage plane at 0.25 mm
Lead angle	0 to 8 degrees
Exposed pad	none on DGG, present on DCA	DCA numbers it terminal 57
JEDEC reference	MO-153	56 leads is a registered variation

Only the length changes as you move up the family. TI dimensions 48 leads at 12.4 mm to 12.6 mm and 64 leads at 16.9 mm to 17.1 mm on the same 6.0 mm to 6.2 mm width and 7.9 mm to 8.3 mm span, so a 56-lead part is a 14 mm variant of a shape you may already have on the board.

TSSOP-56 footprint, thermal land and stencil

For the plain outline, TI shows 56 lands of 1.5 mm by 0.3 mm at 0.5 mm pitch, rows dimensioned at 7.5 mm, non solder mask defined, with 0.05 mm of mask clearance all around. The stencil example uses the same aperture size on a 0.125 mm foil.

Land area works out at roughly 124 mm²: 13.8 mm along the rows, from 27 spaces at 0.5 mm plus one land width, by 9.0 mm across, from the 7.5 mm row dimension plus one land length. That is a third more copper than the 48-lead version for eight more connections.

The gap between adjacent lands is 0.2 mm, the same as every other 0.5 mm pitch package in this family. Threading a trace between pads is not realistic at standard fabrication rates, so plan escapes through vias placed between or outside the land rows.

If the part is the exposed-pad version, take the thermal land, via pattern and aperture table from the drawing for that specific device, then follow two rules from TI’s PowerPAD report. Connect thermal vias to the internal planes with a continuous annulus rather than thermal relief spokes, because spokes exist to slow heat transfer. And at a 5 mil stencil, use a 1:1 aperture to pad ratio, growing the aperture only if the foil is thinner.

[IMAGE 2: land pattern with 56 lands and the 0.2 mm gap called out, next to the exposed-pad variant with its thermal land | alt: “TSSOP-56 footprint with 1.5 mm by 0.3 mm lands on 0.5 mm pitch”]

Thermal performance: the pad is worth 2.7 times

TI publishes 81 °C/W junction-to-ambient for the plain DGG package on the SN74ALVCH16543, calculated per JESD 51. For the DRV8301 in the 56-pin DCA HTSSOP it publishes 30.3 °C/W, with junction-to-case through the bottom at 0.9 °C/W and junction-to-board at 17.5 °C/W.

Convert to power budgets. At an 85 °C ambient and a 150 °C junction limit, the plain package supports about 0.80 W and the exposed-pad version about 2.15 W. The 0.9 °C/W bottom path is the whole reason, and it only exists if the pad is soldered.

One comparison worth carrying: on the 56-lead SN74ALVCH16543, TI lists the wider 300-mil SSOP at 74 °C/W against 81 °C/W for the TSSOP, so the SSOP is the better thermal package here. On the 48-lead SN74ALVCH162244 the ordering reverses, at 89 °C/W for the TSSOP and 94 °C/W for the SSOP. Do not carry a rule of thumb between lead counts.

For the logic case, work the switching load rather than assuming. The SN74ALVCH16543 lists power dissipation capacitance of 64 pF at 3.3 V with outputs enabled. Treating that as a per-channel figure, adding a 30 pF load and running 16 channels at 25 MHz gives about 0.41 W, which is a 33 °C junction rise at 81 °C/W.

TSSOP-56 pinout and terminal 57

Numbering follows the usual rule: pin 1 at the index feature, counterclockwise from the top view, pins 1 to 28 down one side and 29 to 56 back up the other. Beyond that, the two families using this outline arrange pins very differently.

The 16-bit logic convention is regular. On the SN74ALVCH16543, the A ports occupy one side and the B ports the other, ground sits on pins 4, 11, 18, 25, 32, 39, 46 and 53, and VCC sits on pins 7, 22, 35 and 50. Twelve of 56 pins are supply, spaced every few pins so that return paths stay short.

The gate driver convention is functional rather than symmetric. The DRV8301 groups SPI and buck control on pins 1 to 16, PWM inputs on 17 to 22, current sense on 30 to 33, and the three half-bridge gate outputs on 34 to 48, with the pad as terminal 57 tied to device ground. Analog ground on pin 28 is required to connect back to that pad through a low impedance fill.

Check that your schematic symbol exposes terminal 57. A symbol built from a 56-pin table leaves the pad unconnected, and the layout will pass DRC while the ground return and the heat path are both missing.

Assembly, moisture sensitivity and rework

Moisture ratings split along the same line as the pad. TI rates the SN74ALVCH16543 in DGG at Level 1 with a 260 °C peak and unlimited floor life. The DRV8301 in DCA is Level 3 with a 260 °C peak and 168 hours, so the exposed-pad part needs floor-life tracking and a bake if the reel sits open.

Packing differs in pocket depth rather than tape width. The logic version ships 2000 per 330 mm reel on 24 mm tape with pockets 8.9 mm by 14.7 mm by 1.4 mm deep. The gate driver ships 2000 per reel on the same 24 mm tape with pockets 8.6 mm by 15.6 mm by 1.8 mm, plus a 35-piece tube option that the logic part does not offer.

Rework deserves planning at this size. TI’s PowerPAD report recommends preheating the local PCB area to roughly 160 °C before removal, and calls out 56-pin TSSOP explicitly as a case where that preheat helps. Hot air with a vacuum pickup is the recommended removal method, and stencilled paste is preferred over hand-dispensed solder for reattachment.

On sourcing, distributor listings for the DRV8301DCA and DRV8302DCA sat in the range of roughly 45 Malaysian ringgit and 60 Swedish krona in single quantities when checked in August 2026, both from stock. The plain logic parts are cheaper by an order of magnitude, which is a reminder that the two devices sharing this outline are not substitutes for each other in any sense.

Five mistakes that cost a board spin

1. Assuming a 56-pin TSSOP has no thermal pad. The DCA version does, and omitting its land removes both the ground return and the 0.9 °C/W heat path.
2. Reading a summary field of 14.00 mm by 8.10 mm as body dimensions. That second number is the lead span; the body is 6.0 mm to 6.2 mm wide.
3. Connecting thermal vias with relief spokes. TI’s PowerPAD report asks for a continuous connection around the hole, since spokes are designed to impede heat flow.
4. Carrying the thermal rule of thumb from another lead count. On 56 leads the SSOP beats the TSSOP at 74 against 81 °C/W, and on 48 leads the order reverses.
5. Reworking a 14 mm package without local preheat. TI names 56-pin TSSOP as a case for preheating the board area to about 160 °C first.

TSSOP-56 package FAQ

What are the dimensions of a TSSOP-56 package?

Body length is 13.9 mm to 14.1 mm, body width 6.0 mm to 6.2 mm, lead span 7.9 mm to 8.3 mm and height 1.2 mm maximum, on 0.5 mm pitch, per TI drawing DGG0056A. Lead width runs 0.17 mm to 0.27 mm and foot length 0.50 mm to 0.75 mm, with 54 spaces giving a 13.5 mm lead row.

What is the pitch of a TSSOP-56 package?

It is 0.5 mm, the same as the 48-lead and 64-lead members of the family. TI dimensions the row as 54 spaces at 0.5 mm. The land pattern uses 1.5 mm by 0.3 mm lands, which leaves 0.2 mm of bare laminate between adjacent lands.

What is the difference between TSSOP-56 and HTSSOP-56?

HTSSOP-56, which TI calls the DCA outline, is the same 14 mm by 6.1 mm body with an exposed thermal pad underneath, numbered as terminal 57 and tied to ground. Junction-to-ambient falls from 81 °C/W to 30.3 °C/W, and the moisture rating tightens from Level 1 to Level 3.

Is TSSOP-56 the same as TSOP-56?

No, and the numbers invite confusion. Both use 0.5 mm pitch and both mention 14 mm, but TSSOP-56 is 14 mm long and 6.1 mm wide, while a TSOP-56 memory package is about 14 mm wide and 18.4 mm long. The land patterns share nothing.

What is pin 57 on a 56-pin package?

On TI’s DCA outline the exposed pad is numbered as terminal 57. In the DRV8301 it is the device ground: TI requires it to be soldered to the ground plane for correct operation and connected to the bottom side through vias for heat spreading.

Choosing between the two 56-lead options

Table 2 puts the two outlines side by side, using the SN74ALVCH16543 for the plain package and the DRV8301 for the exposed-pad version.

Table 2. Plain TSSOP-56 against the exposed-pad HTSSOP-56

Attribute	TSSOP-56 (TI DGG)	HTSSOP-56 (TI DCA)
Example device	SN74ALVCH16543 16-bit transceiver	DRV8301 three-phase gate driver
Body	13.9 to 14.1 by 6.0 to 6.2 mm	same outline, 1.2 mm max height
Exposed pad	none	terminal 57, tied to ground
Junction-to-ambient	81 °C/W	30.3 °C/W
Junction-to-case, bottom	not published	0.9 °C/W
Power at 85 °C, 150 °C junction	about 0.80 W	about 2.15 W
Moisture sensitivity	Level 1, 260 °C, unlimited	Level 3, 260 °C, 168 h
Tape pocket	8.9 by 14.7 by 1.4 mm, 2000 per reel	8.6 by 15.6 by 1.8 mm, 2000 per reel
Tube option	not offered on this device	35 pieces

What to do next

Open the drawing for your exact orderable part number and answer one question first: is there a pad on the bottom. If not, lay 56 lands of 1.5 mm by 0.3 mm at 0.5 mm pitch with rows at 7.5 mm, non solder mask defined, and route escapes with vias rather than traces between pads.

If there is a pad, add the thermal land and via array from that drawing, connect the vias to the planes with full annular copper, expose terminal 57 in the symbol, and treat the pad as a ground connection in the netlist rather than a mechanical detail.

Then check two numbers before release: the moisture level on the reel you are actually buying, and the junction rise from your own switching or gate-drive load. A 14 mm package with 56 leads gives you plenty of pins, and neither of those numbers forgives being skipped.

[IMAGE 3: exploded comparison of the plain and exposed-pad 56-lead outlines with their land patterns | alt: “TSSOP-56 and HTSSOP-56 land patterns compared at the same scale”]

Internal links

• [INTERNAL LINK: TSSOP-48 package -> TSSOP-48 dimensions, pinout and footprint]
• [INTERNAL LINK: TSSOP-44 package -> TSSOP-44 dimensions, pinout and footprint]
• [INTERNAL LINK: TSSOP-38 package -> TSSOP-38 dimensions, pinout and footprint]
• [INTERNAL LINK: exposed pad thermal via design -> PowerPAD and thermal land layout guide]
• [INTERNAL LINK: moisture sensitivity level -> MSL floor life, baking and dry pack handling]

External references

• TI SN74ALVCH16543 datasheet, containing drawing DGG0056A: https://www.ti.com/lit/ds/symlink/sn74alvch16543.pdf
• TI DRV8301 datasheet, 56-pin HTSSOP thermal data and layout guidance: https://www.ti.com/lit/ds/symlink/drv8301.pdf
• TI PowerPAD Thermally Enhanced Package application report SLMA002: https://www.ti.com/lit/pdf/slma002
• TI SN74ALVCH16269 datasheet, same DGG0056A drawing: https://www.ti.com/lit/ds/symlink/sn74alvch16269.pdf
• JEDEC Publication 95 index by device type: https://www.jedec.org/sites/default/files/MOIND_DT.pdf