The SOIC-24 package is a 24-lead wide-body small outline IC with a 7.5 mm body and 1.27 mm lead pitch, built to JEDEC standard MS-013-AD. It measures roughly 15.4 mm long by 7.5 mm wide, with gull-wing leads spanning about 10.3 mm tip to tip and a 2.65 mm maximum height. Any 24-lead part called SOIC is this wide 0.300 in body — 24 leads do not fit the narrow 3.9 mm frame. Below is the full dimension table, a ready land pattern, and the thermal and sourcing numbers datasheets bury.
Key takeaways
- SOIC-24 is always wide body (7.5 mm / 0.300 in). There is no narrow SOIC-24.
- Registered outline: JEDEC MS-013-AD, 1.27 mm pitch, 2.65 mm max height.
- Body ≈ 15.4 mm × 7.5 mm; lead span (tip to tip) ≈ 10.3 mm.
- Junction-to-ambient thermal resistance is about 60 °C/W on a 4-layer board — a wide-body advantage over shrink packages.
- “Pinout” means a fixed numbering convention, not a fixed function map; pin functions are device-specific.
- A common 24-SOIC part (mux) sells near $0.67 in single units and stays active while its DIP twin is obsolete.
What SOIC-24 specifies
SOIC stands for Small Outline Integrated Circuit: a surface-mount body with two rows of gull-wing leads on the long sides. The number is the lead count. The trap is body width. Small outline refers to standards from more than one organization — JEDEC MS-012 (3.9 mm narrow body) and MS-013 (7.5 mm body), both at 1.27 mm pitch — plus the JEITA/EIAJ family. That ambiguity matters because parts in different widths are not footprint-interchangeable.
For 24 leads the question is settled. The narrow MS-012 family tops out at 16 leads, so every SOIC-24 is the wide MS-013 body, and the registered variant is MS-013-AD. If a supplier’s parametric filter shows a 24-lead part as “SOIC (0.295 in / 7.50 mm width),” that is this package. A separate 5.3 mm EIAJ body exists at high pin counts, but vendors label that SOP, not SOIC. Match the datasheet’s registered outline to your footprint before you trust any generic “SOIC-24” library part.
[IMAGE 1: labeled SOIC-24 top and side view showing body length D, body width E1, lead span E, height A, pitch e | alt: “SOIC-24 package dimensions diagram showing 7.5 mm wide body and 1.27 mm pitch”]
SOIC-24 dimensions (JEDEC MS-013-AD)
The table below is the registered MS-013-AD envelope, cross-checked against three manufacturer outlines that all resolve to the same values.
| Symbol | Dimension | Min (mm) | Max (mm) | Source |
| A | Overall height | 2.35 | 2.65 | onsemi 751E / Renesas M24.3 |
| A1 | Standoff (seating plane to body) | 0.10 | 0.30 | Renesas M24.3 |
| b | Lead width | 0.33 | 0.51 | Renesas M24.3 |
| c | Lead thickness | 0.23 | 0.32 | onsemi 751E |
| D | Body length | 15.20 | 15.60 | Renesas M24.3 |
| E1 | Body width | 7.40 | 7.60 | onsemi 751E |
| E / H | Lead span (tip to tip) | 10.00 | 10.65 | Renesas M24.3 |
| e | Lead pitch | 1.27 BSC | — | JEDEC MS-013 |
| h | Lead-tip chamfer | 0.25 | 0.75 | onsemi 751E |
| L | Foot length | 0.40 | 1.27 | Renesas M24.3 |
| θ | Lead angle | 0° | 8° | onsemi 751E |
The onsemi Case 751E outline gives A 2.35–2.65 mm, b 0.35–0.49 mm, D 15.25–15.54 mm, E1 7.40–7.60 mm, pitch 1.27 mm BSC, and a lead span of 10.30 mm BSC. The Renesas M24.3 outline, also compliant to MS-013-AD, lists D 15.20–15.60 mm, E 7.40–7.60 mm, H 10.00–10.65 mm, A1 0.10–0.30 mm, and L 0.40–1.27 mm. Use the nominal lead span of 10.3 mm as your land-pattern anchor.
The IPC-7351B generated land-pattern name computes from these values (1.27 mm pitch, 10.30 mm span, 2.65 mm height, 24 leads, no thermal pad) as SOIC127P1030X265-24N. That string is what most ECAD libraries assign, and matching it is the fastest way to confirm a downloaded footprint is the right variant.
SOIC-24 pinout and pin-1 identification
There is no universal SOIC-24 pinout. Pin functions belong to the specific IC, so a 16:1 multiplexer and a line driver in the same body share nothing but geometry. What is universal is the numbering rule, inherited from DIP: with the pin-1 marker at the upper left, pin 1 is top-left, numbering runs down the left side to pin 12, then continues at pin 13 bottom-right and runs up the right side to pin 24.
Pin 1 is flagged three ways, and a part may use more than one: a molded dot or dimple over pin 1, a notch or half-moon on the pin-1 end, and sometimes a beveled edge along the pin-1 side. Trust the printed dot on the assembled board, then confirm against the datasheet — silk-screen and package markers occasionally disagree, and reversed placement is the most common SOIC assembly return.
SOIC-24 land pattern and stencil
Two manufacturers publish concrete SOIC-24 footprints. They differ, and both work; the wider TI toe extension buys inspection margin, the tighter onsemi pad saves room.
| Parameter | onsemi (Case 751E footprint) | TI (DW land pattern) |
| Pad length | 1.62 mm | 2.00 mm |
| Pad width | 0.52 mm | 0.60 mm |
| Pitch | 1.27 mm | 1.27 mm |
| Row center-to-center | ≈ 9.4 mm (11.00 mm outer span) | 9.30 mm |
The onsemi recommended footprint uses 24 pads of 1.62 mm × 0.52 mm on 1.27 mm pitch with an 11.00 mm overall span. TI’s DW family land pattern uses pads of 2.0 mm × 0.6 mm on 1.27 mm pitch with a 9.30 mm row center spacing.
To derive your own from IPC-7351, take the nominal tip-to-tip span (10.30 mm) and reduce by half the foot length on each side to set the land center-to-center; keep pad width near 60% of the lead pitch, and add heel and toe extensions for the solder fillet. A density-B (nominal) result lands close to the two vendor patterns above. For the stencil, start from a 0.125 mm foil with apertures at 1:1 to the copper pad; drop to a ~90% area ratio only if you see bridging on the 0.5 mm-wide leads.
[IMAGE 2: SOIC-24 recommended land pattern with 24 pads, dimensioned pad length, width, pitch and row spacing | alt: “SOIC-24 land pattern footprint with 1.27 mm pitch and 9.3 mm row spacing”]
Thermal, moisture and compliance
The wide body is not only mechanical margin; it moves heat. Analog Devices lists the 24-lead wide SOIC (its SW code) at θJC ≈ 23 °C/W and θJA ≈ 60 °C/W on a JEDEC 4-layer board, versus about 88 °C/W for a same-count 5.3 mm SSOP and higher still for narrow small-outline parts. For a part dissipating 200 mW at 70 °C ambient, 60 °C/W puts the junction near 82 °C — comfortable margin to a 125 °C or 150 °C limit. Copper pour under and around the leads is what realizes that number; on 2-layer board with thin traces, expect meaningfully worse.
Moisture sensitivity is per IPC/JEDEC J-STD-020, and it is device-specific, not fixed by the outline — check each datasheet for the MSL rating and observe the floor life in J-STD-033 before reflow. Plastic SOIC-24 parts are RoHS and REACH compliant when marked lead-free (the “G” or Pb-free indicator on the package), and automotive-grade variants add AEC-Q100 qualification. Do not assume the marking; verify it on the reel or datasheet for the exact orderable part number.
Choosing and sourcing an SOIC-24 part
SOIC-24 is a mature, low-risk package with deep multi-vendor supply. A representative part, the 16:1 analog multiplexer CD74HC4067M, ships in this body at roughly $0.67 in single quantity, dropping toward $0.32 in thousands, with several thousand in stock and a -55 °C to +125 °C rating. That is typical: standard logic, mux, driver, and interface functions all populate the 24-SOIC.
Two sourcing points earn their place. First, lifecycle favors the surface-mount body — the 24-DIP version of that same mux is obsolete while the 24-SOIC stays active, a pattern that repeats across legacy logic, so design in SOIC rather than DIP for longevity. Second, because “SOIC-24” spans registered outlines that are all MS-013-AD, second-sourcing across onsemi, TI, ADI, Renesas, and NXP is straightforward on geometry; the risk is electrical spec drift between vendors, not footprint mismatch. Confirm the pin-1 marking method and the MSL of each source before you approve an alternate.
FAQ
What is a SOIC-24 package?
A SOIC-24 is a 24-lead wide-body small outline IC: a surface-mount package with two rows of twelve gull-wing leads on 1.27 mm pitch, a 7.5 mm body, and a 2.65 mm maximum height, registered as JEDEC MS-013-AD. It is used for logic, mux, driver, and interface ICs needing more than 20 pins.
Is SOIC-24 wide or narrow body?
Always wide. The narrow 3.9 mm SOIC family (JEDEC MS-012) stops at 16 leads, so a 24-lead SOIC is the wide 7.5 mm (0.300 in) MS-013 body every time. If a datasheet shows a 24-lead SOIC, it is the wide variant.
What is the pitch of a SOIC-24?
The lead pitch is 1.27 mm (0.050 in), the standard SOIC spacing. This gives twelve leads per side across a body about 15.4 mm long. The pitch is fixed by MS-013 and is the same for every SOIC lead count.
What are the SOIC-24 land pattern dimensions?
A typical footprint uses 24 pads near 1.6–2.0 mm long by 0.5–0.6 mm wide on 1.27 mm pitch, with the two rows centered about 9.3 mm apart. onsemi and TI publish patterns within that range; both solder reliably.
What is the difference between SOIC and SOP?
Both are gull-wing small-outline packages. Vendors typically reserve SOIC for the JEDEC 3.9 mm and 7.5 mm bodies and use SOP for the 5.3 mm EIAJ body. The bodies are not interchangeable, so match the registered outline, not just the name.
What is the thermal resistance of a SOIC-24?
About 60 °C/W junction-to-ambient and roughly 23 °C/W junction-to-case on a 4-layer JEDEC board, per Analog Devices’ data. The wide body dissipates better than shrink packages of the same lead count. Copper pour and vias improve the real figure.
Bottom line
Choose SOIC-24 when a part needs 17 to 24 pins, hand-inspectable solder fillets, and long-term availability, and you can spend roughly 15.4 mm × 7.5 mm of board. Anchor your footprint to the 10.3 mm nominal lead span and MS-013-AD, pull a vendor land pattern rather than improvising, and pour copper if the part dissipates more than a few hundred milliwatts. If the pin count drops to 16 or below and board area is tight, step to narrow SOIC or SSOP instead; if it climbs past 24 or heat rises, move to a wide SSOP or an exposed-pad body.
