A SOIC-16W package has a 7.50 mm body, a 9.97 to 10.63 mm lead span and a 2.65 mm maximum height, registered under JEDEC MS-013. It is 92% wider than the narrow SOIC-16 and costs about 24% more for the same die. The reason to accept that penalty is the isolation path across the package. The standard IPC footprint hands 0.8 mm of that path straight back.
Key Takeaways
- Body is 7.50 mm × 10.30 mm nominal, span 9.97 to 10.63 mm, height 2.65 mm max, pitch 1.27 mm.
- Board-level creepage equals pad row spacing minus pad length. TI’s nominal SOIC-16W footprint gives 7.30 mm; its high-voltage option gives 8.10 mm for 0.10 mm more board width.
- A reinforced SOIC-16W isolator carries more than 8 mm of creepage and clearance, 5,000 V rms per UL 1577, and 12.8 kV peak surge withstand.
- Thermal resistance is 83.4 °C/W for the wide body against 109 °C/W for the same die in a 16-pin QSOP.
- Wide-body isolators ship as MSL 2 with a one-year floor life, not MSL 1 unlimited.
- The same shift register costs $0.278 against $0.225 at reel quantity in the wide body, and stocks about 20 times shallower.
What a SOIC-16W Package Is
A SOIC-16W package is the wide-body member of the JEDEC MS-013 small-outline family: 16 gull-wing leads on 1.27 mm pitch, 7.50 mm nominal body width, 10.30 mm nominal body length, and 2.65 mm maximum height. Vendors also call it SOIC-WB, SO-16W, RW-16, or SOP2-16 300 mil body.
MS-013 is registered as the very thick profile plastic small outline family at 1.27 mm pitch and 7.50 mm body width. That phrase matters. The wide body is not only wider than the narrow MS-012 outline, it is 0.90 mm taller, which decides whether the part clears a chassis or a stacked board.
Suffix letters are the fastest identifier once you know them. Texas Instruments uses DW. Analog Devices uses RW-16. NXP registers SOT-162-1. None of these appear in a BOM line that reads only 16-SOIC, which is where footprint errors start.
[IMAGE 1: SOIC-16W and narrow SOIC-16 outlines overlaid at the same scale with body width and lead span called out | alt: “SOIC-16W package wide body dimensions compared with narrow SOIC-16”]
SOIC-16W Dimensions
Values below are read from Texas Instruments package drawing 4221009/B for DW0016B, which references JEDEC MS-013. The narrow column is included only as a reference point.
| Dimension | SOIC-16W (JEDEC MS-013) | Narrow SOIC-16 (MS-012 AC), reference |
| Body width, E1 | 7.40 – 7.60 mm | 3.80 – 4.00 mm |
| Body length, D | 10.10 – 10.50 mm | 9.80 – 10.00 mm |
| Lead span, E | 9.97 – 10.63 mm | 5.80 – 6.20 mm |
| Height, A (max) | 2.65 mm | 1.75 mm |
| Standoff, A1 | 0.10 – 0.30 mm | 0.10 – 0.25 mm |
| Lead pitch, e | 1.27 mm | 1.27 mm BSC |
| Lead width, b | 0.31 – 0.51 mm | 0.33 – 0.51 mm |
| Lead thickness, c | 0.10 – 0.33 mm | 0.19 – 0.25 mm |
| Foot length, L | 0.40 – 1.27 mm | 0.41 mm min |
| Pin 1 to pin 8 centres | 8.89 mm typ | 8.89 mm typ |
| Lead angle | 0° – 8° | 0° – 8° |
| Mold flash allowance | ≤ 0.15 mm per side | ≤ 0.15 mm per side |
| Vendor codes seen | TI DW, ADI RW-16, NXP SOT-162-1 | TI D, ADI R-16, NXP SO16 |
| Source drawing | TI 4221009/B (DW0016B) | MPS MF-PO-D-00035 rev 0.0 |
Two numbers drive most design work. Lead span at 9.97 to 10.63 mm sets the land pattern. Body width at 7.40 to 7.60 mm sets how much silicon and how much internal isolation distance the package can hold.
The Footprint Decision That Costs You Creepage
Package creepage and board creepage are different quantities, and the smaller of the two wins. TI publishes both footprints on the same DW0016B drawing and annotates each with the resulting distance.
| Land pattern parameter | IPC-7351 nominal | HV / isolation option |
| Pad row spacing (centre to centre) | 9.30 mm | 9.75 mm |
| Pad size | 2.00 mm × 0.60 mm | 1.65 mm × 0.60 mm |
| Pad pitch | 1.27 mm × 14 spaces | 1.27 mm × 14 spaces |
| Gap between pad rows (board creepage) | 7.30 mm | 8.10 mm |
| Copper envelope | 11.30 × 9.49 mm ≈ 107 mm² | 11.40 × 9.49 mm ≈ 108 mm² |
| Solder mask relief | 0.07 mm all round, NSMD | 0.07 mm all round, NSMD |
| Stencil | 0.125 mm, 1:1 aperture | 0.125 mm, 1:1 aperture |
| Specify it for | Logic, transceivers, memory | Basic or reinforced isolation |
| Source drawing | TI 4221009/B | TI 4221009/B |
The rule behind those annotations is arithmetic. Board-level creepage across the barrier equals pad row spacing minus pad length. For the nominal pattern, 9.30 mm minus 2.00 mm is 7.30 mm. For the high-voltage option, 9.75 mm minus 1.65 mm is 8.10 mm. Both match TI’s own labels.
Now compare that with the package. The ISO7741 datasheet specifies external creepage and clearance greater than 8 mm for the DW-16 package. Drop that part onto the nominal IPC footprint and the copper, not the plastic, becomes the limiting path at 7.30 mm.
The cost of fixing it is close to zero. Copper envelope grows from 11.30 mm × 9.49 mm to 11.40 mm × 9.49 mm, roughly 107 mm² to 108 mm². You buy 0.80 mm of creepage for 0.10 mm of board width.
Both vendors warn about this in the same words. TI’s insulation table notes that a board design must not let the mounting pads reduce the creepage and clearance distance. Analog Devices repeats the point in its isolator datasheets.
A third data point shows how much footprints vary. A published CAD library geometry for the SO16W package, built from Micron’s TN-1225 land pattern note for NOR flash, specifies 0.64 mm × 2.50 mm pads on 9.20 mm centres, leaving 6.70 mm between pad inner edges. That is fine for a memory device and unusable under a reinforced isolator.
[IMAGE 2: Nominal and high-voltage SOIC-16W land patterns side by side with the inner-edge gap dimensioned | alt: “SOIC-16W land pattern nominal versus high voltage isolation option creepage”]
What Isolation a SOIC-16W Actually Buys
The wide body exists because a longer surface path across the package supports a higher working voltage. Here is what one reinforced part delivers, with a 16-pin QSOP holding the same die alongside.
| Insulation parameter (ISO7741) | SOIC-16W (DW-16) | QSOP-16 (DBQ-16) |
| External clearance, CLR | > 8 mm | > 3.7 mm |
| External creepage, CPG | > 8 mm | > 3.7 mm |
| Distance through insulation, DTI | > 17 µm | > 17 µm |
| Comparative tracking index, CTI | > 600 V | > 600 V |
| Material group per IEC 60664-1 | I | I |
| Working isolation voltage, VIOWM | 1,500 V rms | 400 V rms |
| Max repetitive peak, VIORM | 2,121 V peak | 566 V peak |
| Transient isolation, VIOTM | 8,000 V peak | 4,242 V peak |
| Surge isolation, VIOSM | 12,800 V peak | 10,000 V peak |
| Withstand per UL 1577, VISO | 5,000 V rms | 3,000 V rms |
| Overvoltage category, mains ≤ 600 V rms | I – IV | Not applicable |
Read the working voltage line carefully. UL 1577 gives 5,000 V rms, but that is a one-minute withstand test, not a level you design to. The working isolation voltage is 1,500 V rms, and TI’s time-dependent dielectric breakdown data projects 36 years of insulation lifetime at that level.
Thermal Headroom and Safety Limiting Values
| Thermal and safety metric (ISO7741) | SOIC-16W (DW-16) | QSOP-16 (DBQ-16) |
| RθJA, junction to ambient | 83.4 °C/W | 109 °C/W |
| RθJC(top), junction to case | 46 °C/W | 54.4 °C/W |
| RθJB, junction to board | 48 °C/W | 51.9 °C/W |
| ψJT, junction to top | 19.1 °C/W | 14.2 °C/W |
| ψJB, junction to board | 47.5 °C/W | 51.4 °C/W |
| Safety limiting power, PS at 25 °C ambient | 1,499 mW | 1,147 mW |
| Safety limiting current at 5.5 V | 273 mA | 209 mA |
| Safety limiting current at 2.75 V | 545 mA | 417 mA |
| Maximum safety temperature, TS | 150 °C | 150 °C |
The wide body runs cooler than the QSOP by 25.6 °C/W. That gap sets the safety limiting values, which are the numbers a safety agency actually looks at.
Work the arithmetic. TI rates the ISO774x junction temperature at 150 °C. At 25 °C ambient, allowable dissipation is (150 − 25) / 83.4 = 1.50 W, and the datasheet’s safety limiting power for the DW-16 is 1,499 mW. The same calculation for the QSOP gives 1.15 W against a published 1,147 mW.
At real ambient temperatures the headroom shrinks fast. At 85 °C the DW-16 allows 0.78 W; at 125 °C it allows 0.30 W. Safety limiting current follows supply voltage: 273 mA at 5.5 V, 416 mA at 3.6 V, and 545 mA at 2.75 V, all at 25 °C ambient.
When 8 mm Is Not Enough
Two escape routes exist before you resort to two isolators in series.
The first is an extended-body 16-lead SOIC. Analog Devices lengthens the standard package by 2.5 mm to reach 8.3 mm of creepage and clearance, and states that the pinout and the recommended pad layout stay identical, so an existing board accepts the longer part.
The second is TI’s ultra-wide DWW. A TI applications engineer confirms roughly 14 mm of creepage and clearance for the ISO7840 in DWW against roughly 8 mm for the DW body. In the automotive ISO774x-Q1 family, DWW is rated 5,700 V rms per UL 1577 against 5,000 V rms for DW.
Neither is a drop-in for the standard SOIC-16W footprint. Both change the body length, and DWW changes the land pattern.
Assembly and Handling
Moisture sensitivity is the first surprise for teams moving up from narrow-body logic. TI ships the ISO7741DWR as Level-2-260C-1 YEAR. Narrow-body logic such as the SN74AHC595 in SOIC is Level-1-260C-UNLIM. Level 2 means a one-year floor life in the factory environment once the dry pack is opened, and a bake before reflow if that clock has run out.
Tape and reel differs too. TI ships the DW-16 at 2,000 pieces on a 330 mm reel in 16 mm tape, with pocket A0 10.75 mm, B0 10.70 mm, K0 2.70 mm and a 12.0 mm pitch. The narrow SOIC-16 ships 2,500 pieces at 8.0 mm pitch. The wide-body reel therefore holds 20% fewer parts on 24 m of tape instead of 20 m, which changes reel-change frequency on a high-volume line.
Stencil design is unchanged from the narrow body: 0.125 mm foil, apertures 1:1 with the pads, non-solder-mask-defined lands with 0.07 mm relief.
The Cost and Availability Penalty
The cleanest comparison is one device in both bodies. On Digi-Key, the TI SN74HC595DR in 16-SOIC (0.154 in, 3.90 mm width) lists at $0.51 in ones and $0.22454 on a 2,500-piece reel, with 64,639 in stock. The SN74HC595DWR in 16-SOIC (0.295 in, 7.50 mm width) lists at $0.61 in ones and $0.27759 on a 2,000-piece reel, with 3,115 in stock.
That is a 24% premium at reel quantity and roughly one twentieth of the inventory depth. Factory lead time runs the other way, 6 weeks for the wide part against 12 weeks for the narrow one, which reflects demand rather than difficulty.
Lifecycle risk sits with tube-packed wide-body parts. Digi-Key lists the tube-packed SN74HC595DW as obsolete while the tape-and-reel SN74HC595DWR stays active. If a design still calls out a tube part number, change it now.
Use the Package / Case field when sourcing. Digi-Key separates 16-SOIC (0.154 in, 3.90 mm width) from 16-SOIC (0.295 in, 7.50 mm width), and also carries a 16-SOIC (0.220 in, 5.59 mm width) category for medium-body parts that belong to neither JEDEC outline. The Supplier Device Package field shows only 16-SOIC for all three.
[IMAGE 3: Decision path from creepage requirement to nominal footprint, high-voltage footprint, extended body or DWW | alt: “SOIC-16W package selection decision path by creepage requirement”]
Four Mistakes Specific to the Wide Body
Inheriting the narrow footprint. Row spacing goes from 5.40 mm to 9.30 mm. A wide-body part on a narrow-body pattern sits on solder mask.
Using the nominal footprint under a reinforced isolator. It caps board creepage at 7.30 mm even though the package offers more than 8 mm.
Routing under the barrier. Traces, vias and copper pours between the two pad rows shorten the same path the footprint was widened to protect.
Treating MSL 2 as MSL 1. Wide-body isolators need dry-pack discipline and a bake schedule that narrow-body logic does not.
Frequently Asked Questions
What are SOIC-16W dimensions?
Body is 10.10 to 10.50 mm long and 7.40 to 7.60 mm wide, with a lead span of 9.97 to 10.63 mm and a maximum height of 2.65 mm. Lead pitch is 1.27 mm, lead width 0.31 to 0.51 mm, and standoff 0.10 to 0.30 mm, per TI drawing 4221009/B.
What is the difference between SOIC-16 and SOIC-16W?
Body width and lead span. The narrow SOIC-16 is 3.90 mm wide with a 6.00 mm span under JEDEC MS-012; the SOIC-16W is 7.50 mm wide with a 10.30 mm span under MS-013. The wide body is also 0.90 mm taller and needs a completely different land pattern.
What is the SOIC-16W land pattern?
TI’s nominal pattern uses 2.00 mm × 0.60 mm pads on 9.30 mm row spacing at 1.27 mm pitch. The high-voltage alternative on the same drawing uses 1.65 mm × 0.60 mm pads on 9.75 mm row spacing, which preserves 8.10 mm of board creepage instead of 7.30 mm.
Is SOIC-16W the same as SOP-16?
No. SOP-16 usually means the JEITA body at about 5.3 mm width, which sits between the two JEDEC outlines and matches neither footprint. Distributors carry it under a separate 5.59 mm width category. Check the mechanical drawing rather than the package abbreviation.
Why do digital isolators use SOIC-16W?
The longer surface path across a 7.50 mm body supports reinforced insulation. A DW-16 isolator reaches more than 8 mm of creepage and clearance and 5,000 V rms per UL 1577, against 3.7 mm and 3,000 V rms for the same die in a 16-pin QSOP.
Which SOIC-16W Footprint to Release
If the part is ordinary logic, a transceiver or a memory, use the nominal pattern. Row spacing 9.30 mm, pads 2.00 mm × 0.60 mm, and stop there.
If the part crosses a safety barrier, start from the creepage your standard demands, then work backwards through the arithmetic. Subtract your pad length from your row spacing and confirm the result clears that requirement before you route anything between the rows.
If the requirement lands above 8.10 mm, the footprint cannot save you. Move to an extended-body 16-lead SOIC at 8.3 mm, or to an ultra-wide DWW at roughly 14 mm, and re-check the body length against your placement keep-out.
