The SOIC-16 package is not one package. Three incompatible outlines share the name: a 3.90 mm narrow body registered as JEDEC MS-012 variation AC, a 7.50 mm wide body under MS-013, and a stretched 12.75 mm long body used for reinforced isolation. Their land patterns differ by 3.9 mm in row spacing. Place the wrong one and eight leads land on bare solder mask. Below are the verified numbers for all three.

Key Takeaways

• Narrow SOIC-16 body is 3.90 mm × 9.90 mm with a 6.00 mm lead span; wide is 7.50 mm × 10.30 mm with a 10.30 mm span.
• Lead pitch is 1.27 mm on every variant. Pitch alone never identifies which one you have.
• Land pattern row spacing is 5.40 mm narrow and 9.30 mm wide. The footprints are not interchangeable.
• The wide body consumes roughly 61% more copper area than the narrow body for the same 16 pins.
• A JEDEC 16-lead SOIC gives about 7.6 mm of creepage; the extended-body version reaches 8.3 mm on the same pad layout.
• Distributor filters separate the two by body width, not by pin count. Check that field before ordering.

What the SOIC-16 Package Actually Is

A SOIC-16 package is a 16-lead gull-wing plastic surface-mount package on 1.27 mm pitch, with eight leads per long side. JEDEC registers two body widths under the name: 3.90 mm narrow (MS-012 variation AC) and 7.50 mm wide (MS-013). Body length is 9.90 mm narrow, 10.30 mm wide.

Vendors label the same outlines differently. Texas Instruments uses suffix D for narrow and DW for wide. Analog Devices uses R-16 and RW-16. NXP and Nexperia use SO16. Onsemi writes SOIC16. None of these letters tell you the body width without opening the mechanical drawing.

One trap deserves its own sentence. EIAJ, now JEITA, defines a 5.3 mm body width package that many catalogs also list as SOIC. The standard package reference notes that EIAJ Type II is 5.3 mm wide and both slightly thicker and longer than JEDEC MS-012. A 5.3 mm part dropped onto a 3.9 mm footprint puts the lead toes past the pad ends, and the joints look acceptable on X-ray until thermal cycling opens them.

[IMAGE 1: Three SOIC-16 outlines drawn to the same scale showing 3.90 mm, 7.50 mm and 12.75 mm bodies | alt: “SOIC-16 package narrow, wide and extended body outlines compared to scale”]

SOIC-16 Dimensions: Narrow, Wide and Extended Body

Every value below comes from a manufacturer package outline drawing, not from a summary table.

Dimension	SOIC-16 narrow (MS-012 AC)	SOIC-16 wide (MS-013)	SOIC-16 extended body
Body width, E1	3.80 – 4.00 mm	7.40 – 7.60 mm	7.40 – 7.60 mm
Body length, D	9.80 – 10.00 mm	10.10 – 10.50 mm	12.65 – 12.95 mm
Lead span, E	5.80 – 6.20 mm	9.97 – 10.63 mm	10.05 – 10.55 mm
Height, A (max)	1.75 mm	2.65 mm	2.64 mm
Standoff, A1	0.10 – 0.25 mm	0.10 – 0.30 mm	0.10 – 0.25 mm
Lead pitch, e	1.27 mm BSC	1.27 mm BSC	1.27 mm BSC
Lead width, b	0.33 – 0.51 mm	0.31 – 0.51 mm	0.35 – 0.49 mm
Lead thickness, c	0.19 – 0.25 mm	0.10 – 0.33 mm	0.23 – 0.33 mm
Foot length, L	0.41 mm min	0.40 – 1.27 mm	0.41 – 1.27 mm
Lead angle	0° – 8°	0° – 8°	0° – 8°
JEDEC reference	MS-012, variation AC	MS-013	MS-013 AC outline
Vendor codes seen	TI D, ADI R-16, NXP SO16	TI DW, ADI RW-16	ADI RI-16-2 (SOIC_IC)
Source drawing	MPS MF-PO-D-00035 rev 0.0	TI 4220721/A (DW0016A)	ADI 12-13-2017-B

The narrow-body values are from Monolithic Power Systems drawing MF-PO-D-00035, which states conformance to JEDEC MS-012 variation AC. The wide-body values are from Texas Instruments drawing 4220721/A for DW0016A, referencing MS-013. The extended-body values are from Analog Devices drawing RI-16-2.

Note what the third column does. It keeps the 7.50 mm body width and the same lead span, then stretches the body 2.45 mm longer. Pin locations do not move.

SOIC-16 Pinout and Pin 1 Identification

Pin numbering follows the DIP convention it replaced. Viewed from the top, pin 1 sits at the upper left, pins 1 through 8 run down the left side, and pins 9 through 16 run up the right side. Pin 8 faces pin 9 across the short end.

The package does not assign function to pin number. On the TI SN74AHC595 shift register, pin 8 is GND and pin 16 is VCC. On a quad digital isolator in the same 16-lead outline, pins 1 and 8 belong to one supply domain and pins 9 and 16 to the other. Always read the device pin table.

Three pin 1 markers appear in the field: a molded dot in the corner, a half-moon notch on the short end, and a beveled edge running along the pin 1 side. Microchip’s SOIC drawings state the chamfer is optional, and that a dot, an embedded metal marker or a printed indicator must appear in the index area if it is absent.

The mirroring mistake costs a board spin. Library footprints are drawn as viewed from the component side. Copy pin coordinates from a bottom-view assembly drawing without flipping them and pin 1 lands where pin 8 should be, with the supply reversed on power-up.

[IMAGE 2: Top view of a SOIC-16 showing the pin 1 index area, numbering direction and the three pin 1 marker styles | alt: “SOIC-16 pinout numbering and pin 1 identification markers”]

SOIC-16 Land Pattern and Stencil Design

The two land patterns share a pitch and nothing else.

Land pattern parameter	SOIC-16 narrow	SOIC-16 wide
Row spacing (pad centre to pad centre, across)	5.40 mm	9.30 mm
Pad length	1.60 mm	2.00 mm
Pad width	0.61 mm	0.60 mm
Pad pitch	1.27 mm × 14 spaces	1.27 mm × 14 spaces
Copper envelope	7.00 mm × 9.50 mm ≈ 66.5 mm²	11.30 mm × 9.49 mm ≈ 107 mm²
Solder mask relief	0.07 mm all round, NSMD	0.07 mm all round, NSMD
Stencil	0.125 mm, 1:1 aperture	0.125 mm, 1:1 aperture
IPC-7351B pattern name	SOIC127P600X175-16N	SOIC127P1030X265-16N
Source drawing	MPS MF-PO-D-00035	TI 4220721/A

Copper envelope is the outer rectangle enclosing all 16 pads: row spacing plus one pad length across, and seven pitches plus one pad width along. On those numbers the wide body consumes 107 mm² against 66.5 mm² for the narrow body, a 61% increase for the same pin count.

IPC-7351B builds land pattern names from family, pitch, lead span, height and pin count, so the narrow footprint reads SOIC127P600X175-16N and the wide one SOIC127P1030X265-16N. The trailing letter is the density level: N for nominal, M for most, L for least. Use nominal for reflow production and most when the board will be hand-reworked.

Older libraries built to IPC-SM-782 are dimensionally different, not merely older. Skyworks application note 200123M specifies 2.20 mm × 0.60 mm pads on 5.20 mm row spacing for the 16-lead narrow body, against 1.60 mm × 0.61 mm on 5.40 mm from the MPS drawing. Both work. Mixing pad length from one with row spacing from the other does not.

Keep the pads non-solder-mask-defined. TI’s drawing allows 0.07 mm of mask clearance all round on the narrow body and specifies a 0.125 mm stencil with 1:1 apertures.

Thermal Reality: What a SOIC-16 Can Dissipate

Thermal resistance for a SOIC-16 is a property of the package, the die and the test board together. The clean comparison is one device offered in several 16-pin packages. The TI SN74AHC595 datasheet, revision N of July 2024, gives exactly that.

Thermal metric (°C/W)	SOIC-16 D	SSOP-16 DB	TSSOP-16 PW	WQFN-16 BQB	PDIP-16 N
RθJA, junction to ambient	93.8	97.8	135.9	91.8	47.8
RθJC(top), junction to case	54.7	48.1	70.3	87.7	35.1
RθJB, junction to board	50.9	48.5	81.3	61.6	27.8
ψJT, junction to top	20.8	10.0	22.5	11.9	20.1
ψJB, junction to board	50.7	47.9	80.8	61.4	27.7

Two results stand out. The narrow SOIC-16 is worse than a 16-pin PDIP by a factor of two, because a through-hole leadframe carries heat into the board. And the SOIC-16 beats a TSSOP-16 by 42 °C/W, which is the real reason a half-watt part stays in SOIC when board area is tight.

A worked example. TI rates the SN74AHC595 junction temperature at 150 °C maximum. At 85 °C ambient the narrow SOIC-16 allows (150 − 85) / 93.8 = 0.69 W. At 125 °C ambient it allows only 0.27 W.

Treat that number as a package comparison, not a system prediction. TI’s application report SPRA953 states that RθJA is measured on a specific test coupon and is the most frequently misused thermal metric. For a junction temperature estimate on your own board, use ψJB, which is 50.7 °C/W here, together with a measured board temperature.

When the Extended-Body SOIC-16 Is Mandatory

Reinforced isolation is decided by creepage, and creepage is decided by body length. The Analog Devices FAQ on its certified 8 mm creepage package states that a JEDEC standard 16-lead SOIC provides 7.6 mm of creepage measured around the end of the package, short of the requirement for 220 V to 250 V ac medical equipment. Extending the body by 2.5 mm raises both creepage and clearance to 8.3 mm.

The useful part for a layout engineer: ADI states the pinout and the recommended pad layout are identical to the standard package, so an existing board accepts the longer part. The one thing to check is whether other components sit close to the package ends, which is where the isolation barrier lives.

SOIC-16 Against the Other 16-Pin Options

Package, 16 pins	Body size	Pitch	Land pattern copper	RθJA (°C/W)	Where it wins
SOIC-16 narrow	3.90 × 9.90 mm	1.27 mm	≈ 66.5 mm²	93.8	Default choice; hand-solderable
SOIC-16 wide	7.50 × 10.30 mm	1.27 mm	≈ 107 mm²	Not published for this die	Large die, isolation barrier
SSOP-16	5.30 × 6.20 mm	0.65 mm	≈ 44 mm²	97.8	Area saving, reflow only
TSSOP-16	4.40 × 5.00 mm	0.65 mm	≈ 36.5 mm²	135.9	Smallest leaded option
WQFN-16	2.50 × 3.50 mm	0.50 mm	Leadless, see drawing	91.8	Smallest; needs AOI or X-ray
PDIP-16	6.35 × 19.31 mm	2.54 mm	Through-hole	47.8	Prototyping, sockets, best cooling

Copper area figures use each drawing’s own recommended land pattern, computed the same way as above. The SSOP and TSSOP patterns are from TI drawings DB0016A and PW0016A.

Five Mistakes That Cause SOIC-16 Rework

Trusting the pin count. A 16-SOIC line in a BOM is ambiguous by 3.9 mm of row spacing. Resolve it against the mechanical drawing before footprint release.

Assuming SOP-16 is a synonym. The 5.3 mm EIAJ body sits between the two JEDEC widths and matches neither footprint.

Sizing heat with RθJA. It describes a JEDEC test board. Use ψJB and a measured board temperature instead.

Ignoring coplanarity after rework. MPS specifies 0.10 mm maximum lead coplanarity after forming. A part straightened by hand rarely holds that, and the resulting joint passes electrical test and fails vibration.

Skipping the moisture-sensitivity check. TI ships the SN74AHC595 SOIC-16 as MSL 1 with a 260 °C peak reflow rating, so no bake is needed. Not every SOIC-16 is MSL 1, and a floor-life violation shows up as delamination rather than as an open.

Cost, Availability and Second Sourcing

The narrow body is a commodity; the wide body is not. On Digi-Key, the TI SN74HC259DR in 16-SOIC (0.154 in, 3.90 mm width) lists at $0.60 in ones and $0.2693 on a 2,500-piece reel, with 8,837 in stock against a 12-week factory lead time. The ADuM1401BRWZ-RL in 16-SOIC (0.295 in, 7.50 mm width) lists at $7.88 in ones and $4.67 at 1,000, with 1,281 in stock and a 13-week lead time.

Use the distributor’s Package / Case field as the filter. It separates 16-SOIC (0.154 in, 3.90 mm width) from 16-SOIC (0.295 in, 7.50 mm width) directly, which the Supplier Device Package field, showing only 16-SOIC, does not.

For the narrow body, second sources are genuinely available: the 74HC595 in SO16 or SOIC16 ships from TI, Nexperia, Toshiba and onsemi. Isolators in the wide body are usually single-sourced on pinout, so qualify a second part early rather than at shortage time.

Reel logistics are worth one line. TI ships the 16-lead narrow SOIC on a 330 mm reel in 16 mm tape, 2,500 pieces, pocket A0 6.5 mm, B0 10.3 mm, K0 2.1 mm, pitch 8.0 mm, pin 1 in quadrant Q1.

[IMAGE 3: Narrow and wide SOIC-16 land patterns overlaid with row spacing and pad dimensions | alt: “SOIC-16 land pattern dimensions for narrow and wide body footprints”]

Frequently Asked Questions

What is the size of a SOIC-16 package?

A narrow SOIC-16 body measures 3.90 mm × 9.90 mm nominal, 1.75 mm maximum tall, with a 6.00 mm lead span. A wide SOIC-16 body measures 7.50 mm × 10.30 mm, 2.65 mm maximum tall, with a 10.30 mm span. Both use 1.27 mm lead pitch.

What is the pin pitch of a SOIC-16?

1.27 mm, equal to 0.050 inches, on every JEDEC SOIC-16 variant. That pitch is roughly twice a TSSOP’s 0.65 mm, which is why SOIC tolerates wider paste-printing variation and stays practical to hand solder.

Is SOIC-16 the same as SOP-16?

Not reliably. TI and Fairchild use SOIC for the JEDEC 3.9 mm and 7.5 mm widths and SOP for the EIAJ 5.3 mm width. Other vendors use the terms loosely. Treat SOP-16 as a different footprint until the drawing says otherwise.

Can you hand solder a SOIC-16?

Yes. The 1.27 mm pitch and exposed gull-wing toes suit drag soldering with flux and wick. Choose the IPC-7351B most density land pattern rather than nominal if the board is built or reworked by hand, since the longer pads leave room for the iron tip.

What is the difference between SOIC-16 and SOIC-16W?

Body width and lead span. SOIC-16 narrow is 3.90 mm wide with a 6.00 mm span; SOIC-16W is 7.50 mm wide with a 10.30 mm span. The W variant exists to fit larger die and to widen the creepage path across the package, which matters for isolators.

Which SOIC-16 to Specify

Default to the narrow body. It is cheaper, smaller, better cooled than a TSSOP, and second-sourced across four vendors.

Move to the wide body only when the die does not fit, or when the datasheet’s isolation rating depends on it. Move to the extended 12.75 mm body when a safety standard demands more than 7.6 mm of creepage; the pad layout does not change, so that decision can be made late.

Before release, open the mechanical drawing and confirm three numbers: body width, lead span, and recommended row spacing. If those three agree with your library footprint, the rest of the SOIC-16 package specification takes care of itself.

[IMAGE 4: Decision flow from pin count to narrow, wide or extended-body SOIC-16 | alt: “SOIC-16 package selection decision path for narrow wide and extended body”]