HTSSOP-24 is not one footprint. Texas Instruments publishes three separate 24-pin PowerPAD TSSOP drawings whose solder mask openings run from 2.44 mm × 3.42 mm to 2.4 mm × 5.16 mm. The ROHM HTSSOP-B24 is not even the same body: 5.6 mm wide against 4.4 mm. Lead pattern and thermal land both change with the part number. Read the drawing bound to your device.
Key takeaways
- The 4.4 mm body form is registered as JEDEC MO-153 variation ADT. Renesas and Analog Devices both cite it by name.
- The ROHM HTSSOP-B24 uses a 5.6 mm body on a 7.6 mm lead span. Its lead pattern is not interchangeable with the rest.
- Exposed pad area across published drawings runs from 8.35 mm² to 17.00 mm², a spread of about 2:1.
- All three TI 24-pin drawings share one copper land, 3.4 mm × 7.8 mm, and differ only in the mask opening.
- Stencil tables hold paste volume constant, not aperture area. The three TI drawings sit at 1.04, 1.44 and 1.55 mm³.
- Budget 41.3 °C/W for a 24-pin HTSSOP against 33.8 °C/W for the same die in a 24-pin VQFN.
One name, two body widths
An HTSSOP-24 is a 24-lead thin shrink small outline package with an exposed thermal pad on the underside. The common form is a 7.8 mm × 4.4 mm body, 0.65 mm pitch, 6.4 mm lead span and 1.20 mm maximum height, registered as JEDEC MO-153 variation ADT.
[IMAGE 1: Bottom view of an HTSSOP-24 showing the exposed thermal pad inside the 24 gull-wing leads | alt: “HTSSOP-24 package bottom view showing the exposed thermal pad and 0.65 mm pitch gull-wing leads”]
Renesas states that conformance on M24.173C, and Analog Devices marks its RE-24 drawing compliant to MO-153-ADT. Texas Instruments references MO-153 without naming the variation on its 24-pin PowerPAD drawings.
ROHM sits outside that group. Its 2024 package catalog gives HTSSOP-B24 a body of 7.8 mm × 5.6 mm on a 7.6 mm lead span, at 1.0 mm maximum thickness. That is 1.2 mm wider in body and 1.2 mm wider across the leads than the MO-153 ADT part. Nothing about the lead pattern carries across.
[IMAGE 3: The ROHM 5.6 mm body outline overlaid on the 4.4 mm MO-153 ADT outline at the same scale | alt: “HTSSOP-24 body width comparison, ROHM HTSSOP-B24 against the JEDEC MO-153 ADT outline”]
The divergence is specific to this pin count. ROHM HTSSOP-B20 and HTSSOP-B28 both sit on the 6.4 mm lead span, while B24 and B30 move to 7.6 mm. Checking the pin count against the catalog is not optional.
Three TI drawings, three thermal pads
Texas Instruments has issued at least three enhanced package outline drawings for the 24-pin PowerPAD TSSOP. They share a body, a pitch and a land pattern. They do not share a pad.
| TI drawing | Issued | Solder mask opening (mm) | Pad area (mm²) | Copper land (mm) |
| PWP0024B, 4222709/A | 02/2016 | 2.4 × 5.16 | 12.38 | 3.4 × 7.8 |
| PWP0024M, 4224354/A | 06/2018 | 2.93 × 3.93 | 11.51 | 3.4 × 7.8 |
| PWP0024U, 4230154/A | 10/2023 | 2.44 × 3.42 | 8.35 | 3.4 × 7.8 |
Table 1: The three TI 24-pin PowerPAD TSSOP drawings. Mask opening equals the 0.125 mm stencil aperture on each. Pad area is calculated from the opening.
[IMAGE 2: The three TI 24-pin mask openings drawn concentrically at the same scale | alt: “HTSSOP-24 thermal pad comparison across TI drawings PWP0024B, PWP0024M and PWP0024U”]
Order the three by area and the range is 8.35 mm² to 12.38 mm², a factor of 1.48 inside one supplier. Aspect ratio moves as well. PWP0024B runs a narrow pad more than twice as long as it is wide. PWP0024U is close to square.
The practical consequence is a mask opening that does not match the part. Too small and solder coverage falls below the 50% minimum TI recommends. Too large and the mask no longer defines the joint, which invites bridging toward the inner ends of the lead lands.
Thermal pad across suppliers
| Drawing | Body L × W (mm) | Lead span (mm) | Exposed pad or mask opening (mm) | Area (mm²) |
| TI PWP0024U, 4230154/A | 7.9/7.7 × 4.5/4.3 | 6.6/6.2 | 2.44 × 3.42 max, 1.74 × 2.72 min | 8.35 |
| TI PWP0024M, 4224354/A | 7.9/7.7 × 4.5/4.3 | 6.6/6.2 | 2.93 × 3.93 max, 2.16 × 3.32 min | 11.51 |
| TI PWP0024B, 4222709/A | 4.4 mm body class | not on drawing | 2.4 × 5.16 mask opening | 12.38 |
| Renesas M24.173C, Rev 1, 12/09 | 7.80 ±0.10 × 4.40 ±0.10 | 6.40 | 4.30 ±0.10 × 3.00 ±0.10 | 12.90 |
| ADI FE24 (AA), 05-08-1771 Rev B | 7.90/7.70 × 4.50/4.30 | 6.40 BSC | 3.25 × 2.74 | 8.91 |
| ROHM HTSSOP-B24, 2024 catalog | 7.8 ±0.1 × 5.6 ±0.1 | 7.6 ±0.2 | 3.4 × 5.0 | 17.00 |
Table 2: Exposed pad geometry for 24-lead TSSOP with exposed pad, from published drawings. The ROHM entry sits on a wider body than the rest.
Renesas publishes the largest pad in the MO-153 ADT group at 12.90 mm². The Analog Devices legacy Linear part is the smallest at 8.91 mm². ROHM tops the list at 17.00 mm², though on a wider body that no other drawing here shares.
Note what the tolerance band does. On PWP0024M the pad ranges from 2.16 mm to 2.93 mm on one axis and 3.32 mm to 3.93 mm on the other. The TI rule is to design the solder mask defined pad to the maximum size in the device data sheet, so the maximum is the number you draw.
The land pattern that covers all three
| Source | Lead land L × W (mm) | Row centres (mm) | Thermal land (mm) | Mask treatment |
| TI, all three 24-pin drawings | 1.5 × 0.45 | 5.8 | 3.4 × 7.8 copper | Solder mask defined at the pad |
| Renesas M24.173C | 1.45 × 0.35 | 5.65 | 4.30 × 3.00 | Not stated on drawing |
| ADI FE24 (AA) | 1.05 × 0.45 | 5.55 | 3.25 × 2.74 minimum metal | Not stated on drawing |
Table 3: Recommended land patterns on the 4.4 mm body. Row centres for the ADI entry are derived from its 4.50 mm inner and 6.60 mm outer span.
Lead lands differ less than the pads, and the geometry works out in a useful way. Measured from the package centreline, the TI land runs from 2.15 mm to 3.65 mm. The Renesas land runs 2.20 mm to 3.38 mm. The Analog Devices land runs 2.25 mm to 3.30 mm.
The TI land encloses both of the others. A board drawn to the TI 1.5 mm × 0.45 mm lands on 5.8 mm centres will solder a Renesas or an Analog Devices 24-lead part, with extra toe and heel fillet rather than less. Going the other way, the Analog Devices land is 0.35 mm short at the toe.
That gives a clean rule for a second-sourced design on the 4.4 mm body: draw the lead lands to TI, then set the mask opening from the drawing for the part you actually buy.
Stencil apertures: constant volume, not constant area
Most published exposed pad advice is written for QFNs, which have no standoff and float on excess solder. A gull-wing package does have standoff. TI puts the JEDEC range at 0.05 mm to 0.15 mm for TSSOP and TQFP bodies, and specifies a 1:1 aperture at 0.125 mm on all three 24-pin drawings.
| Stencil thickness (mm) | PWP0024B aperture (mm) | PWP0024M aperture (mm) | PWP0024U aperture (mm) |
| 0.100 | 2.68 × 5.77 | 3.28 × 4.39 | 2.73 × 3.82 |
| 0.125 (shown on drawing) | 2.4 × 5.16 | 2.93 × 3.93 | 2.44 × 3.42 |
| 0.150 | 2.19 × 4.71 | 2.67 × 3.59 | 2.23 × 3.12 |
| 0.175 | 2.03 × 4.36 | 2.48 × 3.32 | 2.06 × 2.89 |
| Paste volume held (mm³) | 1.55 | 1.44 | 1.04 |
Table 4: Thermal pad stencil apertures from the three TI drawings. Thickness and aperture are published. The volume row is calculated from them.
[IMAGE 4: Stencil aperture, solder mask opening and copper land drawn concentrically at 0.125 mm stencil | alt: “HTSSOP-24 stencil aperture of 2.44 mm by 3.42 mm on a 0.125 mm stencil”]
Multiply each aperture by its stencil thickness and the reason for the table appears. PWP0024U holds 1.04 mm³ of paste at every thickness. PWP0024M holds 1.44 mm³. PWP0024B holds 1.55 mm³. TI is specifying volume and letting area follow.
If your assembler runs a thickness that is not on the drawing, interpolate on volume. TI also warns that thinner stencils may need apertures grown further to reach adequate metal fill, and that inadequate fill drives voiding up.
ROHM argues the opposite case for the same package class. It recommends dividing the aperture to vent flux gas and printing 50% to 80% of the exposed pad area. Its own HTSSOP-C48 example prints 52.7%. Treat that as the fallback when x-ray shows voids, not as the starting point.
Thermal vias and mask capping
The TI guidance is numeric. Keep the via drill at 0.33 mm or smaller so the barrel does not wick paste out of the joint. Five to nine vias suit a small die. Never use thermal relief spokes, since a relief is designed to raise thermal resistance.
The 24-pin drawings differ slightly in the via example. PWP0024M shows 0.2 mm vias on a 1.2 mm grid. PWP0024U shows the same via on a 1.0 mm grid. The TPS65270 layout figure calls for 0.010 in. diameter thermal vias to the ground plane, which is 0.254 mm.
If the vias are not plated shut, cap them with solder mask on the component side at the via diameter plus 0.1 mm minimum. Capping from the far side instead raises measured void area, because flux outgassing and trapped air have no exit.
Thermal budget: what the pad is worth
| Thermal metric, TPS65270 | HTSSOP-24 (PWP) | VQFN-24 (RGE) |
| RθJA junction-to-ambient | 41.3 °C/W | 33.8 °C/W |
| RθJC(top) | 23.9 °C/W | 36.2 °C/W |
| RθJC(bot) | 4 °C/W | 2.5 °C/W |
| RθJB junction-to-board | 22.6 °C/W | 12.1 °C/W |
| ψJT junction-to-top | 0.8 °C/W | 0.4 °C/W |
| ψJB junction-to-board | 22.4 °C/W | 12.2 °C/W |
Table 5: Same die, two 24-pin packages, from the TPS65270 data sheet. The VQFN wins on junction-to-ambient and junction-to-board, the HTSSOP wins on junction-to-case from the top.
The TI power-handling comparison is published for this exact pin count. A standard 24-pin TSSOP is rated at 0.55 W and the PowerPAD version at 2.32 W, both at a 150 °C junction and 80 °C ambient. Divide 70 K by each figure and the implied junction-to-ambient resistances are 127 °C/W and 30 °C/W.
Now size a real part. The TPS65270 recommends a 125 °C junction limit. At 85 °C ambient and 41.3 °C/W, allowable dissipation is 40 K divided by 41.3 °C/W, or 0.97 W. The same die in the 24-pin VQFN at 33.8 °C/W reaches 1.18 W, roughly 22% more headroom.
Neither figure survives a bad joint. TI recommends a minimum solder attach area of 50% of the thermal pad and reports that ordinary production lines exceed 80% without tuning. ROHM defines the same quantity as solder joint rate and treats void rate as approximately 100% minus that rate.
Second sourcing an HTSSOP-24
Moisture sensitivity varies by device rather than by package. The TPS65270 in HTSSOP-24 is rated MSL 2 at 260 °C with a one-year floor life, while the same device in VQFN-24 is MSL 1 with unlimited floor life. Confirm the rating for the orderable part number, not the package family.
Carrier data is worth pulling at the same time. The 24-pin PWP ships 2000 per 330 mm reel in 16 mm tape at 8 mm pitch, with pockets of 6.95 mm × 8.3 mm × 1.6 mm. ROHM ships HTSSOP-B24 at 2000 per reel.
Watch the TI documents for internal disagreement. The generic package view for PWP 24 quotes a 4.4 mm × 7.6 mm body, while the outline drawing gives 7.7 mm to 7.9 mm by 4.3 mm to 4.5 mm and the device information table gives 7.80 mm × 4.40 mm nominal. Use the outline drawing.
Mistakes that send HTSSOP-24 boards back
Treating HTSSOP-24 as a single library part. Three TI mask openings, one Renesas pad and one Analog Devices pad share a lead pattern. The ROHM part does not share even that.
Copying a mask opening from a sibling device. Moving from PWP0024B to PWP0024U cuts pad area by a third and changes the pad from long and narrow to nearly square.
Scaling the stencil aperture by area when the thickness changes. The published tables hold volume. Scaling area strands paste and drives voids.
Leaving thermal relief spokes on the vias under the pad. It is a CAD default and it removes most of the thermal benefit.
Skipping the MSL check on a package change. Moving a 24-pin design from VQFN to HTSSOP can take a line from unlimited floor life to one year.
Frequently asked questions
What is the difference between TSSOP-24 and HTSSOP-24?
Both carry 24 leads on 0.65 mm pitch at 1.20 mm maximum height. The HTSSOP-24 adds an exposed lead frame pad underneath that has to be soldered to board copper. TI rates a standard 24-pin TSSOP at 0.55 W and the PowerPAD version at 2.32 W, at a 150 °C junction and 80 °C ambient.
What size is the HTSSOP-24 thermal pad?
It depends on the drawing. The three TI 24-pin PowerPAD drawings give mask openings of 2.44 mm × 3.42 mm, 2.93 mm × 3.93 mm and 2.4 mm × 5.16 mm. Renesas M24.173C gives 4.30 mm × 3.00 mm. ROHM lists 3.4 mm × 5.0 mm for HTSSOP-B24.
Is HTSSOP-24 a JEDEC package?
The 4.4 mm body version conforms to JEDEC MO-153, variation ADT. Renesas states that on M24.173C and Analog Devices marks the RE-24 drawing MO-153-ADT. HTSSOP itself is a supplier name. The ROHM HTSSOP-B24 uses a wider body and does not match the ADT outline.
How many thermal vias does an HTSSOP-24 need?
The TI guidance is five to nine vias for a small die at a drill diameter of 0.33 mm or smaller. Its 24-pin example layouts use 0.2 mm vias on a 1.0 mm or 1.2 mm grid. Beyond that count, the improvement in board thermal resistance flattens out.
Can I use one footprint for every HTSSOP-24?
Only for the lead lands, and only on the 4.4 mm body. The TI 1.5 mm × 0.45 mm lands on 5.8 mm centres enclose the Renesas and Analog Devices patterns. The thermal land mask opening still has to come from the drawing for your part number.
What to do next
Before you route, open the outline drawing tied to your orderable part number and copy three numbers: the maximum exposed pad, the copper land, and the stencil aperture at your assembler’s stencil thickness. If the drawing code is not on your footprint, your footprint is not verified.
If you are already in production and the die runs hot, x-ray first. Under 50% solder coverage the joint is the fault, not the copper. Over 50% coverage with a hot die, widen the copper, confirm the vias are plated shut, and check for relief spokes.
If you are still choosing, take the HTSSOP-24 when height is capped near 1.2 mm and dissipation sits near 1 W at 85 °C ambient. Take the 24-pin VQFN when board area is the binding constraint and you can accept a harder print in exchange for MSL 1 handling. Take neither on the assumption that the name alone specifies the copper.
Internal links
[INTERNAL LINK: HTSSOP-20 thermal pad and land pattern → the 20-pin equivalent of this footprint problem]
[INTERNAL LINK: JEDEC MO-153 variations → how ACT, ADT and the rest map to pin count and body width]
[INTERNAL LINK: thermal via design rules → drill diameter, grid pitch, plugging and plane connection]
[INTERNAL LINK: MSL 2 and MSL 3 handling → floor life, bake schedules and dry pack policy]
[INTERNAL LINK: HTSSOP vs QFN for power ICs → choosing between height, area and print difficulty]
Sources
TI SLMA002H, PowerPAD Thermally Enhanced Package, Rev. H, July 2018 https://www.ti.com/lit/an/slma002h/slma002h.pdf
TI PWP0024M package outline, land pattern and stencil, drawing 4224354/A https://www.ti.com/lit/ml/pptd353/pptd353.pdf
TI TPS65270 data sheet, SLVSAX7E, with the PWP0024U drawing, thermal, MSL and carrier data https://www.ti.com/lit/ds/symlink/tps65270.pdf
Renesas M24.173C, 24-lead heat-sink TSSOP outline and land pattern, Rev 1, 12/09 https://www.renesas.com/en/document/psc/package-drawing-tssop-ep-24pin-m24173c
Analog Devices FE24 (AA), 24-lead plastic TSSOP, LTC DWG 05-08-1771 Rev B https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-tssop/tssop_24_05-08-1771.pdf
ROHM IC Packages, 2024 Edition short form catalog, HTSSOP-B series https://fscdn.rohm.com/en/products/databook/catalog/common/shortform2024/SF2024_EN_IC_Packages.pdf
