The HTSSOP-20 package has no single thermal pad size. Texas Instruments exposes 2.96 mm × 2.96 mm at maximum material condition on PWP0020T. Renesas exposes 4.19 mm × 3.00 mm on the same 20 leads. Body, pitch and lead span are standardized under JEDEC MO-153. The copper under the body is not. Pull the device drawing before you draw the land.

Key takeaways

• HTSSOP-20 is a supplier name, not a JEDEC name. Drawings reference JEDEC MO-153, and MPS cites variation ACT.
• Body and leads are consistent across suppliers: 6.5 mm × 4.4 mm body, 0.65 mm pitch, 1.20 mm maximum height.
• Exposed pad area spans roughly 1.5:1 across suppliers, from 8.76 mm² to 13.33 mm² on published drawings.
• TI specifies a solder mask defined thermal land and a 1:1 stencil aperture at 0.125 mm stencil thickness.
• Expect junction-to-ambient thermal resistance near 37 °C/W to 40 °C/W, against 83 °C/W for a plain TSSOP-20.
• Solder at least 50% of the pad area, or the datasheet thermal number does not apply to your board.

What the name fixes, and what it leaves open

An HTSSOP-20 is a 20-lead thin shrink small outline package with an exposed thermal pad underneath. Body measures 6.5 mm × 4.4 mm, lead pitch is 0.65 mm, and height is 1.20 mm maximum, per JEDEC MO-153. Exposed pad size is device specific and is not standardized.

[IMAGE 1: Bottom view of an HTSSOP-20 showing the exposed thermal pad set inside the 20 gull-wing leads | alt: “HTSSOP-20 package bottom view showing the exposed thermal pad and 0.65 mm pitch gull-wing leads”]

The H prefix is a supplier convention. Texas Instruments brands the family PowerPAD and uses the package code PWP. ROHM calls its 20-lead version HTSSOP-B20. Renesas issues it as a heat-sink TSSOP under drawings MDP0048 and M20.173A. Monolithic Power Systems simply calls it TSSOP-20 with exposed paddle.

That matters because the exposed pad is the lead frame die pad, exposed at the bottom of the mold. Its size follows the die and the lead frame, not the package outline. Two parts can share a body, a pitch and a lead span while presenting different copper to your board.

Thermal pad size: read the drawing, not the package name

Drawing	Body L × W (mm)	Height max (mm)	Exposed pad (mm)	Pad area (mm²)
TI PWP0020T, 4224598/A, 10/2018	6.6/6.4 × 4.5/4.3	1.2	2.96/2.21 × 2.96/2.16	8.76 max
Renesas M20.173A, Rev 1, 10/15	6.50 ±0.10 × 4.40 ±0.10	1.20	4.19 ±0.10 × 3.000 ±0.1	12.57
Renesas MDP0048, Rev 3, 2/07	6.50 × 4.40	1.20	4.2 × 3.0 reference	12.6
MPS MF-PO-D-0023 Rev 1.0	6.60/6.40 × 4.50/4.30	1.20	4.30/3.80 × 3.10/2.60	13.33 max
ROHM HTSSOP-B20, 2024 catalog	6.5 × 6.4 incl. leads	1.0	2.4 × 4.0	9.6

Table 1: Exposed pad dimensions for 20-lead TSSOP with exposed pad, taken from published package drawings. ROHM quotes body size including the lead span.

The spread is not a rounding difference. The TI maximum exposed pad on PWP0020T is 8.76 mm². The MPS drawing allows 13.33 mm² at maximum material condition, about 52% more area on the same 20 leads.

One more variable hides in the tolerance band. TI dimensions the PWP0020T pad from 2.16 mm to 2.96 mm on one axis and 2.21 mm to 2.96 mm on the other, and notes that the metal pad size may change to satisfy creepage. Design the land to the maximum, then let the solder mask define the joint.

Land pattern: three published footprints, three answers

Source	Lead land L × W (mm)	Row centres (mm)	Thermal land (mm)	Mask treatment
TI PWP0020T example layout	1.5 × 0.45	5.8	3.4 × 6.5 copper, 2.96 × 2.96 opening	Solder mask defined at the pad
Renesas M20.173A	1.45 × 0.35	5.65	4.19 × 3.00	Not specified on drawing
MPS MF-PO-D-0023	1.60 × 0.40	5.80	3.20 × 4.40	Not specified on drawing
KiCad legacy Housings_SSOP	1.45 × 0.45	5.90	3.4 × 6.5, built from 15 plated holes	Mask open over the whole land

Table 2: Recommended land patterns for the same 20 leads. Lead lands are nearly interchangeable. Thermal lands are not.

[IMAGE 2: Three published HTSSOP-20 thermal lands overlaid at the same scale, TI against Renesas against MPS | alt: “HTSSOP-20 land pattern comparison showing TI, Renesas and MPS thermal pad copper at the same scale”]

The lead lands are close enough to interchange. All three suppliers land the gull-wing feet on a pad 1.45 mm to 1.60 mm long and 0.35 mm to 0.45 mm wide, on 0.65 mm pitch, with row centres 5.65 mm to 5.80 mm apart. A generic 0.65 mm TSSOP-20 footprint will solder the leads.

The thermal land is where footprints diverge. TI draws 3.4 mm × 6.5 mm of top copper, then opens the solder mask to 2.96 mm square, so the mask defines the joint and the surplus copper works as a spreader. Renesas matches the land to the pad. MPS oversizes the land by about 0.05 mm per side.

Solder mask and stencil: the QFN rules do not transfer

Most exposed pad advice online is QFN advice. It says never print a full aperture, and target 50% to 75% paste coverage, because a leadless package floats on excess solder. An HTSSOP-20 is not leadless. Its gull-wing leads hold a standoff that TI puts at 0.05 mm to 0.15 mm for TSSOP and TQFP bodies.

That standoff changes the arithmetic. The TI drawing for PWP0020T calls for a 2.96 mm square aperture on a 0.125 mm stencil, which is 1:1 with the mask opening. TI adds that a 5 mil stencil needs a 1:1 aperture ratio to build enough metal for a complete joint, and that thinner stencils may need larger apertures.

Stencil thickness (mm)	Aperture (mm)	Aperture area (mm²)	Paste volume (mm³)
0.100	3.31 × 3.31	10.96	1.10
0.125 (shown on drawing)	2.96 × 2.96	8.76	1.10
0.150	2.70 × 2.70	7.29	1.09
0.175	2.50 × 2.50	6.25	1.09

Table 3: Thermal pad stencil apertures for TI PWP0020T. Thickness and aperture are from the drawing. Area and volume are calculated from them.

[IMAGE 4: Stencil aperture, solder mask opening and copper land drawn concentrically for the thermal pad at 0.125 mm stencil | alt: “HTSSOP-20 thermal pad stencil aperture of 2.96 mm square on a 0.125 mm stencil”]

Read the volume column, not the area column. TI is holding deposited paste at roughly 1.09 mm³ across every stencil thickness. If your assembler deviates from the drawing, hold that volume rather than the aperture dimension.

ROHM takes the other position for the same package class. It recommends splitting the aperture to vent flux gas, and setting printed paste area at 50% to 80% of the exposed pad. Its published HTSSOP-C48 example prints 52.7%. Both positions are defensible. Follow the drawing bound to your part number, and hold the other in reserve if x-ray shows voiding.

Thermal vias under the pad

The TI numbers are specific and easy to apply. Use a via drill of 0.33 mm or smaller so the barrel does not wick paste out of the joint. Five to nine vias are adequate for a small die. Never use thermal relief spokes, because a relief exists to raise thermal resistance.

The example layout on PWP0020T places 0.2 mm vias on a 1.3 mm grid inside the thermal land. If the vias are not plated shut, cap them with solder mask on the component side, sized at the via diameter plus 0.1 mm minimum. Tenting from the opposite side instead shows more voiding on x-ray, because flux outgassing and trapped air have nowhere to go.

[IMAGE 3: Cross section through a soldered thermal pad showing lead standoff, mask-capped thermal via and inner plane | alt: “HTSSOP-20 thermal pad cross section with thermal vias, solder mask capping and inner copper plane”]

ROHM adds the failure mode from the other end. Solder drawn into an open thermal via lowers the fusion ratio, which raises the thermal resistance you designed against.

What the pad buys you, and what takes it away

Thermal metric	LM5117, PWP 20	TPS92601-Q1, PWP 20	TSSOP-20, PW
RθJA junction-to-ambient	40 °C/W	37 °C/W	83 °C/W
RθJC(top)	4 °C/W	23.4 °C/W	not published
RθJC(bot)	not published	0.9 °C/W	not applicable
RθJB junction-to-board	not published	17.7 °C/W	not published
ψJT junction-to-top	not published	0.9 °C/W	not published

Table 4: Published thermal metrics. The TSSOP-20 column is TI logic package data on a high-K board at 0 LPM per JESD51-5, so treat it as an order-of-magnitude comparison, not a like-for-like test.

Work the numbers for a real limit. At a 125 °C junction limit and 85 °C ambient, a part at 37 °C/W dissipates 40 K divided by 37 °C/W, which is 1.08 W. The same silicon in a plain TSSOP-20 at 83 °C/W gets 0.48 W. The TI comparison for a 20-pin SSOP puts the standard package at 0.75 W and the PowerPAD version at 3.25 W, at a 150 °C junction and 80 °C ambient.

None of that arrives without a solder joint. TI recommends a minimum solder attach area of 50% of the package thermal pad, and reports that unoptimised production processes routinely exceed 80%. ROHM frames the same variable as solder joint rate, and treats void rate as approximately 100% minus joint rate.

Five mistakes that send HTSSOP-20 boards to rework

Reusing one footprint across suppliers. A land drawn for a 2.96 mm square TI pad under-serves a 4.19 mm × 3.00 mm Renesas pad. A land drawn for Renesas can crowd the mask on the TI part.

Inheriting a library footprint without checking the paste layer. The archived KiCad HTSSOP-20 footprint builds its thermal land from 15 plated holes on a 1.3 mm grid, on copper and mask layers only. It prints no paste on the thermal land at all.

Putting thermal relief spokes on the thermal vias. This is a default in several CAD tools, and it quietly removes most of the benefit of the pad.

Tenting vias from the far side of the board. It looks tidy on the fabrication drawing and it raises void area under the package.

Assuming the pad is ground. On the LM5117 the exposed pad is electrically isolated, and TI still directs designers to solder it to the ground plane for thermal reasons. Check the pin table, not the habit.

Assembly, moisture and sourcing notes

Moisture sensitivity is a real difference between package options for the same die. TI lists the LM5117 in HTSSOP-20 at MSL 3, 260 °C, with a 168-hour floor life, while the same device in WQFN-24 is MSL 1 with unlimited floor life. That is a bake and dry-pack policy, not a footnote.

Carrier data is worth capturing early. The 20-pin PWP ships in 16 mm tape at 8 mm pitch, with pockets of 6.95 mm × 7.0 mm × 1.4 mm, on 178 mm reels of 250 or 330 mm reels of 2500, plus tubes of 73. ROHM ships HTSSOP-B20 at 2500 per reel.

For rework, TI reports removing 20-pin PowerPAD TSSOP parts with hot air in preference to hot bar, with local preheat near 160 °C. Hot air stresses the board and its neighbours less and is easier to control.

Frequently asked questions

What is the difference between TSSOP-20 and HTSSOP-20?

Same 20 leads, same 0.65 mm pitch, same 1.20 mm maximum height. The HTSSOP-20 adds an exposed lead frame pad on the underside that must be soldered to board copper. The practical result is junction-to-ambient thermal resistance near 37 °C/W to 40 °C/W instead of 83 °C/W on a plain TSSOP-20.

What size is the HTSSOP-20 thermal pad?

It depends on the supplier and the device. The TI PWP0020T drawing gives 2.96 mm square at maximum. Renesas M20.173A gives 4.19 mm × 3.00 mm. ROHM lists 2.4 mm × 4.0 mm for HTSSOP-B20. Take the number from the drawing bound to your orderable part number.

Do I have to solder the HTSSOP-20 thermal pad?

Yes, if you want the datasheet thermal numbers. TI states that the PowerPAD package is not designed for use with an unsoldered pad, and advises against it on thermal and mechanical grounds. Target at least 50% solder coverage of the pad area and verify by x-ray.

How many thermal vias go under an HTSSOP-20?

The TI guidance is five to nine vias for a small die, with a drill diameter of 0.33 mm or smaller. Its own PWP0020T example layout uses 0.2 mm vias on a 1.3 mm grid. Adding vias past that point gives diminishing returns on board thermal resistance.

Is the HTSSOP-20 exposed pad connected to ground?

Usually, but not always internally. On the LM5117 the pad is electrically isolated from the die and is still meant to be soldered to the ground plane. Treat the pin table as authoritative, and confirm that tying the pad to your ground plane is electrically correct.

What to do next

If you are laying out a new HTSSOP-20 today, download the package drawing tied to your exact orderable part number and copy three numbers from it: maximum exposed pad size, thermal land copper, and the stencil aperture at your assembler’s stencil thickness. Do not inherit them from a library.

If you are debugging a hot part, x-ray the joint before you touch the layout. Below 50% solder coverage the thermal path is your problem, not the copper. Above 50% coverage with a hot die, add copper area and confirm the vias are plated shut and free of relief spokes.

If you are selecting a package, take the HTSSOP-20 when height is capped near 1.2 mm and the design needs roughly 1 W of dissipation at 85 °C ambient. Above that, or where board area is tighter than height, a QFN in the same pin count will beat it thermally and cost you the standoff that makes this package easy to print.

Internal links

[INTERNAL LINK: QFN vs HTSSOP for power ICs → package selection when height and area compete]

[INTERNAL LINK: thermal via design rules → via diameter, pitch, fill and plane connection]

[INTERNAL LINK: JEDEC MO-153 package family → TSSOP outline variations and lead spans]

[INTERNAL LINK: MSL 3 handling → floor life, bake schedules and dry pack policy]

[INTERNAL LINK: stencil aperture ratios → holding paste volume across stencil thicknesses]

Sources

TI SLMA002H, PowerPAD Thermally Enhanced Package, Rev. H, July 2018  https://www.ti.com/lit/an/slma002h/slma002h.pdf

TI PWP0020T package outline, land pattern and stencil, drawing 4224598/A  https://www.ti.com/lit/ml/pptd378/pptd378.pdf

TI LM5117 / LM5117-Q1 datasheet, SNVS698F, thermal, MSL and carrier data  https://www.ti.com/lit/ds/symlink/lm5117.pdf

Renesas M20.173A, 20-lead heatsink TSSOP outline and land pattern, Rev 1  https://www.renesas.com/en/document/psc/package-drawing-tssop-ep-20pin-m20173a

MPS TSSOP-20 with exposed paddle, MF-PO-D-0023 Rev 1.0, JEDEC MO-153 ACT  https://media.monolithicpower.com/cms_document/Package%20Information/TSSOP-20%20EP%20POD.pdf

ROHM 67AN015E, Solder Joint Rate and Thermal Resistance of Exposed Pad, June 2024  https://fscdn.rohm.com/en/products/databook/applinote/ic/common/solder_joint_rate_and_thermal_resistance_of_exposed_pad_an-e.pdf