Every 38-lead TSSOP package in production shares one geometry: 0.5 mm pitch on a 4.4 mm wide body, 9.7 mm long, 1.2 mm maximum height, with a lead span of 6.25 mm to 6.55 mm. Texas Instruments, NXP and Infineon all publish that outline. The default TSSOP-38 footprint in the KiCad library does not match it, which is where most failed boards start.

Key takeaways

• TSSOP-38 dimensions: body 9.65 mm to 9.75 mm by 4.35 mm to 4.45 mm, lead span 6.25 mm to 6.55 mm, pitch 0.5 mm, height 1.2 mm max, per TI drawing DBT0038A.
• Unlike lower lead counts, 38-lead TSSOP is not a 0.65 mm pitch package. NXP SOT510-1 and Infineon PG-TSSOP-38-4 confirm 0.5 mm on the same 9.7 mm by 4.4 mm body.
• The KiCad Package_SO library ships TSSOP-38 at 6.1 mm by 12.5 mm on 0.65 mm pitch, with pad rows 1.6 mm further apart than TI specifies. Selecting by name alone produces an unbuildable board.
• The exposed-pad version matters: 83.6 °C/W for the plain 38-pin TSSOP against 32.7 °C/W for the 38-pin HTSSOP, both measured by TI on JEDEC boards.
• TI’s own drawing and datasheet text disagree on thermal via diameter, 0.2 mm against 0.33 mm. The drawing is the controlled document.

[IMAGE 1: dimensioned top, side and end view of a 38-lead TSSOP with pitch, lead span and height called out | alt: “TSSOP-38 package dimensions showing 0.5 mm pitch and 6.4 mm nominal lead span”]

What TSSOP-38 means in practice

A TSSOP-38 package is a plastic thin shrink small outline package with 19 gull-wing leads per side. At this lead count the industry converged on one body: 9.7 mm by 4.4 mm nominal, 0.5 mm pitch. That convergence is real but informal.

JEDEC Publication 95, in its index by device type, lists MO-153 with registered lead counts of 8, 14, 16, 20, 24, 28, 36, 40, 48, 52, 56, 60, 64 and 68. There is no 38. Vendors reference MO-153 anyway: TI notes it on both the DBT0038A and DCP0038A drawings, and NXP lists MO-153 against SOT510-1 with an issue date of 2 November 2005.

So the name is a strong hint rather than a specification. It tells you the pitch is almost certainly 0.5 mm and the body 4.4 mm wide. It does not tell you whether the part underneath carries an exposed thermal pad, and that single question changes both the copper you draw and the power you can dissipate.

TSSOP-38 dimensions

Table 1 sets the plain package against the exposed-pad version, both from current TI drawings.

Table 1. TSSOP-38 mechanical data, dimensions in mm

Parameter	TSSOP-38, TI DBT0038A (4220221/A)	HTSSOP-38, TI DCP0038A (4218816/A)
Leads	38	38 plus thermal pad
Lead pitch	0.5	0.5
Body length	9.65 to 9.75	9.6 to 9.8
Body width	4.35 to 4.45	4.3 to 4.5
Lead span	6.25 to 6.55 typ	6.2 to 6.6 typ
Height, max	1.2	1.2
Standoff	0.05 to 0.15	0.05 to 0.15
Lead width	0.17 to 0.23	0.17 to 0.27
Foot length	0.50 to 0.75	0.50 to 0.75
Lead angle	0 to 8 degrees	0 to 8 degrees
Exposed pad	none	3.94 to 4.70 by 2.43 to 2.90
JEDEC reference	MO-153	MO-153

Two other vendors publish the same envelope. NXP describes SOT510-1 as a 38-lead TSSOP with 0.5 mm pitch and a 9.7 mm by 4.4 mm by 1.1 mm body. Infineon lists PG-TSSOP-38-4 with a 9.7 mm body length, 4.4 mm body width, 0.5 mm minimum terminal pitch and no exposed paddle. Three manufacturers, one outline, which is unusual and useful.

The footprint trap: what your CAD library calls TSSOP-38

The KiCad Package_SO library contains a footprint named TSSOP-38_6.1×12.5mm_P0.65mm. Its pads measure 1.475 mm by 0.4 mm, sit on 0.65 mm pitch, and are centred 3.7125 mm either side of the axis. Its description cites JEDEC MO-153 variation DD-1.

TI’s land pattern for DBT0038A places 38 lands of 1.5 mm by 0.3 mm on 0.5 mm pitch, with the rows dimensioned at 5.8 mm, so land centres sit 2.9 mm either side. The pad rows differ by 0.81 mm per side. Worse, the pitch error accumulates: at 0.15 mm per pin across 19 pins, the last lead lands 2.7 mm away from its pad.

A correct 0.5 mm version exists in KiCad’s legacy Housings_SSOP repository as TSSOP-38_4.4×9.7mm_Pitch0.5mm, referencing NXP SOT510-1. Both files carry the string TSSOP-38, and only one of them matches any device you can buy. Search your library by pitch and body size, never by lead count and family name.

TSSOP-38 footprint, thermal land and stencil apertures

For the plain package, TI’s example land pattern is 38 lands of 1.5 mm by 0.3 mm at 0.5 mm pitch, rows dimensioned at 5.8 mm, non solder mask defined, with 0.05 mm of mask clearance all around. The stencil example uses the same aperture size on a 0.125 mm foil.

The exposed-pad version adds a thermal land of 2.9 mm by 4.7 mm with 0.2 mm vias, three of them spaced 1.2 mm apart along the pad, and TI shows it as a solder mask defined pad rather than the non-mask-defined signal lands. Note 9 on that drawing warns that the surrounding metal, dimensioned 3.4 mm by 9.7 mm, may change to meet creepage requirements.

Thermal aperture size tracks foil thickness so paste volume stays constant: 3.24 mm by 5.25 mm at 0.100 mm, 2.90 mm by 4.70 mm at 0.125 mm, 2.65 mm by 4.29 mm at 0.150 mm and 2.45 mm by 3.97 mm at 0.175 mm. The aperture shrinks by 30 percent in area from the thinnest foil to the thickest.

Board area is worth calculating before you commit. Along the rows, 18 spaces at 0.5 mm plus one land width gives 9.3 mm. Across the rows, 5.8 mm plus one land length gives 7.3 mm, so roughly 68 mm². The mismatched 0.65 mm library footprint claims a 9.4 mm by 13.0 mm courtyard, about 122 mm², which is another way to catch the error during placement review.

At 0.5 mm pitch the gap between adjacent lands is 0.2 mm. Confirm your fabricator’s minimum mask dam, and keep the lands non solder mask defined.

[IMAGE 2: land pattern drawing showing 38 lands, row dimension, thermal land and the three thermal vias | alt: “TSSOP-38 footprint with 1.5 mm by 0.3 mm lands on 0.5 mm pitch and a 2.9 by 4.7 mm thermal land”]

Thermal performance: the pad is worth 2.5 times

TI publishes junction-to-ambient figures for both versions of this outline. The ADS795x family in the plain 38-pin DBT package reads 83.6 °C/W. The DRV8711 in the 38-pin DCP package with a thermal pad reads 32.7 °C/W. Same lead frame footprint, same 9.7 mm body, 2.5 times the difference.

Convert that into a power budget. At an 85 °C ambient and a 150 °C junction limit, the plain package supports 65 divided by 83.6, which is 0.78 W. The exposed-pad version supports 65 divided by 32.7, which is 1.99 W. Any design dissipating more than about three quarters of a watt has already chosen the pad, whether or not the schematic says so.

Do not treat either number as a package constant. The BUF22821, in the same DCP-38 outline, is specified at 40 °C/W with the pad attached on a JEDEC high-K board at zero airflow. Junction-to-ambient depends on die, pad size and board copper together, so use the number from your own part’s datasheet.

The heat path direction is unambiguous. For the DRV8711, junction-to-case through the bottom is 0.9 °C/W while junction-to-case through the top is 17.2 °C/W, a factor of 19. Copper under the package is your heatsink; anything you attach to the plastic is decoration.

Table 2. Thermal and packing data across two TSSOP-38 variants

Attribute	TSSOP-38 without pad (DBT)	HTSSOP-38 with pad (DCP)
Example device	ADS7953, SN65LVDS388A	DRV8711, BUF22821
Junction-to-ambient	83.6 °C/W (ADS795x)	32.7 °C/W (DRV8711), 40 °C/W (BUF22821)
Junction-to-board	44.7 °C/W	14.3 °C/W
Junction-to-case, bottom	not published	0.9 °C/W
Power at 85 °C, 150 °C junction	about 0.78 W	about 1.99 W
Thermal land needed	no	2.9 by 4.7 mm plus vias
Tape and reel	330 mm reel, 16 mm tape, 2500 per reel (NXP SOT510-1)	330 mm reel, 16 mm tape, 12 mm pitch, 2000 per reel (TI DCP)
Moisture sensitivity	check the addendum for the part	Level 3, 260 °C, 168 h (BUF22821)
Rework	leads visible, iron accessible	pad requires hot air or hot plate

TSSOP-38 pinout and the 39th terminal

Pin numbering follows the standard dual-row rule: pin 1 at the index feature, counterclockwise from the top view, pins 1 to 19 down one side and 20 to 38 back up the other, with 19 and 20 facing each other across the short end. Function assignment belongs to the device, so there is no generic TSSOP-38 pinout to copy.

The detail that catches people is terminal 39. On TI’s DCP land pattern the thermal pad is numbered as a 39th terminal, and on parts like the DRV8711 and BUF22821 it is not optional or floating. The DRV8711 lists GND on pins 5, 29, 38 and PPAD; the BUF22821 requires its pad tied to the most negative supply, with analog and digital grounds joined at the device.

Check that your schematic symbol actually exposes that terminal. A symbol generated from a 38-pin table will silently leave the pad unconnected, and the layout will pass DRC while the part runs hot.

Assembly, moisture sensitivity and sourcing

TI ships the BUF22821 in HTSSOP-38 at moisture sensitivity Level 3 with a 260 °C peak and a 168 hour floor life, 2000 per large tape and reel. Classification follows IPC/JEDEC J-STD-020 and floor life follows J-STD-033, so a reel opened on Monday and finished the following week needs a bake, not an argument.

Feeder planning is simple here because the whole family lands on 16 mm tape. TI’s DCP-38 reel is 330 mm with 16.4 mm reel width, pockets 6.9 mm by 10.2 mm by 1.8 mm deep on 12 mm pitch. NXP packs SOT510-1 as 2500 pieces on a 330 mm by 16 mm reel, and Infineon lists 1000 and 3000 piece reels for PG-TSSOP-38-4.

On cost, Digi-Key listed the TI SN65LVDS388ADBTR at 5.17 US dollars in ones and 2.897 US dollars in 2000-piece reels, with 1,267 in stock and a six-week factory lead time when checked in August 2026. The ST STNRG388A, also 38-lead TSSOP, listed at 7.75 dollars in ones from a 36-piece tube stock. Fine-pitch legacy packages carry a price premium at low volume.

Watch the lifecycle signals. NXP’s SOT510-1 page lists four associated products, all TDA665x tuner devices, and Digi-Key’s inventory for the LVDS receiver includes stock held by Rochester Electronics, an aftermarket source. Neither means the part is dead, but both indicate a mature package. If your product runs for a decade, identify a QFN or larger-pitch second source now rather than during an allocation.

One caution on distributor data: Digi-Key files this package under the string 38-TFSOP with a 0.173 inch width, and separately as 38-TSSOP under supplier device package. Parametric search by package name will miss parts. Search by pitch and body dimensions instead.

Five mistakes that cost a board spin

1. Taking a library footprint because its name reads TSSOP-38. Check pitch and pad row spacing against the drawing every time, since the common library part is 0.65 mm pitch and 1.6 mm too wide.
2. Reusing a 38-pin symbol that has no terminal 39, which leaves the thermal pad unconnected on a part that requires it as a ground return.
3. Sizing the thermal stencil aperture once and reusing it across foil thicknesses, when TI’s own table varies the aperture area by 30 percent from 0.100 mm to 0.175 mm foil.
4. Taking a published junction-to-ambient number as a package constant, when two TI devices in the identical DCP-38 outline quote 32.7 and 40 °C/W.
5. Following the datasheet text on via diameter instead of the drawing. The BUF22821 body text calls for 13 mil vias while drawing 4218816/A shows 0.2 mm.

TSSOP-38 package FAQ

What are the dimensions of a TSSOP-38 package?

Body length is 9.65 mm to 9.75 mm, body width 4.35 mm to 4.45 mm, lead span 6.25 mm to 6.55 mm and height 1.2 mm maximum, on 0.5 mm pitch, per TI drawing DBT0038A. Lead width runs 0.17 mm to 0.23 mm and foot length 0.50 mm to 0.75 mm. NXP and Infineon publish the same 9.7 mm by 4.4 mm envelope.

What is the pitch of a TSSOP-38 package?

It is 0.5 mm on every 38-lead device drawing checked here, including TI DBT0038A and DCP0038A, NXP SOT510-1 and Infineon PG-TSSOP-38-4. Lower lead counts in the same family often use 0.65 mm, which is why generic library footprints for 38 pins are frequently wrong.

What is the difference between TSSOP-38 and HTSSOP-38?

HTSSOP-38 is the same outline with an exposed thermal pad measuring 3.94 mm to 4.70 mm by 2.43 mm to 2.90 mm on the underside. Lead geometry and height are unchanged. The board gains a thermal land and vias, and junction-to-ambient falls from about 83.6 to 32.7 degrees Celsius per watt.

Does the TSSOP-38 thermal pad have to be soldered?

Yes on parts that specify it. TI instructs that the PowerPAD be soldered even in low-dissipation applications, because the connection is mechanical as well as thermal, and on devices such as the DRV8711 and BUF22821 the pad is also a ground return.

Can a TSSOP-38 be hand soldered?

The 0.5 mm pitch is workable by drag soldering with plenty of flux and a fine tip, though it is less forgiving than 0.65 mm parts. The exposed pad cannot be reached with an iron, so an exposed-pad device needs hot air or a hot plate, or you accept the plain package instead.

What to do next

Start from the drawing for the exact orderable part number and confirm three numbers: 0.5 mm pitch, a lead span between 6.2 mm and 6.6 mm, and whether an exposed pad exists. Then verify your library footprint against those numbers before routing, because the name on the file proves nothing.

If the part has no pad and your dissipation stays under about 0.75 W at 85 °C ambient, the plain land pattern is enough: 1.5 mm by 0.3 mm lands, 0.5 mm pitch, rows at 5.8 mm. If the part has a pad, or you need more than a watt, draw the 2.9 mm by 4.7 mm thermal land with its vias, size the stencil aperture to the foil you actually use, and connect the pad to the plane with full annular copper rather than thermal relief spokes.

Reach for a different package when the pitch stops paying. Below 68 mm² of available area a QFN gives you the same pin count in far less space, and above roughly 2 W at 85 °C no amount of TSSOP land pattern will save the thermal budget.

[IMAGE 3: side-by-side land patterns, the correct 0.5 mm TSSOP-38 against the 0.65 mm library footprint, same scale | alt: “Correct TSSOP-38 footprint compared with the mismatched 0.65 mm pitch library footprint”]

Internal links

• [INTERNAL LINK: TSSOP-32 package -> TSSOP-32 dimensions, pinout and footprint]
• [INTERNAL LINK: exposed pad thermal via design -> PowerPAD and thermal land layout guide]
• [INTERNAL LINK: moisture sensitivity level -> MSL floor life, baking and dry pack handling]
• [INTERNAL LINK: QFN versus TSSOP -> package selection for pin count against board area]
• [INTERNAL LINK: footprint verification -> checking CAD library land patterns against vendor drawings]

External references

• TI package outline DBT0038A: https://www.ti.com/lit/ml/mpds368a/mpds368a.pdf
• TI BUF22821 datasheet with DCP0038A drawing and PowerPAD guidance: https://www.ti.com/lit/ds/symlink/buf22821.pdf
• TI DRV8711 datasheet, 38-pin HTSSOP thermal data: https://www.ti.com/lit/ds/symlink/drv8711.pdf
• NXP package page SOT510-1 (TSSOP38): https://www.nxp.com/packages/SOT510-1
• JEDEC Publication 95 index by device type: https://www.jedec.org/sites/default/files/MOIND_DT.pdf