The TSSOP-16 package is a 16-lead thin shrink small outline package registered to JEDEC MO-153, variation AB. The body measures 4.4 mm × 5.0 mm, the lead span is 6.4 mm, the pitch is 0.65 mm and the seated height is 1.2 mm maximum. This page gives the outline dimensions, the pin-numbering rules, four vendor land patterns side by side, and the thermal and routing limits that decide whether TSSOP-16 belongs in your design.
Key takeaways
- MO-153 variation AB fixes the outline: 4.4 mm × 5.0 mm body, 6.4 mm lead span, 0.65 mm pitch, 1.2 mm maximum height.
- Vendor land patterns are not interchangeable. Toe-to-toe span runs from 6.80 mm (Diodes) to 7.40 mm (Monolithic Power Systems) for the same package.
- A package has no pinout. TSSOP-16 fixes lead count, geometry and numbering direction only.
- It is the weakest 16-lead package thermally. TI rates the same DRV8833 die at 0.5 A RMS per bridge in TSSOP-16 and 1.5 A in HTSSOP-16.
- Pad width sets your escape strategy. A 0.45 mm pad leaves a 0.20 mm channel; a 0.35 mm pad leaves 0.30 mm, enough for a 0.10 mm trace.
- Moisture sensitivity belongs to the device, not the package. MSL 1 and MSL 3 parts both ship in TSSOP-16.
[IMAGE 1: Dimensioned TSSOP-16 outline, top and side views, with A, A1, D, E, E1, e and L called out | alt: “TSSOP-16 package dimensions: 4.4 mm x 5.0 mm body, 6.4 mm lead span, 0.65 mm pitch”]
TSSOP-16 dimensions (JEDEC MO-153, variation AB)
TSSOP-16 is a 16-lead gull-wing surface-mount package with a 4.4 mm wide by 5.0 mm long plastic body, a 6.4 mm nominal lead span, 0.65 mm lead pitch and a 1.2 mm maximum seated height. Eight leads sit on each long side. It is registered to JEDEC MO-153, variation AB.
Table 1. TSSOP-16 outline dimensions, in millimeters
| Symbol | Feature | Min | Max | Source and notes |
| A | Seated height | — | 1.20 | TI PW0016A; Diodes caps its own part at 1.08 |
| A1 | Standoff | 0.05 | 0.15 | TI, Diodes and MPS agree |
| A2 | Body thickness | 0.80 | 0.93 | Diodes; MPS gives 0.80 to 1.05 |
| b | Lead width | 0.17 | 0.30 | TI; Diodes and MPS start at 0.19 |
| c | Lead thickness | 0.09 | 0.20 | Diodes, MPS |
| D | Body length | 4.90 | 5.10 | All four sources agree |
| E | Lead span | 6.20 | 6.60 | 6.40 BSC nominal |
| E1 | Body width | 4.30 | 4.50 | All four sources agree |
| e | Lead pitch | 0.65 BSC | 0.65 BSC | 14 spaces, 7 per side |
| L | Foot length | 0.50 | 0.75 | TI; Diodes and MPS start at 0.45 |
| θ | Lead angle | 0° | 8° | Gull-wing form |
| — | Coplanarity | — | 0.10 | MPS drawing MF-PO-D-0026 |
Two numbers move between suppliers, and both can bite. Diodes specifies a 1.08 mm maximum height rather than the 1.20 mm JEDEC ceiling, and gives an approximate part weight of 0.055 g. NXP lists SOT403-1 as a 5 mm × 4.4 mm × 1.1 mm body referenced to MO-153, while SOT403-3 is the same package at 1.05 mm.
If your enclosure gap is under about 1.4 mm, take the height from the specific vendor drawing rather than from MO-153. Lead coplanarity after forming is capped at 0.10 mm on the MPS drawing; it is the single mechanical parameter most likely to cause open joints on a warped board.
TSSOP-16 pinout: what the package fixes and what it does not
TSSOP-16 has no pinout. The package standard fixes lead count, geometry and numbering direction. Function assignment belongs to the device, so “TSSOP-16 pinout” only has an answer once you name the part.
Numbering runs counter-clockwise from the pin 1 index area, viewed from the top: pins 1 to 8 down one side, then 9 to 16 back up the other. Pin 1 sits at the top-left, marked by a moulded dimple, a bevelled corner, or both.
Two TI parts in the same PW package show the spread. On the SN74AHC595 shift register, VCC is pin 16 and GND is pin 8. On the DRV8833 motor driver, VM is pin 12 and GND is pin 13. Same body, same land pattern, completely different nets.
Mirror the footprint if the part mounts on the bottom side. The index mark still marks pin 1, but the numbering direction reverses when the board is viewed from the top.
One more trap worth naming: TSSOP-14 and TSSOP-16 share a body. TI drawings PW0014A and PW0016A both specify a 4.9 mm to 5.1 mm body length, 4.3 mm to 4.5 mm width, 6.2 mm to 6.6 mm lead span and the same 5.8 mm land row spacing. Only the lead count differs, so count leads instead of judging by size.
[IMAGE 2: Top view showing counter-clockwise pin numbering 1 to 16 with the pin 1 index area highlighted | alt: “TSSOP-16 pin numbering runs counter-clockwise from the pin 1 index mark, top view”]
TSSOP-16 footprint: four vendor land patterns compared
Every supplier publishes a recommended land for the same JEDEC outline, and they do not match. Z is the toe-to-toe span across the pattern, G is the gap between the inner pad edges.
Table 2. Recommended TSSOP-16 land patterns, in millimeters
| Source | Pad L × W | Pitch | Row centres | Span Z | Gap G |
| TI PW0016A (4220204/B) | 1.50 × 0.45 | 0.65 | 5.80 | 7.30 | 4.30 |
| Monolithic Power Systems | 1.60 × 0.40 | 0.65 | 5.80 | 7.40 | 4.20 |
| Diodes Incorporated | 1.40 × 0.35 | 0.65 | 5.40 | 6.80 | 4.00 |
| Richtek | 1.00 × 0.35 | 0.65 | 6.00 | 7.00 | 5.00 |
That is a 0.60 mm spread in outer span and a 0.60 mm spread in pad length across four suppliers of one package. All four solder acceptably. They trade heel fillet volume against clearance and inspectability.
Use the device manufacturer’s pattern when one exists, because that is the geometry their assembly qualification ran on. If you need a single house footprint for multi-sourced parts, the TI geometry is the safe default: its 7.30 mm span and 4.30 mm gap bracket the others, so a part built to any of these drawings still lands inside the pads.
Two conditions change the answer. For wave or selective soldering, Diodes advises adding 0.2 mm to the Z dimension to build a longer toe fillet. For dense escape routing, the 0.35 mm pads used by Diodes and Richtek buy 0.10 mm of extra channel in every gap.
Mask and stencil follow the same drawing. TI calls non-solder-mask-defined pads preferred, with 0.05 mm mask relief all around, and specifies a 1:1 stencil aperture of 1.5 mm × 0.45 mm on a 0.125 mm stencil.
[IMAGE 3: Four vendor land patterns overlaid on one grid with Z and G dimensioned | alt: “TSSOP-16 footprint comparison, toe-to-toe span from 6.80 mm to 7.40 mm across four vendors”]
Escape routing at 0.65 mm pitch: run the arithmetic first
Subtract pad width from pitch to get the routing channel between two adjacent pads. The result decides your layer count before you place a single trace.
- TI’s 0.45 mm pad: 0.65 − 0.45 = 0.20 mm. One trace plus two clearances must fit in 0.20 mm, which means roughly 0.06 mm line and 0.07 mm space. That is outside standard fabrication.
- A 0.35 mm pad: 0.65 − 0.35 = 0.30 mm. A 0.10 mm trace with 0.10 mm clearance each side fits on a common 4 mil / 4 mil process.
The practical answer is to stop routing between pads. Route under the body instead. TI’s pattern leaves 4.30 mm between the inner pad edges, roughly 4.3 mm × 5 mm of clear area for escape traces or a ground pour, even on a two-layer board. Take whatever is left off the ends of the two pad rows.
Thermal limits: TSSOP-16 is the weakest package in its class
The thin body that makes TSSOP-16 attractive also removes the heat path. TI publishes three 16-lead options for one DRV8833 die, which makes the comparison exact rather than approximate.
Table 3. DRV8833, one die, three 16-lead packages (JEDEC test board)
| Metric | PW (TSSOP) | PWP (HTSSOP) | RTY (WQFN) |
| RθJA, junction to ambient (°C/W) | 103.1 | 40.5 | 37.2 |
| RθJB, junction to board (°C/W) | 48.1 | 28.8 | 15.3 |
| RθJC bottom (°C/W) | not specified | 4.8 | 3.5 |
| Rated output per bridge (A RMS) | 0.5 | 1.5 | 1.5 |
| Body size (mm) | 5.00 × 4.40 | 5.00 × 4.40 | 4.00 × 4.00 |
TI derates the same silicon by 3:1 on package alone and states in the layout section that the PW option is not thermally enhanced.
Worked example, DRV8833 in TSSOP-16 at an 85 °C ambient. On-resistance is 325 mΩ high-side plus 275 mΩ low-side at TJ = 85 °C and VM = 5 V. Two bridges at 0.5 A RMS therefore dissipate 2 × 0.6 Ω × 0.5² = 0.30 W, or about 0.33 W to 0.39 W once the 10 % to 30 % switching loss is added. The budget to hold TJ at 125 °C is (125 − 85) / 103.1 = 0.39 W. The 500 mA figure is not a marketing number; it is the package.
Check the datasheet revision before trusting an older thermal figure. Revision M of the SN74AHC595 datasheet raised RθJA for the PW package from 106.1 °C/W to 135.9 °C/W, and revision N raised the SOIC number from 73 °C/W to 93.8 °C/W. The packages did not change; the characterisation did.
If the budget is tight, move to the exposed-pad variant. TI’s PWP0016C drawing gives a thermal pad of 2.46 mm × 2.31 mm maximum, a solder-mask-defined thermal land, 0.2 mm vias on a 1.2 mm grid, and stencil apertures that scale from 2.46 mm × 2.31 mm at 0.125 mm stencil thickness to 2.75 mm × 2.58 mm at 0.1 mm. The Diodes equivalent, TSSOP-16EP Type DX, exposes 2.70 mm × 2.50 mm minimum. In both cases the 16 lead pads are unchanged, so the swap costs a copper pour and a via field, not a new footprint.
[IMAGE 4: HTSSOP-16 land pattern showing the 16 lead pads plus the solder-mask-defined thermal land and via field | alt: “HTSSOP-16 exposed pad land pattern with 0.2 mm thermal vias on a 1.2 mm grid”]
TSSOP-16 vs SOIC-16, SSOP-16 and WQFN-16
The cleanest comparison again comes from one datasheet, because a single die was characterised in every body. These figures are from the SN74AHC595.
Table 4. Sixteen-lead package options for the SN74AHC595
| Package | Outline (mm) | Body (mm) | Pitch | Height | RθJA (°C/W) |
| TSSOP (PW) | 5.00 × 6.4 | 5.00 × 4.40 | 0.65 | 1.2 max | 135.9 |
| SSOP (DB) | 6.20 × 7.8 | 6.20 × 5.30 | 0.65 | 2.0 max | 97.8 |
| SOIC (D) | 9.90 × 6.0 | 9.90 × 3.90 | 1.27 | 1.75 max | 93.8 |
| WQFN (BQB) | 3.5 × 2.5 | 3.5 × 2.5 | 0.50 | 0.8 max | 91.8 |
| PDIP (N) | 19.31 × 9.4 | 19.31 × 6.35 | 2.54 | through-hole | 47.8 |
Against SOIC-16, TSSOP-16 cuts outline area from 59 mm² to 32 mm², a 46 % reduction, and drops maximum height from 1.75 mm to 1.2 mm. The price is thermal and process: on this data it runs about 45 % hotter per watt than the SOIC and nearly three times hotter than the PDIP.
A decision path that matches how the constraint actually arrives:
- Mounted height under 1.5 mm? SOIC-16 is out. Consider TSSOP-16 or WQFN-16.
- Dissipation above roughly 0.4 W at your maximum ambient? Plain TSSOP-16 is out. Use HTSSOP-16 or WQFN-16.
- Two-layer board with no fine-line process? SOIC-16 at 1.27 mm pitch routes with room to spare.
- Need visible joints for AOI or hand rework? TSSOP-16 beats WQFN-16, because the leads are inspectable.
- All four satisfied? Choose TSSOP-16 and take the device manufacturer’s land pattern.
Sourcing, packing and compliance details that surface late
Moisture sensitivity travels with the device, not the package. TI ships SN74AHC595PWR at MSL 1, 260 °C, unlimited floor life, and DRV8833PWR at MSL 3, 260 °C, 168 hours. Identical bodies, different handling rules. Read the package option addendum for the exact orderable part and bake accordingly.
Reel quantities differ too, which matters when a minimum buy sets your build size. TI supplies 2000 pieces on a 330 mm reel; Diodes and NXP both specify 2500 on a 13 inch reel. All three use 12 mm carrier tape at 8 mm pocket pitch, and TI gives the TSSOP-16 cavity as A0 6.9 mm, B0 5.6 mm, K0 1.6 mm.
Table 5. TSSOP-16 designators by supplier
| Supplier | Package code | Notes |
| Texas Instruments | PW (TSSOP), PWP (HTSSOP) | Drawings PW0016A and PWP0016C |
| NXP / Nexperia | SOT403-1, SOT403-3 | 1.1 mm and 1.05 mm bodies; part suffix PW |
| Diodes Incorporated | TSSOP-16, TSSOP-16EP (Type DX) | Height capped at 1.08 mm |
| Infineon | PG-TSSOP-16-8 | Own outline and footprint drawings |
| Monolithic Power Systems | TSSOP-16 | MF-PO-D-0026, MO-153 variation AB |
| Renesas | PGG16 | Listed as TSSOP 16 |
| Toshiba | TSSOP16 | Land pattern to JEITA ET-7501 level 3 |
Approximate weight is a cheap incoming screen against remarked parts. Diodes gives 0.055 g for TSSOP-16 and 0.054 g for the exposed-pad version. A reel whose sample weight sits well outside that figure deserves X-ray or decapsulation before it reaches the line.
Seven design mistakes that send TSSOP-16 boards back
- Pulling a footprint from a generic library without checking Z and G against the device drawing. The 0.60 mm span spread in Table 2 is real.
- Specifying a 0.45 mm pad, then trying to route between pads. The channel is 0.20 mm.
- Assuming TSSOP-14 and TSSOP-16 are visually distinguishable. They share a body.
- Sizing copper for a plain TSSOP-16 as though it had an exposed pad. RθJC bottom is not specified for the PW package for a reason.
- Letting an MSL 3 reel sit past 168 hours of floor life, then reflowing it without a bake.
- Reusing an RθJA number from a datasheet revision that predates the current characterisation.
- Wave soldering onto a reflow-sized land without adding 0.2 mm to Z.
TSSOP-16 FAQ
What does TSSOP-16 stand for?
TSSOP stands for thin shrink small outline package, and 16 is the lead count. “Thin” refers to the 1.2 mm maximum height; “shrink” refers to the 0.65 mm pitch, half the 1.27 mm pitch of a standard SOIC. The leads are gull-wing formed and split evenly, eight per side.
What is the pitch of a TSSOP-16 package?
0.65 mm, specified as basic on every drawing referenced here, giving 14 spaces across the two rows. The wider TSSOP family also includes 0.5 mm pitch bodies, but a 16-lead part built to MO-153 variation AB is 0.65 mm. Always confirm against the specific vendor drawing before committing a footprint.
Is TSSOP-16 the same as SSOP-16?
No. Both use 0.65 mm pitch, but SSOP-16 is larger in every other axis. On TI drawings, SSOP-16 (DB0016A) has a 5.3 mm body width, 7.4 mm to 8.2 mm lead span and 2.0 mm maximum height, against 4.4 mm, 6.2 mm to 6.6 mm and 1.2 mm for TSSOP-16. The land patterns are not interchangeable.
Can you hand-solder a TSSOP-16?
Yes. At 0.65 mm pitch the leads are visible and reachable with a fine tip. Tack two opposite corners, then drag-solder each row and wick the excess. Because the joints stay inspectable under a stereo microscope, TSSOP-16 remains the practical choice for prototype and low-volume work where WQFN would need X-ray.
Does the TSSOP-16 package have a thermal pad?
The standard TSSOP-16 does not. Exposed-pad versions exist under separate designators: HTSSOP-16 or PWP at TI, TSSOP-16EP Type DX at Diodes. Lead geometry and lead land pattern are identical, so the difference on your board is a thermal land, a via field and a much lower junction-to-ambient resistance.
What is the footprint size for TSSOP-16?
Using the TI pattern, the copper occupies about 7.30 mm across the pad rows by 5.0 mm along them, so roughly 37 mm² before courtyard. Diodes calls for 6.80 mm across and Richtek 7.00 mm. Budget an 8 mm × 6 mm placement envelope and confirm against the drawing for the device you are buying.
What to do next
Choose TSSOP-16 when mounted height must stay under 1.2 mm, dissipation stays below roughly 0.4 W at your worst-case ambient, and your fabricator holds 0.10 mm lines and spaces. Take the land pattern from the device manufacturer’s drawing, not a library default, and verify Z and G against Table 2 before release.
If the thermal margin is anywhere near the edge, specify the exposed-pad variant at layout time. The lead pattern is identical, so the change costs one copper pour and a via field today, instead of a re-spin after the first thermal chamber run.
Sources
- Texas Instruments, PW0016A package drawing 4220204/B, MPDS361B: https://www.ti.com/lit/pdf/MPDS361B
- Texas Instruments, SN74AHC595 datasheet SCLS373N: https://www.ti.com/lit/ds/symlink/sn74ahc595.pdf
- Texas Instruments, DRV8833 datasheet SLVSAR1E, including PWP0016C: https://www.ti.com/lit/ds/symlink/drv8833.pdf
- Diodes Incorporated, TSSOP-16 package information, rev. 2017-04-04: https://www.diodes.com/assets/Package-Files/TSSOP-16.pdf
- Diodes Incorporated, TSSOP-16EP Type DX, rev. 2018-08-10: https://www.diodes.com/assets/Package-Files/TSSOP-16EP-Type-DX.pdf
- Monolithic Power Systems, 16-TSSOP outline MF-PO-D-0026 rev. 1.0: https://media.monolithicpower.com/cms_document/Package%20Information/TSSOP-16%20POD.pdf
- Richtek, TSSOP-16 footprint drawing: https://www.richtek.com/assets/podfiles/Footprint-TSSOP-16.pdf
- NXP Semiconductors, SOT403-1 TSSOP16 package summary: https://www.nxp.com/packages/SOT403-1?lang=en
Internal links to place
- [INTERNAL LINK: SOIC-16 package dimensions -> SOIC package dimensions and footprint guide]
- [INTERNAL LINK: IPC-7351 land pattern density levels -> IPC-7351 footprint standard explainer]
- [INTERNAL LINK: moisture sensitivity level and floor life -> J-STD-020 MSL handling guide]
- [INTERNAL LINK: thermal vias under an exposed pad -> exposed-pad thermal design guide]
- [INTERNAL LINK: reading a JEDEC package outline drawing -> JEDEC package outline explainer]
