A TSSOP package is a plastic gull-wing surface-mount package on 0.65 mm pitch with a 1.2 mm maximum height, registered under JEDEC MO-153. Texas Instruments’ 16-lead PW outline measures 4.9 to 5.1 mm long by 4.3 to 4.5 mm wide with a 6.2 to 6.6 mm lead span. Below: real dimensions, the land pattern the manufacturer publishes, and what the package costs you thermally against HTSSOP and QFN.
Key takeaways
- Standard pitch is 0.65 mm and maximum seated height is 1.2 mm. Body widths run 4.4 mm for most parts, with 0.5 mm pitch used on the higher lead counts.
- JEDEC MO-153 registers lead counts up to 68. Several widely cited references stop at 56, which is wrong.
- The thermal penalty for choosing plain TSSOP over an exposed-pad version is large. On the same die, TI measures 103.1 °C/W for the TSSOP against 40.5 °C/W for the HTSSOP.
- That penalty is a current rating in practice: the same part is specified at 500 mA RMS per bridge in TSSOP and 1.5 A RMS in HTSSOP.
- TI’s published land pattern for the 16-lead TSSOP package is 0.45 mm by 1.5 mm pads on 0.65 mm pitch with 5.8 mm between pad-row centres.
- Typical qualification is MSL 3 with a 260 °C peak reflow, and 16-lead parts ship 2,000 per reel on 12 mm tape.
What a TSSOP package is
A TSSOP package is a plastic surface-mount package with gull-wing leads on two sides, 0.65 mm lead pitch and a seated height capped at 1.2 mm. The name expands to Thin Shrink Small Outline Package: shrink for the pitch, thin for the height class. JEDEC registers the outline family as MO-153.
The naming is descriptive rather than dimensional, which causes trouble. SSOP shares the 0.65 mm pitch. VSSOP and MSOP also use 0.65 mm on TI parts. What separates the TSSOP package is the height ceiling combined with a 4.4 mm body width on the mainstream parts. Pitch alone will not identify it, and a part marked SSOP will not drop into a TSSOP land pattern at the same lead count.
JEDEC’s own index lists MO-153 lead counts as 8, 14, 16, 20, 24, 28, 36, 40, 48, 52, 56, 60, 64 and 68. Several widely copied reference pages state a range of 8 to 56 leads, which understates the family by two registered sizes and misses parts that exist and ship.
[IMAGE 1: dimensioned outline of a 16-lead TSSOP showing D, E1, E, e, L and A | alt: “TSSOP package dimensions diagram showing 5 mm body, 4.4 mm width, 6.4 mm lead span and 0.65 mm pitch”]
TSSOP package dimensions
The values below are from TI package outline drawing PW0016A, revision 4220204/B, December 2023, for the 16-lead TSSOP package. All in millimetres. The drawing references JEDEC MO-153.
| Symbol | Parameter | Min | Max | Note |
| A | Seated height | — | 1.20 | Defines the package class |
| A1 | Standoff | 0.05 | 0.15 | |
| D | Body length | 4.90 | 5.10 | Excludes mold flash, 0.15 mm per side |
| E1 | Body width | 4.30 | 4.50 | Excludes interlead flash, 0.25 mm per side |
| E | Lead span, tip to tip | 6.20 | 6.60 | Typical dimension on the drawing |
| e | Lead pitch | — | 0.65 | 14 spaces on a 16-lead part |
| b | Lead width | 0.17 | 0.30 | |
| L | Foot length | 0.50 | 0.75 | |
| — | Gage plane offset | — | 0.25 | Foot angle 0° to 8° |
| — | Lead row half-span | — | 4.55 | 2 x 4.55 across the outer leads |
Two numbers get misused. The 4.4 mm body width is what datasheets quote, but the pads have to reach the lead span, which is 6.2 mm to 6.6 mm. And the mold flash allowances are separate: 0.15 mm per side on the length, 0.25 mm per side across the width. A part that measures 5.4 mm long under calipers is still inside the drawing.
Lead width runs 0.17 mm to 0.30 mm. That range matters because pad width has to cover the maximum while leaving mask clearance on 0.65 mm pitch, and the answer is tight enough that the manufacturer publishes it rather than leaving it to the designer.
Body sizes outside 4.4 mm exist. The 64-lead TSSOP package sits on a 17 mm by 6.1 mm body at 0.5 mm pitch, which is a different assembly problem from the 16-lead part and should not be treated as the same package with more leads.
What plain TSSOP costs you thermally
The most useful comparison is not between package families on paper but between package options on one part number, because the die and the test conditions are held constant. TI’s DRV8833 motor driver ships in TSSOP, HTSSOP and WQFN, and the datasheet, revision E, July 2015, publishes the thermal metrics side by side.
| Thermal metric (DRV8833) | TSSOP (PW), 16 | HTSSOP (PWP), 16 | WQFN (RTY), 16 |
| Body size | 5.00 x 4.40 mm | 5.00 x 4.40 mm | 4.00 x 4.00 mm |
| RθJA, junction to ambient | 103.1 °C/W | 40.5 °C/W | 37.2 °C/W |
| RθJC (top) | 38 °C/W | 32.9 °C/W | 34.3 °C/W |
| RθJB, junction to board | 48.1 °C/W | 28.8 °C/W | 15.3 °C/W |
| RθJC (bottom) | not applicable | 4.8 °C/W | 3.5 °C/W |
| ψJB | 47.5 °C/W | 11.5 °C/W | 15.4 °C/W |
| Rated output per bridge | 500 mA RMS | 1.5 A RMS | 1.5 A RMS |
| Rated output, bridges paralleled | 1 A RMS | 3 A RMS | 3 A RMS |
Junction-to-ambient resistance is 2.5 times worse in the plain TSSOP package than in the exposed-pad version of the same device. TI translates that directly into a specification limit rather than leaving it as a layout exercise: 500 mA RMS per bridge in the TSSOP, against 1.5 A RMS in the HTSSOP and WQFN. Paralleled, the gap is 1 A against 3 A.
The datasheet is blunt about why. The PW option is not thermally enhanced, and TI directs designers to the dissipation limits rather than to heatsinking techniques. Copper pour under a plain TSSOP helps at the margins, because the only paths out are the leads and the top surface, and the junction-to-board figure of 48.1 °C/W shows how weak the lead path is.
Read this as a selection rule. If the part dissipates more than a few hundred milliwatts, the choice between TSSOP and HTSSOP is not a footprint preference; it changes what the part is rated to do.
TSSOP package against SOIC, VSSOP and QFN
Where the TSSOP package sits against its neighbours is a question of pitch, height and board area. Cells marked not read here were not present in the drawings opened for this article, and are left blank rather than filled from memory.
| Package | Pitch | Max height | Lead span | Body width |
| TSSOP (TI PW), 16 lead | 0.65 mm | 1.20 mm | 6.2 to 6.6 mm | 4.3 to 4.5 mm |
| HTSSOP (TI PWP), 16 lead | 0.65 mm | 1.20 mm | 6.2 to 6.6 mm | 4.3 to 4.5 mm |
| VSSOP / MSOP (TI DGK) | 0.65 mm | 1.10 mm | 4.75 to 5.05 mm | not read here |
| SOIC narrow (JEDEC MS-012) | 1.27 mm | not read here | not read here | 3.9 mm |
| SOIC wide (TI DW), 16 lead | 1.27 mm | 2.65 mm | not read here | 7.5 mm |
| WQFN (TI RTY), 16 lead | no leads | not read here | no leads | 4.00 x 4.00 mm |
The practical ordering is straightforward. SOIC buys assembly margin at 1.27 mm pitch and costs height and area. The TSSOP package halves the pitch and caps height at 1.2 mm. VSSOP and MSOP shave another 0.1 mm of height and roughly 1.5 mm of lead span at the same pitch. QFN removes the leads entirely and wins on thermal path, at the cost of X-ray inspection.
One trap: SOIC wide body at 2.65 mm maximum height is more than twice the TSSOP ceiling. Designs with a stack-up height budget, card slots or shielding cans usually fail on that number rather than on area.
TSSOP package footprint and land pattern
TI publishes a land pattern on the same drawing as the outline, which removes most of the guesswork. For PW0016A the pads are 0.45 mm wide and 1.5 mm long on 0.65 mm pitch, with 5.8 mm between the centres of the two pad rows.
| Land and stencil parameter (16-lead TSSOP package) | Value |
| Pad pitch | 0.65 mm |
| Pad size | 0.45 mm wide x 1.50 mm long |
| Distance between pad-row centres | 5.80 mm |
| Outer edge to outer edge (Z) | 7.30 mm |
| Inner edge to inner edge (G) | 4.30 mm |
| Pad-to-pad gap | 0.20 mm |
| Pad-row length, first to last pad centre | 9.10 mm |
| Stencil aperture | 1:1 with the pad, 0.125 mm foil |
| Area ratio at 0.125 mm foil | 1.39 |
| Solder mask | Non-solder-mask defined preferred, 0.05 mm clearance all around |
Work out what those numbers give you. Pads centred 5.8 mm apart and 1.5 mm long put the outer edges 7.30 mm apart and the inner edges 4.30 mm apart. Against a maximum lead span of 6.6 mm that is 0.35 mm of toe extension. Against a minimum span of 6.2 mm with the longest 0.75 mm foot, the heel sits 2.35 mm from centre and the pad inner edge at 2.15 mm, leaving 0.20 mm of heel fillet at the worst stack.
Stencil design follows the pad one to one. A 0.45 mm by 1.5 mm aperture in 0.125 mm foil gives an area ratio of 0.675 / (2 x 1.95 x 0.125) = 1.39, well clear of the 0.66 release threshold. There is no reason to shrink apertures on this package; bridging at 0.65 mm comes from placement offset and paste slump, not from over-deposit.
Use non-solder-mask-defined pads with 0.05 mm clearance all around. TI marks this as the preferred construction on the drawing, and it is the right call at a 0.20 mm pad gap, where a mask-defined pad would need a dam narrower than most fabricators guarantee.
[IMAGE 2: land pattern with pad size, pitch and row spacing called out | alt: “TSSOP package footprint with 0.45 mm by 1.5 mm pads on 0.65 mm pitch”]
HTSSOP: the exposed-pad version
The exposed-pad version changes the board work more than it changes the outline. On TI’s PWP0016C drawing the signal pads are identical to the plain part. What is added underneath is a thermal pad measuring 2.31 mm by 1.75 mm at minimum, with a 2.46 mm by 1.75 mm variant, and TI notes that the metal size can vary with creepage requirements.
The recommended board land for that pad is 3.4 mm by 5 mm of copper with 0.2 mm vias on roughly 1.2 mm centres. Those vias are the heat path to the plane; without them the exposed pad is a solder joint that goes nowhere.
Paste volume over a large thermal pad is the failure mode that actually shows up in production. Print 100 percent of the pad area and the package floats, tilts and opens signal joints. TI handles this by scaling the thermal aperture against stencil thickness so the deposited volume stays roughly constant.
| Stencil thickness | Thermal pad aperture | Change against the 0.125 mm case |
| 0.100 mm | 2.75 x 2.58 mm | Larger opening, thinner deposit |
| 0.125 mm | 2.46 x 2.31 mm | Reference case on the drawing |
| 0.150 mm | 2.25 x 2.11 mm | Smaller opening, thicker deposit |
| 0.175 mm | 2.08 x 1.95 mm | Smallest opening, thickest deposit |
Two rules go with that table. Vias under the paste area must be filled, plugged or tented, or solder wicks down them and leaves voids in the thermal joint. And the aperture on the drawing is a single opening on a small pad; on larger thermal pads the same volume target is usually met with a segmented window instead.
[IMAGE 3: HTSSOP thermal land showing copper area, via grid and stencil window | alt: “HTSSOP thermal pad land pattern with 0.2 mm thermal vias under an exposed pad”]
Reflow, moisture and packing
Qualification for the TSSOP package follows the same profile as the rest of the thin leadframe family. TI lists the DRV8833 tape-and-reel TSSOP and HTSSOP options at moisture sensitivity level 3 with a 260 °C peak reflow and 168 hours of floor life, with a NiPdAu lead finish and RoHS status yes.
Packing differs by package in a way that affects line changeover. The 16-lead TSSOP and HTSSOP parts ship 2,000 per reel on 12 mm tape with 8 mm pocket pitch, cavity 6.9 mm by 5.6 mm by 1.6 mm deep. The 16-lead WQFN version of the same device ships 3,000 per reel on the same tape width with a 4.25 mm square cavity.
Lifecycle risk sits at the packing level rather than the package level. On the DRV8833, the tube TSSOP option is marked obsolete while the tape-and-reel option remains active production. A BOM line that specifies the tube part number fails; the same silicon in the same package on a reel does not.
For inspection, the TSSOP package is one of the last high-pin-count options where every joint is visible. That is worth real money on conformal-coated, low-volume or field-repairable hardware, and it is the main reason to keep it over QFN when thermal performance is not the deciding factor.
How to choose
Work through the constraints in this order.
- Height budget under 1.2 mm and a lead count between 8 and 68: the TSSOP package is the default. Below about 10 leads, check whether VSSOP or MSOP saves useful area at the same pitch.
- Dissipation above roughly 0.5 W, or a datasheet that lists separate current ratings per package: take the exposed-pad version and budget the thermal land, the vias and the stencil work. The plain package will be derated.
- Inspection or rework access required, for conformal coat, field service or low volume: keep TSSOP over QFN. Every joint stays visible and reworkable with an iron.
- Thermal path is the dominant requirement and X-ray is available: QFN beats both, at 37.2 °C/W against 40.5 °C/W for HTSSOP on the reference device, in a smaller body.
- Hand assembly or wave-adjacent processes: SOIC at 1.27 mm pitch remains easier. Only accept the height and area penalty if the build genuinely needs it.
- Before release, confirm the fabricator will hold a 0.20 mm gap between non-solder-mask-defined pads, and confirm the stencil house has the aperture set matched to the foil thickness actually being used.
Frequently asked questions
What does TSSOP stand for?
Thin Shrink Small Outline Package. Shrink refers to the lead pitch, which is 0.65 mm rather than the 1.27 mm used by SOIC. Thin refers to the height class, capped at 1.2 mm seated. The combination is registered by JEDEC as outline MO-153.
What is the pitch of a TSSOP package?
0.65 mm on nearly all parts. A 0.5 mm variant exists for the higher lead counts, such as the 64-lead version on a 17 mm by 6.1 mm body. Pitch alone does not identify the package, since SSOP and VSSOP also use 0.65 mm.
What is the difference between TSSOP and SSOP?
Height and body. Both commonly use 0.65 mm pitch, but TSSOP is capped at 1.2 mm seated height and standardises on a 4.4 mm body width. SSOP is taller and is offered in wider bodies. The two are not footprint compatible at the same lead count.
What is HTSSOP?
A TSSOP with an exposed thermal pad on the underside, marketed by TI as PowerPAD. The pad on the 16-lead version measures 2.31 mm by 1.75 mm at minimum. It must be soldered to a copper land, not left floating, or the thermal advantage disappears entirely.
Can you hand-solder a TSSOP package?
Yes. At 0.65 mm the pads are 0.45 mm wide with a 0.20 mm gap, which drag-solders cleanly with flux and braid. The exposed-pad version is a different problem, since the underside pad cannot be reached with an iron and needs hot air or a preheater.
Is TSSOP being phased out?
No. It remains in current production across logic, analog and driver families. Individual packing options do get retired: on the TI DRV8833, for example, the tube version of the TSSOP part is marked obsolete while the tape-and-reel version stays active.
What to do next
Specify the exposed-pad version whenever the datasheet gives the package its own current or dissipation rating. The thermal numbers on the reference device make that a 2.5 times difference in junction-to-ambient resistance and a threefold difference in rated output, which no amount of copper pour under a plain package recovers.
Where dissipation is not the constraint, the plain TSSOP package is still the sensible default for anything between 8 and 68 leads under a 1.2 mm height budget. Draw the footprint from the manufacturer drawing rather than a generic library part, hold 0.45 mm by 1.5 mm pads at 5.8 mm row spacing, and print the stencil one to one at 0.125 mm foil.
