The TSOP-86 package is an 86-lead thin small outline package, Type II, on a 22.22 mm by 10.16 mm body with a 1.20 mm maximum height and 0.50 mm lead pitch. It carried the x32 SDR SDRAM generation and nothing after it. Below are verified dimensions, the full 86-lead pin assignment, a land pattern worked from the drawing tolerances, and what is actually in stock.
Key takeaways
- Body is 22.22 mm x 10.16 mm with 1.20 mm maximum height and 11.76 mm nominal lead span. Identical outline to the 54 and 66-lead TSOP II parts; only the pitch changes.
- Pitch is 0.50 mm and pin 1 sits 0.61 mm from the body end. On the 66-lead part that offset is 0.71 mm, which is the fastest way to tell two identical-looking footprints apart.
- At 0.50 mm this package is genuinely fine pitch under IPC-7351, unlike the 66-lead version at 0.65 mm. Land, stencil and placement rules tighten accordingly.
- Twenty-four of the 86 leads are supply or return, and six are no-connect. Only 56 leads carry signal.
- Body volume is roughly 271 mm³ at under 1.6 mm thick, so J-STD-020 Table 4-2 puts the Pb-free classification temperature at 260 °C.
- Alliance Memory is the only broad-line source still shipping. ISSI and Micron x32 TSOP parts are flagged obsolete at DigiKey, and no DDR generation ever used this package.
What the TSOP-86 package actually is
The TSOP-86 package is an 86-lead thin small outline package, Type II, with gull-wing leads on the long edges. The body measures 22.22 mm by 10.16 mm, stands 1.20 mm tall at most, and uses 0.50 mm lead pitch across a 11.76 mm nominal lead span. It was the leaded package for x32 SDR SDRAM.
Samsung states the outline plainly on the K4S643232H datasheet, rev 1.2, April 2006: 86-pin TSOP (II), 400 mil by 875 mil, 0.5 mm pin pitch. Alliance Memory publishes the full dimension table on the AS4C4M32SA datasheet, rev 1.0, September 2015. Both describe the same package.
The 875 mil figure is 22.22 mm, the body length. The 400 mil figure is the body width. Neither is the dimension a footprint has to reach, which is the 11.76 mm lead span. Distributor listings quote 22.42 mm by 10.29 mm for some x32 parts; that length exceeds the 22.35 mm maximum on the Alliance drawing because the drawing excludes interlead flash and the listing does not.
[IMAGE 1: dimensioned outline of the 86-lead TSOP II showing D, E, HE, e, L and A | alt: “TSOP-86 package dimensions diagram showing 22.22 mm body, 10.16 mm width, 11.76 mm lead span and 0.50 mm pitch”]
TSOP-86 package dimensions
Values below are from the package outline drawing in Alliance Memory’s AS4C4M32SA datasheet, rev 1.0, September 2015. All in millimetres.
| Symbol | Parameter | Min | Nom | Max | Note |
| A | Overall height | — | — | 1.20 | Same ceiling as 54 and 66-lead |
| A1 | Standoff | 0.05 | 0.10 | 0.20 | Body sits 0.05 mm off the board worst case |
| A2 | Body thickness | 0.90 | 1.00 | 1.10 | |
| D | Body length | 22.09 | 22.22 | 22.35 | Excludes interlead flash |
| E | Body width (400 mil) | 10.03 | 10.16 | 10.29 | Excludes interlead flash |
| HE | Lead span, tip to tip | 11.56 | 11.76 | 11.96 | The dimension the pads must reach |
| e | Lead pitch | — | 0.50 | — | 0.0197 in |
| B | Lead width | 0.17 | 0.22 | 0.27 | Excludes dambar protrusion |
| C | Lead thickness | — | 0.127 | — | |
| L | Foot length | 0.40 | 0.50 | 0.60 | |
| L1 | Formed lead length | — | 0.80 | — | |
| S | Body end to pin 1 centre | — | 0.61 | — | Includes end flash |
| y | Coplanarity | — | — | 0.10 | Across all 86 leads |
| θ | Lead foot angle | 0° | — | 8° |
Check the pin 1 offset before trusting any library part. Forty-three leads at 0.50 mm pitch span 42 x 0.50 = 21.00 mm. Subtract that from the 22.22 mm body, halve the remainder, and pin 1 falls 0.61 mm from the body end, which is exactly the S dimension the drawing publishes. On the 66-lead package the same arithmetic gives 0.71 mm.
Two dimensions differ from the 66-lead part in ways that matter downstream. Lead width B runs 0.17 mm to 0.27 mm here against 0.22 mm to 0.45 mm on the 66-lead drawing, so the lead is both narrower and more tightly toleranced. Lead thickness C is 0.127 mm nominal. Narrow, thin leads bend easily in trays, and coplanarity is still held to 0.10 mm across all 86 of them.
TSOP-86 pinout
Leads split 43 per side. The assignment below is Alliance Memory’s AS4C4M32SA, a 128 Mb 4M x 32 SDR SDRAM, top view. The x32 members of the family share it, which is what allowed the Samsung, Micron and ISSI parts in the cross reference further down to act as drop-in alternatives.
| Pin | Signal | Pin | Signal |
| 1 | VDD | 44 | VSS |
| 2 | DQ0 | 45 | DQ24 |
| 3 | VDDQ | 46 | VSSQ |
| 4 | DQ1 | 47 | DQ25 |
| 5 | DQ2 | 48 | DQ26 |
| 6 | VSSQ | 49 | VDDQ |
| 7 | DQ3 | 50 | DQ27 |
| 8 | DQ4 | 51 | DQ28 |
| 9 | VDDQ | 52 | VSSQ |
| 10 | DQ5 | 53 | DQ29 |
| 11 | DQ6 | 54 | DQ30 |
| 12 | VSSQ | 55 | VDDQ |
| 13 | DQ7 | 56 | DQ31 |
| 14 | NC | 57 | NC |
| 15 | VDD | 58 | VSS |
| 16 | DQM0 | 59 | DQM3 |
| 17 | WE# | 60 | A3 |
| 18 | CAS# | 61 | A4 |
| 19 | RAS# | 62 | A5 |
| 20 | CS# | 63 | A6 |
| 21 | A11 | 64 | A7 |
| 22 | BA0 | 65 | A8 |
| 23 | BA1 | 66 | A9 |
| 24 | A10 / AP | 67 | CKE |
| 25 | A0 | 68 | CLK |
| 26 | A1 | 69 | NC |
| 27 | A2 | 70 | NC |
| 28 | DQM2 | 71 | DQM1 |
| 29 | VDD | 72 | VSS |
| 30 | NC | 73 | NC |
| 31 | DQ16 | 74 | DQ8 |
| 32 | VSSQ | 75 | VDDQ |
| 33 | DQ17 | 76 | DQ9 |
| 34 | DQ18 | 77 | DQ10 |
| 35 | VDDQ | 78 | VSSQ |
| 36 | DQ19 | 79 | DQ11 |
| 37 | DQ20 | 80 | DQ12 |
| 38 | VSSQ | 81 | VDDQ |
| 39 | DQ21 | 82 | DQ13 |
| 40 | DQ22 | 83 | DQ14 |
| 41 | VDDQ | 84 | VSSQ |
| 42 | DQ23 | 85 | DQ15 |
| 43 | VDD | 86 | VSS |
The pin budget explains why an x32 device needs 86 leads for a 32-bit bus. Thirty-two DQ lines, four byte masks (DQM0 to DQM3), twelve address lines, two bank selects and six command lines account for 56 leads. Another 24 are supply and return: four VDD, four VSS, eight VDDQ and eight VSSQ. Six leads are no-connect (14, 30, 57, 69, 70 and 73).
Note what is absent. There is no VREF and no data strobe, because this is an LVTTL SDR interface clocked on the rising edge of CLK only. DQM3 masks DQ31 to DQ24, DQM2 masks DQ23 to DQ16, DQM1 masks DQ15 to DQ8 and DQM0 masks DQ7 to DQ0. Wire the masks to the wrong byte lane and the part still passes a memory test that writes and reads full words.
[IMAGE 2: pin 1 corner detail showing the 0.61 mm offset and lead numbering | alt: “TSOP-86 pinout showing pin 1 located 0.61 mm from the package end”]
TSOP-86 footprint and land pattern
The outer geometry is fixed by the lead span, which is identical to the 66-lead package. Half of HE runs 5.78 mm to 5.98 mm. Subtract foot length L at 0.40 mm to 0.60 mm and the heel sits between 5.18 mm and 5.58 mm from the centreline. Pads running from 4.85 mm to 6.35 mm cover every combination.
| Land pattern parameter | Value |
| Pad pitch | 0.50 mm (fixed by the package) |
| Pads per row | 43, two rows |
| Row length, first to last pad centre | 21.00 mm |
| Pad width | 0.30 mm |
| Pad length | 1.50 mm |
| Outer span, pad outer edge to outer edge (Z) | 12.70 mm |
| Inner gap, pad inner edge to inner edge (G) | 9.70 mm |
| Worst-case toe fillet | 0.37 mm |
| Worst-case heel fillet | 0.33 mm |
| Pad-to-pad gap | 0.20 mm |
| Courtyard | 12.70 mm x 22.35 mm plus assembly clearance |
That produces 0.37 mm of toe extension and 0.33 mm of heel extension at the worst tolerance stack. Anyone migrating a design from the 66-lead package can keep the outer pad geometry unchanged and alter only pitch, pad width and pad count, because Z and G come out identical.
Pad width is where the two packages part company. Lead width maxes at 0.27 mm, so a 0.30 mm pad on 0.50 mm pitch leaves a 0.20 mm gap. That is at or below the minimum solder mask dam many fabricators will guarantee, so expect to specify an open mask window over each lead row rather than individual dams. IPC-7351 names the geometry SOP50P1176X120-86N.
The 0.50 mm pitch also crosses IPC’s fine-pitch boundary at 0.625 mm, which the 66-lead package at 0.65 mm does not. That change moves the part into the fine-pitch gull-wing land table, where the side goal goes negative to absorb fabrication tolerance rather than adding pad width.
Stencil aperture of 0.30 mm by 1.50 mm in 0.12 mm foil gives an area ratio of 0.45 / (2 x 1.80 x 0.12) = 1.04, above the 0.66 release threshold with margin. Going thicker than 0.12 mm buys nothing here and raises bridging risk; the failure mode at this pitch is paste volume and placement offset, not starved release.
[IMAGE 3: land pattern drawing with Z, G, pad width and pitch called out | alt: “TSOP-86 footprint land pattern with 0.50 mm pitch, 0.30 mm pads and 12.70 mm outer span”]
TSOP-86 against the rest of the TSOP II family
Four TSOP II lead counts share the 400 mil body width, and three of them share the same 22.22 mm length. Pitch is the only thing separating their footprints, which is why substitution errors in this family are expensive.
| Package | Leads/side | Body D x E (mm) | Pitch | Pin 1 offset from body end |
| 44-pin TSOP II | 22 | 18.81 x 10.16 | 0.80 mm | not published in the sources checked |
| 54-pin TSOP II | 27 | 22.22 x 10.16 | 0.80 mm | not published in the sources checked |
| 66-pin TSOP II | 33 | 22.22 x 10.16 | 0.65 mm | 0.71 mm |
| 86-pin TSOP II | 43 | 22.22 x 10.16 | 0.50 mm | 0.61 mm |
The 86-lead and 66-lead parts are the dangerous pair. Same body, same lead span, same height, same courtyard. A 3D model will not distinguish them and neither will a mechanical fit check. The pin 1 offset does: 0.61 mm against 0.71 mm, or count leads across a 10 mm span and compare 20 against 15.
Renesas publishes the 54-lead drawing as 22.22 x 10.16 x 1.00 mm body at 0.80 mm pitch, and the 44-lead figures come from the TSOP2-44 entry at mbedded.ninja. Pin 1 offsets for those two were not published in the sources checked here.
Reflow, moisture and fine-pitch assembly
Reflow ceiling comes from package volume. At 22.22 x 10.16 x 1.20 the body is roughly 271 mm³ with a thickness of 1.20 mm. Both fall in the first cell of J-STD-020 Table 4-2, giving a Pb-free classification temperature of 260 °C. That matches the family; Alliance lists 260 °C soldering temperature as an absolute maximum on its DDR1 TSOP II parts.
Moisture sensitivity is not stated on the AS4C4M32SA datasheet. A parametric database entry for Alliance’s 54-lead SDR part lists MSL 3, and level 3 was the common rating for thin leadframe memory of this era, but read the dry-pack label for the lot in hand rather than working from the pattern.
Assembly risk sits higher than on the coarser TSOP II parts for two compounding reasons. The pitch halves the clearance between adjacent joints, and the leads are narrower and thinner, so they deform more readily during handling. Parts that have been out of tray, reclaimed from boards, or shipped loose are the usual source of coplanarity failures at 0.50 mm.
For rework, use hot air with a nozzle sized to the 22 mm body and a preheated board. Drag soldering works at 0.50 mm with good flux, but inspection has to be angled to see the heel fillet, and an unwetted heel on a x32 bus shows up as an intermittent byte lane rather than a dead board.
Sourcing an 86-pin TSOP II part in 2026
Alliance Memory’s 2026 product catalogue lists 86-pin TSOP II across the x32 SDR range: 64 Mb (2M x 32), 128 Mb (4M x 32), 256 Mb (8M x 32) and 512 Mb (16M x 32), all at 3.3 V and 143 or 166 MHz. The 512 Mb entry, AS4C16M32SC-7TIN, is industrial grade only at 143 MHz.
| Density | Org | Alliance | Samsung | Micron (obsolete) | ISSI |
| 64 Mb | 2M x 32 | AS4C2M32SA-6/7TxN | K4S643232H-UCxx | MT48LC2M32B2P-x | IS42S32200 |
| 128 Mb | 4M x 32 | AS4C4M32SA-6/7TxN | — | MT48LC4M32B2P-x | IS42S32400 |
| 256 Mb | 8M x 32 | AS4C8M32S-6/7TxN | — | MT48LC8M32B2B5-x (FBGA) | IS42S32800 |
| 512 Mb | 16M x 32 | AS4C16M32SC-7TIN | — | — | IS42S32160 |
Read the 256 Mb row with care. The Micron entry Alliance lists there carries a B5 suffix, which is an FBGA part, so it is a density and organization match rather than a package match. The unambiguous x32 TSOP parts are the MT48LC2M32B2P and MT48LC4M32B2P.
Stock in August 2026 tells a clear story. DigiKey shows Alliance AS4C4M32SA-6TIN at about 8.40 US dollars with roughly 2,500 units on hand, and AS4C4M32SA-7TCN at about 8.51 dollars with roughly 3,300 units, while ISSI IS42S32400F-7TL and Micron MT48LC4M32B2P are both flagged obsolete and no longer manufactured. Future Electronics lists the same Alliance part at 15.77 dollars in 108-piece trays with zero stock and a 16-week factory lead time.
That split matters for planning. Distributor shelf stock exists today, but the factory lead time behind it is four months, and only one manufacturer is feeding it. Treat any x32 TSOP II build as a last-time-buy candidate and size the order against the full product life rather than the next build. Broker-sourced parts at this pitch deserve incoming coplanarity inspection before they reach a placement machine.
When to keep TSOP-86 and when to move to FBGA
Apply the rules rather than a preference.
- Repairing or extending an existing x32 SDR board: keep the package, buy Alliance current production, and match the organization and speed grade rather than the package alone.
- New design that needs a 32-bit bus and can accept BGA: move to the 90-ball TFBGA version of the same density. It is a smaller board area, an easier land pattern, and the part sits on a broader supply base.
- New design that must stay leaded: TSOP-86 works, but plan around a 16-week factory lead time and a single manufacturer, and accept that the road stops at SDR SDRAM.
- Anything needing DDR bandwidth on a x32 bus: FBGA is the only option. No DDR generation was offered in this package.
- Assembly capability check before committing: confirm the fab will hold a 0.20 mm mask gap or agree to an open mask window, and confirm the line places at 0.50 mm pitch with vision alignment on 22 mm bodies.
Frequently asked questions
Is TSOP-86 the same as 86-pin TSOP II?
Yes. TSOP-86 is distributor shorthand for the 86-lead Type II thin small outline package, 400 mil body. Samsung writes it as 86-pin TSOP (II) 400 mil x 875 mil, 0.5 mm pin pitch. There is no Type I version of this lead count in production memory.
What is the pitch of a TSOP-86 package?
0.50 mm, with no tolerance published on the pitch itself. Forty-three leads per side give a 21.00 mm span from the first to the last lead centre, inside a 22.22 mm body. That leaves 0.61 mm from the body end to the pin 1 centre.
What size footprint does TSOP-86 need?
The pads reach 11.76 mm nominal lead span, not the 10.16 mm body. A worked land pattern gives 12.70 mm across the outer pad edges and 9.70 mm between inner edges, with 0.30 mm by 1.50 mm pads on 0.50 mm pitch. Row length is 21.00 mm.
What chips come in an 86-pin TSOP II package?
x32 SDR SDRAM, almost exclusively. Alliance lists 64 Mb through 512 Mb in 2M x 32, 4M x 32, 8M x 32 and 16M x 32 organizations. Samsung, Micron, ISSI, Winbond and Nanya all shipped equivalents. No DDR generation used the package.
Is TSOP-86 harder to assemble than TSOP-66?
Yes. At 0.50 mm it falls under IPC fine-pitch rules, where 0.65 mm does not. Pads drop to about 0.30 mm with a 0.20 mm gap, which pushes solder mask dams to the limit of most fabs and makes placement offset the dominant bridging cause.
What replaces an 86-pin TSOP II SDRAM?
For a x32 bus, a 90-ball or 144-ball FBGA. Alliance offers the same x32 densities in 90-ball TFBGA, and its x32 DDR parts are 144-ball FBGA only. Staying leaded means staying on SDR SDRAM, since the package never crossed into DDR.
What to do next
If a board already runs an 86-pin TSOP II SDRAM and the design has years left, buy Alliance now and size the buy against remaining production, not against the next run. One supplier and a four-month factory lead time is not a supply chain to schedule against.
If the design is new, put the x32 part in a 90-ball TFBGA and keep the leaded package only where inspection access or conformal coating genuinely requires it. And before any TSOP-86 layout is released, verify three numbers on the drawing: 0.50 mm pitch, 0.61 mm from body end to pin 1, and 11.76 mm lead span rather than the 10.16 mm body width.
