The TSOP-56 package is the largest member of the TSOP Type I family: 56 gull-wing leads on 0.50 mm pitch, 28 per short edge, a 14 mm body width and a 20 mm lead span. It is also a ceiling. One gigabit is the most parallel NOR flash you can buy in it, the part that gets there does so by stacking two dice, and everything larger exists only in a ball grid array.
Key takeaways
- Body 14 mm × 18.4 mm, lead span 20 mm, pitch 0.50 mm, maximum seated height 1.20 mm.
- 56 leads is the top of JEDEC MO-142. No larger Type I registration exists.
- 1 Gbit is the density ceiling for parallel NOR in this package, and Macronix reaches it with a two-die part.
- The leaded package costs roughly 3.5× the board area of the 9 × 9 mm BGA alternative for the same die.
- Infineon’s flash longevity program lists the S29GL-S family in 56-pin TSOP with support through October 2030.
- A longevity commitment is not stock. RS has already delisted the 1 Gbit 56-pin TSOP part.
[IMAGE 1: TSOP-56 outline with 28 leads per short edge, 20 mm lead span and 0.5 mm pitch dimensioned | alt: “TSOP-56 package dimensions showing 0.5 mm pitch, 14 mm body width and 20 mm lead span”]
What a TSOP-56 package is
A TSOP-56 package is a 56-lead thin small outline package, Type I, with 28 gull-wing leads on each of the two shorter edges at 0.50 mm pitch and a maximum seated height of 1.20 mm. Infineon and Cypress designate the outline TS056. It is used almost exclusively for high-density parallel NOR flash.
Fifty-six leads is where the Type I family stops. The JEDEC JEP95 index registers MO-142 at 24, 32, 40, 48 and 56 leads, with nothing above. A separate registration, MO-249, covers a thin small outline on an 8.89 mm body that also reaches 56, so confirm the body width before assuming which one you have.
TSOP-56 dimensions
| Parameter | Value | Source |
| Body width | 14 mm nominal, 14.1 mm max | Infineon TS056 outline; RS record for S29GL01GS |
| Body length | 18.4 mm nominal, 18.5 mm max | JCET TSOP brief; RS record |
| Lead span | 20.0 mm | Family convention, TS056 designated 14 × 20 mm |
| Pitch | 0.50 mm | Infineon TS056 outline |
| Leads per edge | 28 | — |
| Max seated height | 1.20 mm | JEDEC MO-142 family |
| Body thickness | 1.05 mm max | RS record for S29GL01GS |
The land pattern is the same one every 0.50 mm pitch Type I part uses, at 0.35 mm × 1.65 mm pads on a 19.25 mm row centreline. The derivation is on the TSOP Type I page. For 56 leads the only change is the array: 28 pads per row spanning 13.85 mm, which sits inside the 14 mm body with the family’s usual quarter-millimetre margin at each end.
The density ceiling, and how it is reached
Here is the fact that should drive the decision. Infineon’s GL-S family spans 128 Mbit, 256 Mbit, 512 Mbit and 1 Gbit, and the datasheet offers all of them in 56-pin TSOP. The 2 Gbit part in the same family, the S70GL02GS, is not offered in it.
Macronix reaches the same ceiling from the other side. Its application note AN0240, revision 3 dated 26 January 2018, notes that the MX68GL1G0G is a two-die solution. The 1 Gbit part in this package is not one die; it is a stack.
That tells you two things. The package has run out of room at the top of the parallel NOR range, and the industry answer at 1 Gbit was to stack rather than to grow the outline. Above 1 Gbit, parallel NOR is a ball grid array product and there is no leaded alternative.
Access time moves with density too. For the GL-S family at full VCC = VIO, the 128 Mbit and 256 Mbit parts specify 90 ns random access, while the 512 Mbit and 1 Gbit parts specify 100 ns. In VersatileIO mode those become 100 ns and 110 ns. Page access holds at 15 ns across the range.
What the leaded package costs in board area
The S29GL01GS ships in four packages: the 56-pin TSOP, a 64-ball LAA Fortified BGA at 13 mm × 11 mm, a 64-ball LAE Fortified BGA at 9 mm × 9 mm and a 56-ball VBU Fortified BGA at 9 mm × 7 mm. Same die, four outlines.
| Package | Outline | Area | Relative to TSOP-56 |
| 56-pin TSOP | 20.0 mm × 14.1 mm | 282 mm² | 1.0× |
| 64-ball LAA BGA | 13 mm × 11 mm | 143 mm² | 0.51× |
| 64-ball LAE BGA | 9 mm × 9 mm | 81 mm² | 0.29× |
| 56-ball VBU BGA | 9 mm × 7 mm | 63 mm² | 0.22× |
The leaded package occupies roughly three and a half times the board area of the 9 × 9 mm BGA, and four and a half times the smallest option. That is the price of keeping the joints visible.
It is often the right price. A TSOP-56 can be inspected optically, reworked with hot air and probed at the lead. None of that is true of a Fortified BGA. If your product is repaired in the field, built in low volume, or has to pass a visual inspection regime, the area is worth paying.
[IMAGE 2: TSOP-56 and the three BGA alternatives drawn to scale on one board outline | alt: “TSOP-56 package compared with 64-ball and 56-ball Fortified BGA outlines by board area”]
Cross-vendor pin compatibility
The 56-lead footprint has something the smaller TSOP sizes mostly lack: documented compatibility across two suppliers. Macronix states in AN0240 that the 56-TSOP and 64-LFBGA packages of its MX29GL-G and Infineon’s S29GL-S are pin compatible, and that the MX29GL-G is command compatible with the S29GL-S.
The note also records the exceptions, which is what makes it usable. Ball G8, carrying A25, is a no-connect on both the MX29GL512G and the S29GL512S. On the LFBGA, pin F7 is BYTE# on the Macronix part and can be left unconnected for x16 operation because it carries an internal pull-up.
Read the differences table rather than the headline. Pin compatible in a vendor application note means compatible with named exceptions, and those exceptions are the ones that bite.
Other vendors have shipped this package as well. Intel and Micron’s JS28F256P30TF, a 256 Mbit 1.8 V part organized 16M × 16 with 110 ns access, is a 56-pin TSOP device.
Lifecycle: a commitment to 2030 and a delisting today
Two facts sit in tension, and both are true.
Infineon’s flash memory product longevity program lists the S29GL-S family, covering the S29GL064S through S29GL01GS, in 56-pin TSOP and 64-ball BGA with support running to October 2030. That is a dated supply commitment on a leaded package, and it is longer than anything else in the TSOP family.
At the same time, RS has delisted the S29GL01GS10TFI010, the 1 Gbit 56-pin TSOP part, across two separate catalog records. Both now read that the product will no longer be stocked.
The lesson is not that one source is wrong. A longevity program is a commitment from the manufacturer to keep building; distributor delisting is a decision about shelf space. Design against the longevity program, buy against live stock, and expect to order through a franchised distributor or the factory rather than a catalog house.
Five mistakes on TSOP-56 designs
- Planning a density upgrade path inside the package. 1 Gbit is the ceiling. The next step is a BGA and a board spin.
- Assuming one die. The 1 Gbit Macronix part is a two-die stack, which changes nothing electrically and everything about how you read the reliability data.
- Taking “pin compatible” at face value. AN0240 lists named exceptions. Read them.
- Confusing the two 56-lead registrations. MO-142 and MO-249 both reach 56 on different bodies.
- Treating a longevity commitment as availability. The 1 Gbit part is committed to 2030 and already delisted at one distributor.
TSOP-56 FAQ
What are TSOP-56 package dimensions?
Body 14 mm wide, 14.1 mm maximum, by 18.4 mm long, 18.5 mm maximum; lead span 20.0 mm; lead pitch 0.50 mm; maximum seated height 1.20 mm; body thickness up to 1.05 mm. Twenty-eight leads sit on each of the two shorter edges. Infineon designates the outline TS056.
Is TSOP-56 Type I or Type II?
Type I. The leads emerge from the two shorter 14 mm edges, so the lead span runs along the 20 mm axis. Fifty-six is the largest lead count JEDEC registers under MO-142, the Type I registration. No 56-lead Type II outline exists.
What is the largest flash memory available in TSOP-56?
One gigabit. Infineon’s S29GL01GS and Macronix’s MX68GL1G0G both reach it, the latter as a two-die solution. The 2 Gbit parts in the same families are offered only in ball grid array packages, so 1 Gbit is a genuine ceiling rather than a current gap.
How much bigger is TSOP-56 than the BGA version?
About three and a half times. The 56-pin TSOP occupies roughly 282 mm² of board outline against 81 mm² for the 64-ball LAE Fortified BGA at 9 mm × 9 mm, and 63 mm² for the 56-ball VBU at 9 mm × 7 mm. The same die is available in all of them.
Is TSOP-56 obsolete?
No, but it is mature and thinning at distribution. Infineon’s longevity program commits the S29GL-S family in this package to October 2030, while RS has already delisted the 1 Gbit part. Design against the manufacturer commitment and confirm live stock through a franchised distributor.
Choosing TSOP-56
Specify TSOP-56 when you need parallel NOR at 128 Mbit or above, when the joints have to be inspectable or reworkable, and when you can spend the board area. The dated commitment to 2030 makes it a defensible choice for equipment with a long service life, and the cross-vendor pin compatibility gives you a second source that most packages in this family cannot offer.
Move to a Fortified BGA when board area is the constraint, or the moment your density requirement passes 1 Gbit. There is no leaded option above that line and no amount of layout work creates one.
Before committing, do three things: confirm the outline is MO-142 rather than the 8.89 mm body registration, check the exceptions table in any cross-vendor compatibility claim, and separate the longevity question from the stock question. The first is a footprint error, the second is a silent one, and the third decides whether you can build next year.
[IMAGE 3: TSOP-56 land pattern showing 28 pads per row and the 13.85 mm array | alt: “TSOP-56 package footprint with 28 pads per row on 0.5 mm pitch”]
Internal links to add
- [INTERNAL LINK: TSOP package → the full TSOP family, registrations and land patterns]
- [INTERNAL LINK: TSOP Type I → short-side lead layout and the land pattern derivation]
- [INTERNAL LINK: TSOP-48 package → the 48-lead outline and its three pinouts]
- [INTERNAL LINK: SSOP-56 package → the 56-lead SSOP alternative at 0.635 mm pitch]
- [INTERNAL LINK: parallel NOR flash selection → TSOP against Fortified BGA]
