A TSOP-54 package is a Type II thin small outline package with 27 gull-wing leads on each long edge at 0.80 mm pitch. Two of them exist. The common one has a 10.16 mm body and an 11.76 mm lead span; a second, registered separately, has a 12.70 mm body and a 14.3 mm lead span. Their land patterns differ by exactly one tenth of an inch, and nothing on the part marking tells you which you have.

Key takeaways

• The mainstream outline is 10.16 mm × 22.22 mm body, 11.76 mm lead span, 0.80 mm pitch, 1.20 mm max height.
• A 500-mil variant exists: 12.7 ± 0.1 mm body width, 22.66 mm max body length, 14.3 ± 0.2 mm lead span.
• Both use the same 20.8 mm lead row, so pad pitch and array length are identical. Only the row spacing changes, by 2.54 mm.
• SDRAM, SRAM, nvSRAM and MRAM all ship in the 400-mil version, which makes the footprint unusually future-proof.
• Everspin publishes named replacement notes for swapping Cypress nvSRAM and SRAM for MRAM in this package.
• MRAM on this footprint brings its own rules: a 2 ms startup delay and control pins that must be pulled up through power-up.

[IMAGE 1: TSOP-54 outline with 27 leads per long edge, 11.76 mm lead span and 0.80 mm pitch dimensioned | alt: “TSOP-54 package dimensions showing 0.80 mm pitch, 10.16 mm body width and 11.76 mm lead span”]

What a TSOP-54 package is

A TSOP-54 package is a 54-lead thin small outline package, Type II, with 27 gull-wing leads on each of the two longer edges at 0.80 mm pitch and a maximum seated height of 1.20 mm. It is the standard leaded package for SDR SDRAM and for parallel non-volatile memory in industrial equipment.

Type II means the leads emerge from the long edges, which lets a 10.16 mm wide body carry 54 pins. That narrowness is why the format survived on memory modules long after Type I had settled into flash.

Two 54-pin outlines, one tenth of an inch apart

Renesas publishes two 54-pin TSOP II drawings. They are not variants of one another in any useful sense.

Parameter	400 mil	500 mil
Body width	10.16 mm	12.7 ± 0.1 mm
Body length	22.22 mm	22.66 mm max
Lead span	11.56 / 11.76 / 11.95 mm	14.3 ± 0.2 mm
Pitch	0.80 mm BSC	0.8 mm T.P.
Lead width	0.30 / 0.35 / 0.45 mm	0.30 ± 0.10 mm
Foot length	0.40 / 0.50 / 0.60 mm	0.5 ± 0.1 mm
Standoff	0.05 / 0.10 / 0.15 mm	0.05 ± 0.05 mm
Registration	MS-024	MO-135
Source	Everspin TSOP2 guide	Renesas PTSB0054GB

The JEDEC JEP95 index confirms the split: MO-135 covers the 12.70 mm body family at 32, 34, 50 and 54 leads, while the 10.16 mm family sits under MS-024. Both register 54. The 500-mil drawing is Renesas PTSB0054GB.

Now the part that makes this tractable. Work out the lead row on each:

400 mil: 27 per edge, 26 × 0.80 mm = 20.8 mm row in a 22.22 mm body

500 mil: 27 per edge, 26 × 0.80 mm = 20.8 mm row in a 22.66 mm body

The rows are identical. Both outlines put the same 20.8 mm of leads on the same pitch. The only meaningful difference runs across the short axis, and it is a clean 0.1 inch step from 400 to 500 mil.

The footprint difference is one number

The 400-mil land pattern is derived in full on the TSOP Type II page and comes out at 0.53 mm × 1.50 mm pads on an 11.16 mm row centreline. Running the same IPC-7351B nominal method on the 500-mil drawing, with Level B fillet goals of Jt = 0.35 mm, Jh = 0.35 mm and Js = 0.03 mm and 0.05 mm allowances for fabrication and placement:

Lead span L runs 14.1 mm to 14.5 mm, so Ltol = 0.40 mm. Inner separation S runs from 14.1 − 2(0.6) = 12.9 mm to 14.5 − 2(0.4) = 13.7 mm, so Stol = 0.80 mm. Lead width W runs 0.20 mm to 0.40 mm, so Wtol = 0.20 mm.

Z = 14.1 + 0.70 + √(0.40² + F² + P²) = 15.21 mm

G = 13.7 − 0.70 − √(0.80² + F² + P²) = 12.20 mm

X =  0.20 + 0.06 + √(0.20² + F² + P²) =  0.47 mm

Land pattern parameter	400 mil	500 mil
Pad size	0.53 mm × 1.50 mm	0.47 mm × 1.50 mm
Row centreline spacing	11.16 mm	13.70 mm
Outer pad extent (Z)	12.66 mm	15.21 mm
Inner gap (G)	9.66 mm	12.20 mm
Pad-to-pad clearance	0.27 mm	0.33 mm
Pad array length	21.33 mm	21.27 mm

The row centreline moves 2.54 mm and the pad length does not change at all. Converting a 400-mil footprint to 500-mil is a row-spacing edit, not a redraw. The pad width drops 0.06 mm only because the two drawings quote different lead-width tolerances, and the wider clearance that results makes the 500-mil version slightly easier to route.

[IMAGE 2: 400-mil and 500-mil TSOP-54 land patterns overlaid showing the 2.54 mm row spacing difference | alt: “TSOP-54 package footprint comparison showing 11.16 mm and 13.70 mm row centreline spacing”]

One footprint, four memory technologies

Pin numbering runs down one long edge and back up the other, with pin 1 at the marked index corner and pin 27 facing pin 28 across the far end.

What makes the 400-mil version worth designing in is what it hosts. The same 54-lead outline carries:

• SDR SDRAM, from ISSI, Alliance Memory and Winbond
• Asynchronous SRAM, in industrial densities
• nvSRAM, including Infineon’s parts in the PG-TSOP-54-800 package, drawing 51-85160
• Parallel MRAM, including Everspin’s MR4A16B at 16 Mb and MR5A16A at 32 Mb

Pin assignment is not standardized across those technologies, so none of them is a blind drop-in for another. What is real is that vendors document the migrations. Everspin publishes an application note on replacing 8 Mb nvSRAM with 16 Mb MRAM in TSOP2 and FBGA, effective 1 March 2013, and a second, EST 2902, on replacing the Cypress CY62168EV30LL-45BVXI MoBL SRAM with the MR4A08B, effective 27 May 2020.

If you are laying out a 54-lead footprint for a product with a long service life, that documented upgrade path is the strongest argument for the package.

Designing MRAM onto a 54-lead footprint

Three device rules from the Everspin MR4A16B datasheet, revision 11.7 dated March 2018, catch people who treat parallel MRAM as a straight SRAM substitute.

There is a startup delay. Once VDD exceeds its minimum, the part needs 2 ms before read or write operations can begin. An SRAM-style boot sequence that writes immediately after power-good will fail.

Control pins need pull-ups. The datasheet specifies that the E and W control signals should track VDD on power-up to VDD − 0.2 V or VIH, whichever is lower, and remain high for the startup time. In most systems that means a pull-up resistor so the pin stays high while the driving signal is high-impedance.

ECC is already inside. The MR4A16B carries internal single-bit error correction with 7 parity bits for every 64 data bits, alongside 35 ns SRAM-compatible timing and better than 20 years of retention. If your design planned to add external ECC, check whether you are duplicating it.

The magnetic immunity constraint covered on the TSOP Type II page applies here too, and matters more at 54 leads because these are the densities that end up near motors and contactors.

Sourcing and second sources

The 400-mil version is well supplied and the supply is specialist rather than from the original vendors. ISSI’s IS42S16320F-7TLI, a 512 Mbit SDRAM in 54-TSOP II, is active with a 12-week factory lead time. Alliance Memory positions its AS4C32M16SB as a pin-for-pin replacement for Micron’s discontinued MT48LC32M16A2P and states it bought the remaining Micron stock in 2014.

Everspin’s MRAM in this package spans commercial, industrial and automotive grades, with the MR5A16A rated −40 °C to +125 °C.

Two sourcing checks are worth building into your process. Everspin’s change notices for 16 Mb MRAM record moisture sensitivity moving from MSL 6 to MSL 5, and separately from MSL 5 to MSL 3 on the 48-BGA version, so take the MSL from the orderable part number rather than the family. And the company has added and requalified assembly sites more than once, which does not change the drawing but can change how a marginal reflow profile behaves.

Distributors index this package under the 400-mil outline only. DigiKey writes it as “54-TSOP (0.400 in, 10.16 mm Width)”. If your part is the 500-mil variant, the package field will not help you find it.

Five mistakes on TSOP-54 designs

1. Assuming one 54-pin outline. Two exist, 2.54 mm apart in row spacing. Take the lead span from the drawing.
2. Redrawing instead of editing. Both outlines share the lead row and pad length. Converting between them is a row-spacing change.
3. Treating parallel MRAM as an SRAM drop-in. The 2 ms startup and the control-pin pull-up requirement are real.
4. Taking MSL from the family. Everspin’s own notices show the level moving twice on the same product line.
5. Searching only the 400-mil package field. Distributor taxonomy does not cover the 500-mil variant.

TSOP-54 FAQ

What are TSOP-54 package dimensions?

For the common 400-mil outline: body 10.16 mm × 22.22 mm, lead span 11.56 mm to 11.95 mm, pitch 0.80 mm, maximum height 1.20 mm, with 27 leads on each long edge. A 500-mil outline also exists at 12.7 ± 0.1 mm body width, 22.66 mm maximum body length and a 14.3 ± 0.2 mm lead span.

Is TSOP-54 Type I or Type II?

Type II. The leads emerge from the two longer edges, which is what lets a body only 10.16 mm wide carry 54 pins. Distributors write it as “54-TSOP II” or “54-TSOP (0.400 in, 10.16 mm Width)”. No 54-lead Type I registration exists.

What does 400 mil mean on a TSOP-54?

The body width, 10.16 mm, which identifies the JEDEC family MS-024. The number matters because a second 54-lead registration, MO-135, uses a 12.70 mm body and is described as 500 mil. Both run 0.80 mm pitch and 54 leads, so only the mil figure separates them.

What is a 54-TSOP II used for?

SDR SDRAM, asynchronous SRAM, nvSRAM and parallel MRAM. Everspin ships 16 Mb and 32 Mb MRAM in it, Infineon ships nvSRAM, and ISSI, Alliance Memory and Winbond ship SDRAM. Pin assignments differ by technology, so confirm the specific device rather than assuming compatibility.

Is TSOP-54 still in production?

Yes, from specialists rather than original vendors. SDRAM comes mainly from ISSI and Alliance Memory, with lead times around 12 weeks. MRAM in this package is current across commercial, industrial and automotive grades. Treat it as a mature format with a stable supply rather than a growing one.

Choosing TSOP-54

Specify the 400-mil TSOP-54 when you need parallel memory in a leaded, inspectable package with a long service life, and when board height rather than board area is your constraint. The range of technologies sharing this footprint is its real advantage: a board laid out for SDRAM today can host nvSRAM or MRAM in a later revision without a new land pattern, provided you check the pin assignment.

Choose the 500-mil variant only when the part you need is built in it, and edit the row spacing rather than starting a new footprint.

Before you commit, do three things: read the lead span off the drawing to establish which outline you have, confirm the pin assignment against the specific device rather than the technology, and take the MSL from the orderable part number. The first is a footprint error; the other two fail after assembly.

[IMAGE 3: 54-lead TSOP II devices in SDRAM, nvSRAM and MRAM on one board outline | alt: “TSOP-54 package hosting SDRAM, nvSRAM and MRAM on the same footprint”]

Internal links to add

• [INTERNAL LINK: TSOP package → the full TSOP family, registrations and land patterns]
• [INTERNAL LINK: TSOP Type II → long-side lead layout and the 400-mil land pattern derivation]
• [INTERNAL LINK: TSOP Type I → short-side lead layout and escape routing]
• [INTERNAL LINK: TSOP-48 package → the 48-lead outline and its three pinouts]
• [INTERNAL LINK: MRAM vs nvSRAM → non-volatile memory selection for industrial designs]