Post: SOIC-8 Package: Dimensions, Pinout and Land Pattern

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SOIC-8 Package: Dimensions, Pinout and Land Pattern

A SOIC-8 package is an 8-lead plastic package with gull-wing leads on 1.27 mm pitch, a 3.90 mm nominal body width and a 6.00 mm nominal lead span, registered to JEDEC MS-012 variation AA. Its nominal footprint is eight 1.55 mm × 0.60 mm pads with the two rows 5.40 mm apart, centre to centre. One warning before you draw anything: at least three different body widths ship under this same name.

Key takeaways

Lead pitch is always 1.27 mm (50 mil). Body width is not always 3.90 mm.
JEDEC MS-012 covers the 3.90 mm narrow body; MS-013 covers a 7.50 mm body; JEITA/EIAJ Type II parts at 5.30 mm are also sold as SOIC-8.
The IPC-7351B nominal land pattern is SOIC127P600X175-8N: 1.55 mm × 0.60 mm pads, 1.27 mm pitch, rows 5.40 mm apart.
Texas Instruments specifies 124.7 °C/W junction-to-ambient for its 8-pin SOIC on a JEDEC high-K board — about 520 mW of headroom at 85 °C ambient.
Pin 1 sits top-left in top view; numbering runs counterclockwise.
Most 8-pin SOICs ship at MSL 1 with a 260 °C peak reflow classification, so no bake is required before assembly.

[IMAGE 1: dimensioned top and side view of a SOIC-8 body showing D, E, E1, e and A | alt: “SOIC-8 package dimensions diagram showing 1.27 mm pitch and 3.90 mm body width”]

SOIC-8 dimensions: what JEDEC MS-012 actually specifies

Work from the package drawing in the datasheet you are actually buying, not from a generic figure. The table below is the D0008A outline (rev C, 02/2019) published by Texas Instruments, which references JEDEC registration MS-012 variation AA. Controlling dimensions in that drawing are inches; the millimetre values are conversions.

Dimension	Symbol	Millimetres	Inches
Lead pitch	e	1.27 BSC	.050 BSC
Body length	D	4.81 – 5.00	.189 – .197
Body width	E1	3.81 – 3.98	.150 – .157
Lead span, tip to tip	E	5.80 – 6.19	.228 – .244
Overall height	A	1.75 max	.069 max
Standoff	A1	0.11 – 0.25	.004 – .010
Lead width	b	0.31 – 0.51	.012 – .020
Lead thickness	c	0.13 – 0.25	.005 – .010
Foot length	L	0.41 – 1.27	.016 – .050
Foot angle	—	0° – 8°	—
Lead coplanarity	—	0.10 max	.004 max

Table 1. SOIC-8 dimensions per TI drawing D0008A, JEDEC MS-012 variation AA.

Two numbers on that list do more damage than the rest when they are ignored. Lead coplanarity of 0.10 mm maximum is the flatness budget across all eight feet; a reel that has been dropped can exceed it and produce open joints that pass visual inspection. The 0.11 mm minimum standoff is what lets flux residue wash out from under the body, so under-body conformal coating and no-clean process choices depend on it.

SOIC-8 vs SOP-8: three body widths, one package name

“SOIC-8” identifies a lead count and a pitch. It does not identify a footprint. Three registrations circulate under the label, and vendors do not apply the naming consistently.

Datasheet label	Body width	Registration	Where you meet it
SOIC-8 narrow, SOIC_N, SO-8, TI suffix D	3.90 mm (150 mil)	JEDEC MS-012	Op-amps, logic, gate drivers, small MOSFETs
SOP-8, SOIC 208-mil, TI suffix PS	5.30 mm (208 mil)	JEITA / EIAJ Type II	Serial flash, EEPROM, some regulators
SOIC-8 wide, SOIC_W	7.50 mm	JEDEC MS-013	Isolators and parts needing creepage

Table 2. Body widths sold under the SOIC-8 name.

The SPI flash market is where this bites hardest. Winbond ships the W25Q128JV with package code S, and its own datasheet (rev H, 10 March 2021) calls that package SOIC 208-mil — a 5.30 mm body, not the 3.90 mm one your library probably holds under “SOIC-8”. Texas Instruments takes the opposite convention: its device table lists the D package as SOIC at 4.90 mm × 3.90 mm and the PS package as SO at 5.20 mm × 5.30 mm. Same physical family, different letters, different footprint.

The practical rule: never place a part from a footprint named after the package. Match the lead span dimension E from the drawing to the row spacing of your land pattern. If E is around 6.0 mm you want the narrow footprint; if it is materially larger, you need the 208-mil one.

[IMAGE 2: three SOIC-8 bodies overlaid at 3.90 mm, 5.30 mm and 7.50 mm width | alt: “SOIC-8 body width comparison showing 3.90 mm JEDEC, 5.30 mm EIAJ and 7.50 mm wide-body packages”]

SOIC-8 pinout and pin 1 identification

The package carries no fixed function assignment. Pin 1 sits at the upper left when the part is viewed from above with the pin 1 identifier in the top-left corner, and numbering runs counterclockwise: 1 to 4 down the left side, 5 to 8 up the right side.

Vendors mark pin 1 in several ways, and a footprint silkscreen that assumes one of them will eventually mislead an operator. TI’s D0008A drawing calls out a “pin 1 ID area” — a corner region, not a dot — while Monolithic Power’s 8-SOIC exposed-pad drawing shows an explicit “PIN 1 ID” feature, and other suppliers use a moulded dimple or a laser-marked dot. Vishay’s SOIC-8 drawing (document 83247, rev 1.2) carries its own pin one ID geometry again.

For a dual op-amp in this package, TI assigns OUT1, IN1−, IN1+, V− to pins 1 to 4 and IN2+, IN2−, OUT2, V+ to pins 5 to 8. A serial flash in the same outline assigns /CS, DO, /WP, GND, DI, CLK, /HOLD, VCC. Nothing about the package predicts either. Read the pin table.

[IMAGE 3: SOIC-8 pinout top view with pin 1 marker and counterclockwise numbering | alt: “SOIC-8 pinout top view showing pin 1 identifier and counterclockwise pin numbering”]

SOIC-8 land pattern and stencil design

The recommended land pattern published with TI’s D0008A outline matches the IPC-7351B nominal-density footprint SOIC127P600X175-8N. Using it means your board is inspectable against IPC-A-610 fillet criteria without argument.

Feature	Value	Source
Pad count	8	TI D0008A example board layout
Pad size	1.55 mm × 0.60 mm	TI D0008A example board layout
Pad pitch	1.27 mm	TI D0008A example board layout
Row spacing, pad centre to pad centre	5.40 mm	TI D0008A example board layout
Outer span of the pattern	6.95 mm	Derived: 5.40 + 1.55
Inner gap between rows	3.85 mm	Derived: 5.40 − 1.55
Solder mask	Non-solder-mask-defined, 0.07 mm clearance all round	TI D0008A solder mask details
Stencil aperture	1:1 with the pad, 0.125 mm foil	TI D0008A example stencil design
Courtyard excess, nominal density	0.25 mm per side	IPC-7351B level N

Table 3. SOIC-8 land pattern and stencil values.

If you need to build the footprint yourself rather than copy it, IPC-7351B sets the fillet extensions for gull-wing leads at 0.55 / 0.35 / 0.15 mm toe and 0.45 / 0.35 / 0.25 mm heel for the Most, Nominal and Least density levels, with side extensions of 0.05 / 0.03 / 0.01 mm. Applying nominal values to the MS-012 lead geometry reproduces the 1.55 mm × 0.60 mm pad above, which is a useful sanity check on any library you inherit.

Pick Most density for hand assembly and rework-heavy prototypes, Nominal for ordinary reflow production, and Least only when routing density forces it. The 1:1 stencil aperture is deliberate: shrinking apertures on a 1.27 mm pitch part starves the heel fillet, which is where thermal-cycling cracks start.

[IMAGE 4: SOIC-8 land pattern with pad dimensions and row spacing called out | alt: “SOIC-8 land pattern drawing with 1.55 mm by 0.60 mm pads on 5.40 mm row spacing”]

SOIC-8 thermal performance and power limits

The package sets your power budget long before the silicon does. TI publishes measured thermal metrics for the same die in seven package options in datasheet SLOS068Z, which makes it one of the cleanest package-to-package comparisons available. All values are on JEDEC high-K test boards.

8-pin package	RθJA (°C/W)	RθJC top (°C/W)	ψJB (°C/W)	Max PD at 85 °C (derived)
SOIC, suffix D	124.7	66.9	67.2	521 mW
SO 208-mil, suffix PS	116.9	62.5	67.6	556 mW
TSSOP, suffix PW	171.7	68.8	97.9	379 mW
VSSOP, suffix DGK	181.4	69.4	101.2	358 mW
SOT-23-8, suffix DDF	164.3	98.1	81.7	396 mW
PDIP, suffix P	80.9	70.4	56.9	803 mW

Table 4. Thermal metrics from TI SLOS068Z. The final column is derived as (150 − 85) / RθJA, assuming the 150 °C maximum junction temperature that datasheet specifies.

Worked example. A part in this package dissipating 250 mW in an 85 °C enclosure runs at 85 + (0.25 × 124.7) = 116 °C junction. That leaves 34 °C of margin to the 150 °C limit — comfortable. Push the same part to 125 °C ambient and the ceiling collapses to (150 − 125) / 124.7 = 200 mW. Automotive underhood and industrial cabinet designs fail here far more often than at room temperature.

Two results in Table 4 are worth internalising. The 208-mil SO package is thermally slightly better than the narrow SOIC because of its larger lead frame, and the PDIP beats both — miniaturisation costs thermal headroom every time. If you need more than roughly 500 mW at 85 °C, move to an exposed-pad variant rather than fighting the standard outline: Monolithic Power’s 8-SOIC with exposed pad, drawn to MS-012 variation BA, exposes a die pad of roughly 2.26 – 2.56 mm × 3.15 – 3.45 mm that couples directly into board copper.

Assembly, moisture sensitivity and tape-and-reel data

Everything in this section comes from the package addendum of the same TI datasheet, and the values are typical across suppliers of the narrow body.

Moisture sensitivity: Level 1 with a 260 °C peak classification temperature. MSL 1 carries unlimited floor life at ordinary factory conditions, so no pre-bake is required.
Lead finish: NIPDAU or matte tin on RoHS-compliant parts.
Tape and reel: 12 mm carrier tape on a 330 mm reel, 2,500 pieces, pocket pitch P1 = 8.0 mm, pocket A0 = 6.4 mm, B0 = 5.2 mm, K0 = 2.1 mm, pin 1 in quadrant Q1.
Tube packing: 75 pieces per tube for the same outline.

Those A0 and B0 pocket numbers matter when you specify feeders. A0 = 6.4 mm and B0 = 5.2 mm are cut for the 3.90 mm body; a 208-mil part will not seat correctly in that tape, which is a second, quieter consequence of confusing the two.

When to choose SOIC-8 and when to move on

Run the decision in this order. It takes about a minute and prevents most late-stage package changes.

Power first. Compute (TJmax − TAmax) / RθJA against your worst-case dissipation. Above roughly 500 mW at 85 °C ambient, go to an exposed-pad or leadless outline.
Voltage and creepage next. Reinforced isolation or mains-referenced nodes push you to the wide body or to a dedicated isolator package.
Board area third. If the SOIC-8 footprint of roughly 6.95 mm × 5.0 mm does not fit, TSSOP-8 or VSSOP-8 will — at 172 °C/W and 181 °C/W respectively, so re-run step one.
Assembly capability fourth. SOIC-8 is hand-solderable, reworkable with a standard iron, and probe-accessible. Leadless packages are none of those. Prototype volume and field repair policy often decide this alone.
Sourcing last. The 1.27 mm pitch is universal, so second sources are plentiful — but confirm body width and lead span on every alternate before approving it.

SOIC-8 design mistakes that cause board spins

Reusing a library footprint named “SOIC-8” for a 208-mil part. The part sits across the pads with no heel contact. Verify dimension E, not the name.
Copying a land pattern without its solder mask rule. The TI pattern is non-solder-mask-defined with 0.07 mm clearance; letting mask encroach onto the pad edge shrinks the joint and hides the defect from optical inspection.
Reducing stencil apertures below 1:1 to control bridging. On 1.27 mm pitch, bridging is a paste-release or placement problem, not an aperture-size one.
Assuming the exposed-pad variant is a drop-in. MS-012 variation BA adds a thermal pad; a board drawn for variation AA has no copper under it and loses the entire thermal benefit.
Quoting RθJA from one vendor and applying it to another. The metric depends on the test board as much as the package, which is why TI states the board condition alongside the number.
Ignoring the 0.10 mm coplanarity limit on parts that have been stored loose or reworked once already.

SOIC-8 package FAQ

What is a SOIC-8 package?

A SOIC-8 is a surface-mount plastic package with eight gull-wing leads on 1.27 mm pitch, four per side. The common narrow version has a 3.90 mm nominal body width, a 6.00 mm nominal lead span and a 1.75 mm maximum height, registered to JEDEC MS-012. It carries no fixed pin function assignment.

What are SOIC-8 dimensions in mm?

Per JEDEC MS-012 variation AA: body 4.81 – 5.00 mm long and 3.81 – 3.98 mm wide, lead span 5.80 – 6.19 mm, height 1.75 mm maximum, pitch 1.27 mm, lead width 0.31 – 0.51 mm, standoff 0.11 – 0.25 mm. Coplanarity is limited to 0.10 mm.

Is SOIC-8 the same as SOP-8?

Not reliably. Texas Instruments and several other suppliers reserve SOIC for the 3.90 mm JEDEC body and SOP for the 5.30 mm JEITA/EIAJ Type II body. Other suppliers, Winbond among them, call the 5.30 mm part SOIC 208-mil. Check the lead span on the drawing before treating the two as interchangeable.

What is the recommended SOIC-8 land pattern?

Eight pads of 1.55 mm × 0.60 mm on 1.27 mm pitch, with the two rows 5.40 mm apart centre to centre. That gives an outer span of 6.95 mm and an inner gap of 3.85 mm. Solder mask is non-solder-mask-defined with 0.07 mm clearance, and the stencil is 1:1 on a 0.125 mm foil.

How do I identify pin 1 on a SOIC-8?

Look for the pin 1 identifier in the top-left corner in top view — depending on the supplier this is a moulded dimple, a printed dot, a chamfered corner or a marked corner region. From there, numbering runs counterclockwise: pins 1 to 4 down the left, 5 to 8 up the right.

How much power can a SOIC-8 dissipate?

On a JEDEC high-K board, TI specifies 124.7 °C/W junction-to-ambient for its 8-pin SOIC. With a 150 °C maximum junction temperature, that allows roughly 520 mW at 85 °C ambient and about 200 mW at 125 °C. Real boards differ; treat these as a starting budget, not a guarantee.

What to do before you release the footprint

Open the drawing for the exact orderable part number and read dimension E. If it is 5.80 – 6.19 mm, place the IPC-7351B nominal pattern — 1.55 mm × 0.60 mm pads on 5.40 mm rows — and move on. If it is larger, you are holding a 208-mil part and you need a separate footprint in your library, named for the body width rather than the package.

Then run the thermal number once: (TJmax − TAmax) / RθJA against worst-case dissipation. If the answer is under 500 mW at your real ambient and you are close to it, specify the exposed-pad variant now, while the board is still cheap to change.