A SOIC-20 package is 12.80 mm × 7.50 mm nominal with a 10.30 mm lead span, 2.65 mm maximum height and 1.27 mm pitch, registered under JEDEC MS-013. At 20 leads the name stops being one package. Distributors file two different body widths under the same 20-SOIC heading, and the same die in a 5.30 mm body runs marginally cooler than the 7.50 mm one.
Key Takeaways
- Wide body is 7.50 mm × 12.80 mm nominal, span 9.97 to 10.63 mm, height 2.65 mm max, pitch 1.27 mm.
- Land pattern is 9.30 mm row spacing with 2.00 mm × 0.60 mm pads, identical in cross-section to the 16- and 18-lead members of the family.
- Thermal resistance is 70.4 °C/W in the wide SOIC-20 against 94.9 °C/W in a TSSOP-20 for the same die, which costs 90 mm² of extra copper.
- Digi-Key lists both a 7.50 mm and a 5.30 mm body as 20-SOIC. Read the width in the field, not the pin count.
- The wide body needs 24 mm tape. SSOP-20, TSSOP-20 and VSSOP-20 all fit 16 mm feeders.
- Two vendors publish pad widths for this outline that differ by 27%.
What the SOIC-20 Package Is
A SOIC-20 package is a 20-lead gull-wing plastic surface-mount package on 1.27 mm pitch, ten leads per long side, built on the JEDEC MS-013 wide-body outline: 7.50 mm nominal body width, 12.80 mm nominal body length, 2.65 mm maximum height. Vendors label it DW, SO, SW or 20-SOIC.
Pin 1 to pin 10 centres span exactly 11.43 mm, which is nine pitches of 1.27 mm. Texas Instruments prints that same 11.43 mm on the DW0020A drawing, so it is a useful sanity check when you are reading an unfamiliar outline.
[IMAGE 1: SOIC-20 outline with body width, body length and lead span dimensioned, next to a 5.30 mm 20-lead SO body at the same scale | alt: “SOIC-20 package dimensions compared with the 5.30 mm 20-lead SO body”]
SOIC-20 Dimensions
Two independent drawings for the same outline are shown side by side, because tolerance bands differ slightly between vendors even when the JEDEC registration is identical.
| Dimension | TI DW0020A (drawing 4220724/A) | ADI SW 20-lead (drawing 05-08-1620) |
| Body length, D | 12.6 – 13.0 mm | 12.598 – 13.005 mm |
| Body width, E1 | 7.4 – 7.6 mm | 7.391 – 7.595 mm |
| Lead span, E | 9.97 – 10.63 mm typ | 10.007 – 10.643 mm |
| Height, A | 2.65 mm max | 2.362 – 2.642 mm |
| Standoff, A1 | 0.1 – 0.3 mm | 0.102 – 0.305 mm |
| Lead pitch, e | 1.27 mm | 1.270 mm BSC |
| Lead width, b | 0.31 – 0.51 mm | 0.356 – 0.482 mm typ |
| Lead thickness, c | 0.10 – 0.33 mm | 0.229 – 0.330 mm |
| Foot length, L | 0.40 – 1.27 mm | 0.406 – 1.270 mm |
| Lead angle | 0° – 8° | 0° – 8° typ |
| Pin 1 to pin 10 centres | 11.43 mm typ | 9 × 1.270 mm BSC |
| Mold flash allowance | ≤ 0.15 mm per side | ≤ 0.15 mm |
| Interlead flash allowance | ≤ 0.43 mm per side | Not stated |
| Reference | JEDEC MS-013 | Wide 0.300 inch |
One difference is worth reading twice. TI’s DW0020A drawing allows interlead flash up to 0.43 mm per side. The 16-lead drawing in the same family, DW0016B, allows 0.25 mm per side. If your incoming inspection rule was written against a SOIC-16W, it will fail good SOIC-20 parts.
The Three Bodies Filed Under 20-SOIC
At 8 and 14 leads, SOIC means one thing. At 20 it does not.
| Designation | Body width | Body length (nom) | Distributor Package / Case | Status |
| SOIC-20 wide (TI DW, ADI SW) | 7.50 mm | 12.80 mm | 20-SOIC (0.295″, 7.50 mm Width) | Mainstream, deeply stocked |
| SO-20 / SOP-20 (TI NS) | 5.30 mm | 12.60 mm | 20-SOIC (0.209″, 5.30 mm Width) | Available, thinner stock |
| SO20N narrow (CAD libraries) | 3.90 mm claimed | Not published | No matching category found | Not offered by ADI, Microchip, NXP or TI |
The two commercial bodies come from different standards families. TI and Fairchild use SOIC for the JEDEC 3.9 mm and 7.5 mm widths and SOP for the EIAJ 5.3 mm width. Digi-Key ignores that distinction in its Package / Case field and calls both 20-SOIC, separating them only by the width in parentheses.
The Supplier Device Package field does distinguish them, reading 20-SOIC for the wide part and 20-SO for the 5.30 mm part. Filter on Package / Case and read the width.
A third body shows up in CAD libraries as SO20N, a 150 mil narrow 20-lead outline. None of the four vendor catalogues checked for this article — Analog Devices, Microchip, NXP and TI — offers a 20-lead narrow SOIC. Treat a narrow 20-lead library part as unverified until a drawing says otherwise.
SOIC-20 Pinout and Pin 1 Identification
Numbering follows the DIP convention it replaced. Viewed from the top, pin 1 sits at the upper left, pins 1 through 10 run down the left side, and pins 11 through 20 run up the right side. Pin 10 faces pin 11 across the short end.
Pin function is not fixed by the package. On the TI SN74HCT245 octal transceiver, pin 10 is GND and pin 20 is VCC, with the direction control on pin 1 and the output enable on pin 19. TI notes that the centre VCC and GND pin arrangement minimises high-speed switching noise, which is a reason to check the pinout rather than assume corner power pins.
Three pin 1 markers appear across the family: a molded dot, a notch on the short end, and a beveled edge along the pin 1 side. The Analog Devices drawing states that the notch on top and the cavities on the bottom are manufacturing options and may or may not be present, so an inspection rule written around one marker style will reject good parts.
[IMAGE 2: SOIC-20 top view showing pin numbering direction, the pin 1 index area and the pin 10 to pin 11 short-end pair | alt: “SOIC-20 pinout numbering and pin 1 identification”]
SOIC-20 Land Pattern
| Land pattern parameter | TI DW0020A | ADI SW 20-lead |
| Pad row spacing | 9.30 mm centre to centre | Layout dimension marked 8.255 mm ± 0.127 mm; datum not labelled |
| Pad length | 2.00 mm | 1.143 mm ± 0.127 mm |
| Pad width | 0.60 mm | 0.762 mm ± 0.127 mm |
| Pad pitch | 1.27 mm × 9 spaces per side | 1.270 mm BSC |
| Pads per side | 10 | 10 |
| Solder mask relief | 0.07 mm all round, NSMD | Not stated |
| Stencil | 0.125 mm, 1:1 aperture | Not stated |
| Copper envelope | 11.30 × 12.03 mm ≈ 136 mm² | Not computed here |
| Source | Drawing 4220724/A | Drawing 05-08-1620 |
TI’s published pattern is 9.30 mm row spacing with 2.00 mm × 0.60 mm pads at 1.27 mm pitch, non-solder-mask-defined with 0.07 mm relief, and a 0.125 mm stencil printed 1:1. That is the same cross-section TI publishes for the 16-lead wide body, so a library built for one scales to the other by pad count alone.
Analog Devices recommends something different for the identical JEDEC outline: pads 1.143 mm long by 0.762 mm wide on 1.270 mm pitch. The pad width differs by 27% between the two vendor recommendations. Both are legitimate. Pick one and apply it consistently, because a library that mixes TI pad lengths with ADI pad widths matches neither reflow model.
Copper envelope for the TI pattern is 11.30 mm across by 12.03 mm along, about 136 mm². That number is what the next section trades against.
Thermal Performance Against Every Other 20-Pin Package
The SN74HCT245 is offered in nine 20-pin packages, so one datasheet gives a controlled comparison that no package summary page carries. Six surface-mount and through-hole options are shown here.
| SN74HCT245, 20 pins | DW (SOIC) | NS (SO) | DB (SSOP) | PW (TSSOP) | DGS (VSSOP) | N (PDIP) |
| Body size, nominal (mm) | 12.80 × 7.50 | 12.60 × 5.30 | 7.80 × 7.20 | 6.50 × 4.40 | 5.10 × 3.00 | 24.33 × 6.35 |
| RθJA (°C/W) | 70.4 | 68.9 | 84.6 | 94.9 | 118.4 | 43.4 |
| RθJC(top) (°C/W) | 36.5 | 34.7 | 44.3 | 30.2 | 57.7 | 29.5 |
| RθJB (°C/W) | 38.1 | 36.4 | 40.2 | 45.7 | 73.1 | 24.3 |
| ψJB (°C/W) | 37.7 | 36 | 39.7 | 45.1 | 72.7 | 24.2 |
| Allowable PD at 85 °C | 0.92 W | 0.94 W | 0.77 W | 0.68 W | 0.55 W | 1.50 W |
| Land pattern copper | ≈ 136 mm² | Not published here | ≈ 56 mm² | ≈ 46 mm² | ≈ 28 mm² | Through-hole |
Two results deserve attention. First, the wide SOIC-20 buys 24.5 °C/W over a TSSOP-20 and 48 °C/W over a VSSOP-20. Second, and less expected, the 5.30 mm SO body measures 68.9 °C/W against the wide body’s 70.4 °C/W. Wider is not automatically cooler at the same pin count.
Work the trade. Allowable dissipation at 85 °C ambient, with the 150 °C junction limit, is (150 − 85) / 70.4 = 0.92 W in the wide SOIC-20 and (150 − 85) / 94.9 = 0.68 W in the TSSOP-20. The SOIC-20 costs 90 mm² more copper for that extra 0.24 W, which works out at 3.7 mm² of board area per °C/W saved.
Whether that is a good trade depends on what else competes for the area. On a dense consumer board it rarely is. On a four-layer industrial board with room to spare, it usually is.
Treat these figures as a package comparison rather than a system prediction. TI’s own thermal metrics application report states that RθJA is measured on a specific test coupon and is the most frequently misused thermal metric. For a junction estimate on your board, use ψJB together with a measured board temperature.
Tape, Reel and Feeder Planning
| Package (SN74HCT245, 20 pins) | Per reel | Tape width W | Reel width W1 | A0 × B0 × K0 | Pitch P1 |
| SOIC (DW) | 2,000 | 24.0 mm | 24.4 mm | 10.9 × 13.3 × 2.7 mm | 12.0 mm |
| SO (NS) | 2,000 | 24.0 mm | 24.4 mm | 8.4 × 13.0 × 2.5 mm | 12.0 mm |
| SSOP (DB) | 2,000 | 16.0 mm | 16.4 mm | 8.2 × 7.5 × 2.5 mm | 12.0 mm |
| TSSOP (PW) | 2,000 | 16.0 mm | 16.4 mm | 6.95 × 7.0 × 1.4 mm | 8.0 mm |
| VSSOP (DGS) | 5,000 | 16.0 mm | 16.4 mm | 5.4 × 5.4 × 1.45 mm | 8.0 mm |
The wide body and the 5.30 mm body both need 24 mm tape. Every shrink option at this pin count fits 16 mm. If a line is set up for 8 mm and 16 mm feeders, choosing SOIC-20 over SSOP-20 costs a 24 mm feeder slot, and all of these ship 2,000 per reel except the VSSOP at 5,000.
Moisture sensitivity is a device property, not a package property. TI ships the SN74HCT245DWR as Level-1-260C-UNLIM, meaning no floor-life clock at all. The same DW body carries Level-2-260C-1 YEAR on other TI devices. Read the dry-pack label rather than a package reference table.
Cost and Availability
The clean comparison is one logic function in both bodies from one manufacturer. On Digi-Key, the SN74HCT245DWR in 20-SOIC (0.295 in, 7.50 mm width) lists at $0.93 in ones and $0.44103 on a 2,000-piece reel, with 8,199 in stock and a 6-week factory lead time. The SN74HCT245ANSR in 20-SOIC (0.209 in, 5.30 mm width) lists at $0.90 in ones and $0.42713 at 2,000, with 1,707 in stock.
The prices sit within 3% of each other. The stock does not: the wide body is stocked roughly five times deeper. For a 20-pin logic part the wide body is the safer supply choice even though it is nominally the more expensive one.
Logic family matters more than package here. The SN74AHC245DWR lists at $0.29024 on a 2,000-piece reel against $0.44103 for the HCT part, in the identical 20-SOIC outline. Changing family saves 34%; changing package saves 3%.
[IMAGE 3: Decision path from a 20-pin function to SOIC-20, SO-20, SSOP-20 or TSSOP-20 based on board area and thermal budget | alt: “SOIC-20 package selection decision path against SSOP and TSSOP alternatives”]
Four Mistakes That Cause SOIC-20 Rework
Ordering on pin count alone. Two bodies 2.20 mm apart in width share the 20-SOIC heading at the same distributor.
Reusing a SOIC-16W footprint length. The cross-section is identical, so nothing looks wrong until two pads per side are missing.
Carrying a SOIC-16W inspection limit. Interlead flash allowance is 0.43 mm per side on the 20-lead drawing against 0.25 mm on the 16-lead one.
Assuming the wide body is the thermal answer. At 20 pins the 5.30 mm body measured slightly better on the same die.
Frequently Asked Questions
What are SOIC-20 dimensions?
Body is 12.6 to 13.0 mm long and 7.4 to 7.6 mm wide, with a lead span of 9.97 to 10.63 mm and a maximum height of 2.65 mm, per TI drawing 4220724/A. Lead pitch is 1.27 mm, lead width 0.31 to 0.51 mm, foot length 0.40 to 1.27 mm and standoff 0.1 to 0.3 mm.
What is the SOIC-20 land pattern?
Texas Instruments publishes 9.30 mm row spacing with 2.00 mm × 0.60 mm pads at 1.27 mm pitch, ten pads per side, non-solder-mask-defined with 0.07 mm relief and a 0.125 mm stencil. Analog Devices recommends 1.143 mm × 0.762 mm pads for the same outline, so confirm against your device drawing.
Is there a narrow-body SOIC-20?
Not from the vendors checked here. Analog Devices, Microchip, NXP and TI all list the 20-lead SOIC as a 300 mil wide body. CAD libraries do carry a 150 mil SO20N entry, which is why a footprint should always be traced back to a drawing.
What is the difference between SOIC-20 and SSOP-20?
Pitch and area. SOIC-20 uses 1.27 mm pitch on a 7.50 mm body and about 136 mm² of copper; SSOP-20 uses 0.65 mm pitch on a 7.20 mm body and about 56 mm². The SOIC runs 14.2 °C/W cooler on the same die.
What ICs come in a SOIC-20 package?
Octal logic such as the 74×245 transceiver and 74×244 buffer families, shift registers, ADCs, DACs and interface devices. Twenty pins covers most 8-bit-wide functions once power, ground, direction and enable pins are counted.
Which 20-Pin Package to Specify
Start from the thermal budget. If the part dissipates under about 0.5 W at your maximum ambient, a TSSOP-20 or SSOP-20 saves 80 to 90 mm² of board area and drops to a 16 mm feeder.
Take the wide SOIC-20 when the die needs the width, when you want the deeper stock position, or when 0.92 W of headroom at 85 °C is the binding constraint. Take the 5.30 mm SO body only if a specific part number requires it, because the stock is thinner and the footprint is different.
Before release, check three numbers against the device drawing: body width, lead span, and row spacing. Then confirm the width in the distributor’s Package / Case field matches the drawing you laid out from, because at 20 leads that field carries two different packages.
