There is no narrow-body SOIC-18. Every 18-lead SOIC is the 7.50 mm wide body under JEDEC MS-013, with an 11.55 mm nominal body length and a 2.65 mm maximum height. Two major vendors do not list a 150 mil 18-lead outline at all, and one skips 18 leads entirely. That scarcity is the real story, and it shows up in your feeder width and your BOM risk.
Key Takeaways
- Body is 7.50 mm × 11.55 mm nominal, span 10.007 to 10.643 mm, height 2.65 mm max, pitch 1.27 mm.
- The 18-lead SOIC exists only as a wide body. Microchip lists it under 300 mil only; NXP’s SOIC family table skips 18 leads.
- Pin 1 to pin 9 centres span exactly 10.16 mm, being eight pitches of 1.27 mm.
- Tape is 24 mm wide on a 24.4 mm reel, not the 16 mm tape a SOIC-16W uses. That is a feeder change on the line.
- Thermal resistance is 66.4 °C/W for the DW-18 body, which still limits an eight-channel driver to two active channels at 200 mA and 85 °C.
- The mainstream TI part in this package is obsolete at Digi-Key; surviving stock comes from second-tier suppliers.
What the SOIC-18 Package Is
A SOIC-18 package is an 18-lead gull-wing plastic surface-mount package on 1.27 mm pitch, nine leads per long side, built on the JEDEC MS-013 wide-body outline: 7.50 mm nominal body width, 11.55 mm nominal body length, 2.65 mm maximum height. Vendors label it DW, SO, SW or 18-SOP.
MS-013 is registered as the very thick profile plastic small outline family at 1.27 mm pitch and 7.50 mm body width. Every 18-lead SOIC you will meet sits inside that registration. The narrow MS-012 family, at 3.90 mm body width, does not carry an 18-lead variation.
[IMAGE 1: SOIC-18 outline with body width, body length and lead span dimensioned, shown beside a SOIC-16W for scale | alt: “SOIC-18 package dimensions compared with SOIC-16W wide body outline”]
SOIC-18 Dimensions
Values below are from the Analog Devices LTC legacy drawing 05-08-1620 for the 18-lead SW package. The neighbouring pin counts are shown to make the family arithmetic visible.
| Dimension | SOIC-18 (JEDEC MS-013) | SOIC-16W, reference | SOIC-20W, reference |
| Body width, E1 | 7.391 – 7.595 mm | 7.40 – 7.60 mm | 7.4 – 7.6 mm |
| Body length, D | 11.354 – 11.760 mm (11.55 nom) | 10.10 – 10.50 mm | 12.6 – 13.0 mm |
| Lead span, E | 10.007 – 10.643 mm | 9.97 – 10.63 mm | 9.97 – 10.63 mm |
| Height, A | 2.362 – 2.642 mm | 2.65 mm max | 2.65 mm max |
| Standoff, A1 | 0.102 – 0.305 mm | 0.10 – 0.30 mm | 0.10 – 0.30 mm |
| Lead pitch, e | 1.27 mm BSC | 1.27 mm | 1.27 mm |
| Lead width, b | 0.356 – 0.482 mm | 0.31 – 0.51 mm | 0.31 – 0.51 mm |
| Lead thickness, c | 0.229 – 0.330 mm | 0.10 – 0.33 mm | 0.10 – 0.33 mm |
| Foot length, L | 0.406 – 1.270 mm | 0.40 – 1.27 mm | 0.40 – 1.27 mm |
| Lead angle | 0° – 8° | 0° – 8° | 0° – 8° |
| Pin 1 to end-pin centres | 10.16 mm (8 × 1.27) | 8.89 mm | 11.43 mm |
| Leads per side | 9 | 8 | 10 |
| Source drawing | ADI 05-08-1620 (SW, 18-lead) | TI 4221009/B | TI 4220724/A |
Note the pattern across the three columns. Every two leads add 1.27 mm of body length: 10.30 mm at 16 leads, 11.55 mm at 18, 12.80 mm at 20. Nothing else changes. Width, span, height and lead geometry are constant across the whole MS-013 family.
That is why the 18-lead outline is easy to get wrong in a library. It looks like a SOIC-16W in every dimension a quick glance checks.
Why There Is No Narrow-Body SOIC-18
Two vendor catalogues settle this better than any standards summary.
Microchip’s packaging specification lists narrow 150 mil small-outline bodies at 8, 14 and 16 leads. The 18-lead entry appears only as an 18-lead plastic small outline, wide, 300 mil body. There is no narrow 18.
NXP, in application note AN2409, publishes its complete standard SOIC offering: 8N, 14, 16N, 16W, 20W, 24W, 28W, 32W and 54W. Eighteen leads does not appear in either width. A major supplier simply does not build the package.
The practical consequence is sourcing, not geometry. An 18-pin function is usually a legacy DIP-18 part carried forward, so the SOIC-18 population skews old. Before you design one in, check the specific part’s lifecycle status rather than the package’s.
SOIC-18 Pinout and Pin 1 Identification
Numbering follows the DIP convention. Viewed from the top, pin 1 sits at the upper left, pins 1 through 9 run down the left side, and pins 10 through 18 run up the right side. Pin 9 faces pin 10 across the short end.
Because 18 is an odd multiple of two, the mid-package pins land in an unusual place. On the TI ULN2803A the ground pin is 9 and the flyback-diode common is 10, so the two highest-current nets sit diagonally opposite pin 1 and adjacent to each other. Route that pair as a plane connection, not a trace.
Pin 1 markers are the same three used across the SOIC family: a molded dot, a notch on the short end, or a beveled edge along the pin 1 side. The ADI drawing states that the notch on top and the cavities on the bottom are manufacturing options and may or may not be present, so never rely on a single marker style when writing an assembly inspection rule.
[IMAGE 2: SOIC-18 top view showing pin numbering, pin 1 index area and the pin 9 to pin 10 short-end pair | alt: “SOIC-18 pinout numbering and pin 1 identification”]
SOIC-18 Land Pattern
The MS-013 cross-section is identical at 16, 18 and 20 leads, so the pad geometry does not change with pin count. Only the number of pads does.
| Land pattern parameter | Value | Basis |
| Pad row spacing (centre to centre) | 9.30 mm | TI published for DW0016B and DW0020A |
| Pad size | 2.00 mm × 0.60 mm | TI published for DW0016B and DW0020A |
| Pads per side | 9 | 18 leads, nine per long side |
| Pad pitch | 1.27 mm × 8 spaces per side | Lead pitch, BSC |
| Copper envelope | 11.30 × 10.76 mm ≈ 122 mm² | Derived from row spacing and pad size |
| Centre-to-centre cross-check | 9.46 mm | NXP AN2409 method |
| Pad length cross-check | 1.84 mm | NXP AN2409 method |
| Pad width rule | 0.60 mm, about 60% of pitch | NXP AN2409, Table 3 |
| Stencil foil at 1.27 mm pitch | 0.125 – 0.150 mm | NXP AN2409, section 5.2.1 |
Texas Instruments publishes the same pattern for both the 16-lead and 20-lead members of this family: 9.30 mm row spacing with 2.00 mm × 0.60 mm pads on 1.27 mm pitch. The 18-lead pattern uses that same cross-section with nine pads per side. Confirm it against the specific device drawing before release rather than assuming it.
You can also derive it. NXP’s AN2409 gives the method: pad width should be roughly 60% of the lead pitch, which is 0.60 mm at 1.27 mm pitch; the pad extends 0.5 mm beyond the foot at both heel and toe; and land centre-to-centre equals the nominal tip-to-tip dimension minus half the foot length on each side.
Run the numbers. Tip to tip is 10.30 mm nominal. Foot length is 0.40 to 1.27 mm, so about 0.84 mm nominal. Centre-to-centre lands at 10.30 − 0.84 = 9.46 mm, and pad length at 0.84 + 1.0 = 1.84 mm. That is within 0.16 mm of TI’s published 9.30 mm, which is close enough to confirm you have read the drawing correctly.
Copper envelope works out at 11.30 mm across by 10.76 mm along, about 122 mm². A SOIC-16W in the same family needs 107 mm² and a SOIC-20W needs 136 mm².
Thermal Performance
| Thermal metric (°C/W) | ULN2803A, DW-18 | ISO7741, DW-16 | SN74AHC595, D-16 narrow |
| RθJA, junction to ambient | 66.4 | 83.4 | 93.8 |
| RθJC(top), junction to case | 29.5 | 46 | 54.7 |
| RθJB, junction to board | 33.0 | 48 | 50.9 |
| ψJT, junction to top | 6.0 | 19.1 | 20.8 |
| ψJB, junction to board | 32.5 | 47.5 | 50.7 |
| Body size (nominal) | 7.50 × 11.55 mm | 7.50 × 10.30 mm | 3.90 × 9.90 mm |
Treat that table as an ordering, not a controlled comparison. The three rows are different devices with different die sizes measured on JEDEC boards, so the only safe conclusion is that a larger wide body dissipates better than a smaller one.
A worked example makes the limit concrete. TI recommends holding the ULN2803A junction below 125 °C. At 85 °C ambient, allowable dissipation is (125 − 85) / 66.4 = 0.60 W. The datasheet’s own method sums each channel’s output voltage times its load current.
At 200 mA per channel, collector-emitter saturation voltage is 1.3 V max, so each active channel burns 0.26 W. Two channels reach 0.52 W and a third pushes past the budget. An eight-channel driver in SOIC-18 runs two channels at 200 mA at 85 °C. Drop to 100 mA per channel, where saturation voltage is 1.1 V max, and roughly five channels fit.
Tape, Reel and Assembly
This is the detail that catches production teams. TI ships the DW-18 at 2,000 pieces on a 330 mm reel in 24 mm tape, reel width 24.4 mm, with pocket A0 10.9 mm, B0 12.0 mm, K0 2.7 mm and a 12.0 mm pitch.
Compare that with the 16-lead wide body, which ships in 16 mm tape. Adding two leads pushes the part into the next feeder class. If your line is stocked for 8 mm and 16 mm feeders, a single SOIC-18 forces a 24 mm feeder allocation for a 2,000-piece reel, and 2,000 parts at 12.0 mm pitch is 24 m of tape.
Moisture sensitivity is device-specific rather than package-specific. TI ships the ULN2803ADW as Level-2-260C-1 YEAR, a one-year floor life. NXP rates its wide-body SOIC family at MSL 3 with the same 260 °C peak, which is 168 hours. Read the label on the dry pack, not a package reference table.
Lifecycle and Sourcing
The SOIC-18 population is thin and ageing. Digi-Key lists the TI ULN2803ADWR as obsolete and no longer manufactured, which removes the single most common 18-pin SOIC part from the mainstream catalogue.
What remains splits in two. Active mainstream silicon still exists: the Microchip PIC16F628A-I/SO ships in 18-SOIC (0.295 in, 7.50 mm width) and is stocked. For the Darlington array function, the stocked options now come from smaller suppliers. One example listing, the EVVO ULN2803A-EV, quotes $0.96 in ones and $0.45824 on a 2,000-piece reel, with 3,987 in stock and a 3-week lead time.
Watch the distributor field names. Digi-Key’s Package / Case entry reads 18-SOIC (0.295 in, 7.50 mm width), but Supplier Device Package on that same EVVO listing reads 18-SOP. Filter on Package / Case, because the supplier field will not group the parts you want.
[IMAGE 3: Decision path from an 18-pin function to SOIC-18, SOIC-20W or a repinned alternative | alt: “SOIC-18 package selection decision path for 18-pin designs”]
Four Mistakes Specific to SOIC-18
Reusing a SOIC-16W footprint. The cross-section matches, so the error passes visual review. The body is 1.25 mm longer and needs one extra pad per side.
Assuming a narrow option exists. It does not. A BOM line reading SOIC-18 is unambiguous on width, which is the one useful thing about this package.
Planning 16 mm feeders. The DW-18 arrives in 24 mm tape.
Designing in a legacy part number without a lifecycle check. The pin count itself is a warning sign that the function predates surface mount.
Frequently Asked Questions
What are SOIC-18 dimensions?
Body is 11.354 to 11.760 mm long and 7.391 to 7.595 mm wide, with a lead span of 10.007 to 10.643 mm and a height of 2.362 to 2.642 mm, per the Analog Devices 18-lead SW drawing 05-08-1620. Lead pitch is 1.27 mm and foot length 0.406 to 1.270 mm.
Is there a narrow-body SOIC-18?
No. Microchip’s packaging specification lists 18-lead small outline only as a 300 mil wide body, and NXP’s standard SOIC family omits 18 leads in both widths. Every 18-lead SOIC is the 7.50 mm MS-013 outline.
What is the SOIC-18 land pattern?
Texas Instruments publishes 9.30 mm row spacing with 2.00 mm × 0.60 mm pads at 1.27 mm pitch for the 16-lead and 20-lead members of this family, and the 18-lead cross-section is identical with nine pads per side. Deriving it from the NXP method gives 9.46 mm, which agrees within 0.16 mm.
What is the difference between SOIC-18 and SOIC-16?
Two leads and 1.25 mm of body length, if you mean SOIC-16 wide. If you mean the narrow SOIC-16, the difference is far larger: 3.90 mm body width against 7.50 mm, and a 6.00 mm lead span against 10.30 mm. The footprints share nothing.
What ICs come in a SOIC-18 package?
Darlington driver arrays such as the ULN2803 family and legacy 18-pin microcontrollers such as the Microchip PIC16F628A. The pin count comes from the DIP-18 era, so most SOIC-18 parts are surface-mount versions of older through-hole functions.
Which Package to Specify
If your device only exists in SOIC-18, use it, but plan the 24 mm feeder and verify the part’s lifecycle status before layout rather than after.
If you have a choice of package for the same function, take it. SOIC-20W costs 14 mm² more copper and buys a deeper supply base and more second sources.If you are laying out an 18-lead footprint now, check three numbers against the device drawing: body length near 11.55 mm, lead span near 10.30 mm, and nine pads per side at 1.27 mm pitch on 9.30 mm centres. Two of those three match a SOIC-16W, which is exactly why the third one is worth checking twice.
