A SOIC-14 package is a 3.90 mm wide, 8.65 mm long plastic body with seven gull-wing leads per side on 1.27 mm pitch, registered as JEDEC MS-012 variation AB. Lead span runs 5.80 mm to 6.20 mm and height tops out at 1.75 mm. The land pattern is fourteen 0.60 mm × 1.55 mm pads with 5.40 mm between pad rows, which TI and Microchip publish identically.
Key takeaways
- Outline, per TI drawing 4220718/A: body 8.55–8.75 mm × 3.80–4.00 mm, lead span 5.80–6.20 mm, height 1.75 mm max, pitch 1.27 mm, lead width 0.31–0.51 mm.
- Land pattern: 14 pads of 0.60 mm × 1.55 mm, 12 gaps of 1.27 mm, 5.40 mm row spacing, 0.07 mm solder mask clearance, 0.125 mm stencil foil.
- Pin 1 sits at the top left with the pin-1 marker; numbering runs down the left side to pin 7 and up the right side from pin 8 to pin 14.
- A second, incompatible SOIC-14 exists: TI’s DDB0014A puts 14 leads in the 9.8–10.0 mm MS-012 AC body, which is 1.25 mm longer than the standard part.
- Thermal resistance is the weak point. TI rates the same die at 133.6 °C/W in SOIC-14 against 57.5 °C/W in PDIP-14, per data sheet SCLS181H.
SOIC-14 package dimensions
Every figure below comes from TI drawing 4220718/A for the D0014A body, cross-checked against the Monolithic Power Systems outline MF-PO-D-0071. The two agree within the tolerance band on every dimension.
Table 1. SOIC-14 outline dimensions, millimeters (JEDEC MS-012 variation AB)
| Dimension | Symbol | Min | Max | Note |
| Body length | A | 8.55 | 8.75 | Excludes mold flash up to 0.15 mm per side |
| Body width | B | 3.80 | 4.00 | Excludes interlead flash up to 0.43 mm per side |
| Lead span, tip to tip | C | 5.80 | 6.20 | The dimension that identifies the package |
| Height, seated | — | 1.35 | 1.75 | MPS drawing gives the 1.35 mm lower limit |
| Lead pitch | e | 1.27 BSC | 1.27 BSC | Basic dimension, no tolerance |
| Lead width | — | 0.31 | 0.51 | MPS gives 0.33 to 0.51 |
| Foot length | L | 0.40 | 1.27 | Wide band; it drives the IPC heel calculation |
| Pin row length | — | 7.62 | 7.62 | Six pitches, reference |
Two numbers matter more than the rest. Lead span identifies the package against every other 14-lead body, and foot length is the term that makes IPC and vendor land patterns disagree.
[IMAGE 1: SOIC-14 outline drawing with body length, body width, lead span, height and pitch dimensioned, plus the pin-1 index area | alt: “SOIC-14 package dimensions showing 8.65 mm body, 6.0 mm lead span and 1.27 mm pitch”]
SOIC-14 pinout and numbering
Pin numbering is fixed by the package, not by the device. Viewed from the top with the pin-1 index at the upper left, pins 1 through 7 run down the left side and pins 8 through 14 run up the right side. That counterclockwise order matches the DIP-14 it replaced, so a DIP schematic symbol maps straight across.
Function assignment is device-specific, but the 74-series convention is worth knowing because it covers thousands of parts: pin 7 is GND and pin 14 is VCC. On the SN74HC00 the four NAND gates occupy pins 1 to 6 and 8 to 13, with inputs and outputs grouped per gate.
The index feature varies. Some vendors mold a dot over pin 1, others cut a notch in the body end, and some bevel the edge along the pin 1 side. All three are valid; only the silkscreen on your board has to be unambiguous.
SOIC-14 land pattern
Three vendor drawings and one standard calculation give four answers for the same package. They agree on the toe and diverge at the heel.
Table 2. SOIC-14 land pattern, four sources, millimeters
| Source | Pad width X | Pad length Y | Row spacing C | Toe-to-toe Z | Heel gap G |
| TI drawing 4220718/A | 0.60 | 1.55 | 5.40 | 6.95 | 3.85 |
| Microchip C04-2065-OD Rev D | 0.60 | 1.55 | 5.40 | 6.95 | 3.85 |
| MPS MF-PO-D-0071 | 0.61 | 1.60 | 5.40 | 7.00 | 3.80 |
| IPC-7351B Nominal, calculated | 0.61 | 2.18 | 4.74 | 6.92 | 2.56 |
The IPC row is calculated from the Table 1 limits at Nominal density, using the standard toe and heel allowances of 0.35 mm each and 0.10 mm for fabrication and placement. The heel collapses because the foot-length band of 0.40 mm to 1.27 mm enters the equation as a 2.14 mm root-sum-square penalty, which pushes copper inward by 0.63 mm per pad.
Use the vendor pattern for production reflow and the IPC Level A pattern when the board will be hand-soldered or reworked. Both drawings specify non-solder-mask-defined pads with 0.07 mm of clearance all around, and both dimension the paste example for 0.125 mm stencil foil.
For courtyard, the land pattern extends 6.95 mm across the pads and the 8.75 mm maximum body length governs the other axis. Adding the 0.25 mm Nominal courtyard excess per side and rounding outward gives roughly 7.45 mm × 9.25 mm, about 69 mm² of reserved board area.
The other SOIC-14, and why it breaks boards
TI publishes a second 14-lead SOIC under drawing 4222925/A, the DDB0014A. It references MS-012 variation AC, which is the 16-lead body: 9.8 mm to 10.0 mm long instead of 8.55 mm to 8.75 mm. Fourteen leads sit in a sixteen-lead outline with two positions vacant, and the drawing still labels pins 1, 8, 9 and 16.
The pads themselves match the standard part at 0.60 mm × 1.55 mm on 5.40 mm spacing, so the two footprints look identical in a thumbnail. The difference is pad count along each row and a 1.25 mm longer body. Dropping a standard SOIC-14 footprint under this part leaves two leads hanging past the copper.
The same trap appears with parts that remove a pin for creepage, where the library entry keeps the 16-lead length. Check the pin row count on the drawing, not the pin count in the part number.
Thermal and electrical trade-offs at 14 pins
TI publishes the SN74HC00 die in five 14-pin bodies, all measured per JESD 51-7, which makes the package the only variable.
Table 3. One die, five 14-pin packages (TI SCLS181H, revised August 2021)
| Package | Body size | RθJA | ψJB | Note |
| PDIP (N) | 19.30 × 6.40 mm | 57.5 °C/W | 37.2 °C/W | Through hole, best of the five |
| SO / EIAJ (NS) | 10.20 × 5.30 mm | 91.0 °C/W | 49.5 °C/W | 5.30 mm body, 1.27 mm pitch |
| SSOP (DB) | 6.50 × 5.30 mm | 108.3 °C/W | 55.2 °C/W | 0.65 mm pitch |
| SOIC (D) | 8.70 × 3.90 mm | 133.6 °C/W | 89.1 °C/W | The subject of this article |
| TSSOP (PW) | 5.00 × 4.40 mm | 151.7 °C/W | 94.1 °C/W | 1.2 mm max height |
Read the revision history before trusting any of those numbers elsewhere. In revision F the same SOIC entry read 94.7 °C/W; revisions G and H raised it to 133.6 °C/W with no change to the package, and TI logged the change as updated thermal values. A designer working from a cached PDF will underestimate the rise by 40 percent.
A worked case: four gates dissipating 150 mW at a 70 °C ambient reach about 90 °C junction in this body, which is comfortable. The same 150 mW in a sealed enclosure at 105 °C ambient reaches 125 °C, and at that point ψJB of 89.1 °C/W says the board is doing very little of the cooling.
Cost, stock and second sources
Package choice at 14 pins is often a supply decision rather than a technical one. Reading DigiKey on 13 August 2026 for the same NAND gate in two bodies gives a result that contradicts the usual assumption.
Table 4. SN74HC00, SOIC-14 against TSSOP-14, DigiKey US, read 13 August 2026
| Metric | SN74HC00DR (14-SOIC) | SN74HC00PWR (14-TSSOP) |
| Unit price, quantity 1 | $0.40000 | $0.42000 |
| Unit price, quantity 100 | $0.21270 | $0.22450 |
| Full-reel unit price | $0.17105 (2500 pcs) | $0.18286 (2000 pcs) |
| Stock at time of reading | 9,042 | 20,662 |
| Manufacturer lead time quoted | 9 weeks | 6 weeks |
The SOIC version was about 6 percent cheaper per piece at reel quantity, and the TSSOP carried more than twice the stock and a shorter quoted lead time. Neither package is reliably the cheap one; check the pair on the day you commit.
Second sourcing is straightforward at this pin count. The same listing shows three drop-in alternatives in the identical body, including an onsemi MC74HC00ADR2G at $0.32000 and a Toshiba TC74HC00AFELF at $0.41000, all sharing the footprint. Lifecycle is worth a check too: the tube-packed SN74HC00D is marked obsolete while the tape-and-reel SN74HC00DR stays active, and the SSOP option is flagged not recommended for new designs.
[IMAGE 2: side-by-side footprint outlines for SOIC-14, SSOP-14 and TSSOP-14 at the same scale with courtyard areas shaded | alt: “SOIC-14 land pattern compared with SSOP-14 and TSSOP-14 footprints”]
Five mistakes worth avoiding
- Reusing a SOIC-16 footprint because the pads match. Row spacing and pad size are identical; the pin count per row is not.
- Assuming the 5.30 mm EIAJ SO-14 is the same part. Its 10.20 mm body will not sit on this pattern.
- Copying an RθJA figure from an old datasheet copy. Check the revision letter and date on every thermal number.
- Placing the pin-1 silkscreen marker under the body, where the part hides it during inspection.
- Sizing a footprint from the nominal 8.65 mm body length. Use the 8.75 mm maximum for courtyard, or adjacent parts will collide.
Frequently asked questions
What are the dimensions of a SOIC-14 package?
Body 8.55 mm to 8.75 mm long by 3.80 mm to 4.00 mm wide, lead span 5.80 mm to 6.20 mm, height 1.75 mm maximum, pitch 1.27 mm, lead width 0.31 mm to 0.51 mm. Those limits come from TI drawing 4220718/A, which references JEDEC MS-012 variation AB.
What is the footprint for a SOIC-14?
Fourteen pads of 0.60 mm × 1.55 mm on 1.27 mm pitch, with 5.40 mm between the two pad-row centers. Solder mask is pulled back 0.07 mm all around on a non-solder-mask-defined pad, and the paste stencil is dimensioned for 0.125 mm foil.
How are SOIC-14 pins numbered?
From the top view with the pin-1 index at the upper left, numbering runs down the left side from pin 1 to pin 7, then up the right side from pin 8 to pin 14. This matches DIP-14 numbering, which is why the two share schematic symbols.
Is SOIC-14 the same as SO-14 or TSSOP-14?
No. SO-14 often means the 5.30 mm EIAJ body with a 10.20 mm length, and TSSOP-14 uses 0.65 mm pitch in a 5.00 mm × 4.40 mm body with a 5.8 mm land span. All three need separate footprints. Compare lead span on the drawing before reusing anything.
Can SOIC-14 be hand-soldered?
Yes. At 1.27 mm pitch the copper gap between 0.60 mm pads is 0.67 mm, which tolerates drag-soldering with flux and leaves a visible fillet for inspection. Use the IPC Level A pattern if hand assembly is the plan, since the longer toe gives the iron somewhere to land.
What to do next
Pull the drawing for your exact orderable part number and confirm the lead span is near 6.0 mm and the body length near 8.65 mm; if it reads 9.9 mm you have the 16-lead outline and need a different pattern. Take the pads from Table 2, using the vendor row for reflow production and the IPC row for hand-built boards. Then check the thermal table in the current datasheet revision rather than a stored copy, and price both the SOIC and TSSOP versions before releasing the bill of materials, because at 14 pins the cheaper body changes from part to part.
Sources
- Texas Instruments, SNx4HC00 data sheet SCLS181H, December 1982, revised August 2021 – package drawing D0014A (4220718/A, 09/2016), 14-pin thermal table, pinout, orderable status and tape-and-reel data – https://www.ti.com/lit/ds/symlink/sn74hc00.pdf
- Texas Instruments, DDB0014A package drawing 4222925/A, 04/2016 – 14 leads in a JEDEC MS-012 variation AC body – https://www.ti.com/lit/ml/mpdc008/mpdc008.pdf
- Monolithic Power Systems, package outline drawing for 14-SOIC, MF-PO-D-0071 revision 0.0 – outline limits and recommended land pattern – https://media.monolithicpower.com/cms_document/Package%20Information/SOIC-14%20POD.pdf
- Microchip, 14-Lead Plastic Small Outline (OD) Narrow 3.90 mm Body [SOIC], drawing C04-2065-OD Rev D – recommended land pattern – https://ww1.microchip.com/downloads/aemDocuments/documents/corporate-responsibilty/environmental/material-compliance-documents/14LSOIC3_90mm(OD)C04-00065d.pdf
- NXP / Freescale, AN2409 Rev 3.0, 10/2014 – SOIC body sizes, pad width rule, stencil thickness and MSL – https://www.nxp.com/docs/en/application-note/AN2409.pdf
- DigiKey product listing, SN74HC00DR, pricing and stock read 13 August 2026 – https://www.digikey.com/en/products/detail/texas-instruments/SN74HC00DR/276830
- DigiKey product listing, SN74HC00PWR, pricing and stock read 13 August 2026 – https://www.digikey.com/en/products/detail/texas-instruments/SN74HC00PWR/377066
