A SOIC package is a plastic surface-mount IC body with gull-wing leads on two sides at 1.27 mm pitch, registered by JEDEC in two widths: 3.90 mm under MS-012 and 7.50 mm under MS-013. It displaced the DIP for most 8 to 28 pin devices and stays in production because it leaves a 0.67 mm copper gap between pads, an inspectable solder fillet, and enough room for a soldering iron.

Key takeaways

• Two JEDEC widths dominate: MS-012 at 3.90 mm body and 1.75 mm maximum height, MS-013 at 7.50 mm and 2.65 mm. A third outline, the EIAJ 5.30 mm body, also ships labeled SOIC.
• Standard land pattern for narrow body: 0.60 mm × 1.55 mm pads at 1.27 mm pitch with 5.40 mm between pad rows, published identically by TI and Microchip.
• Thermal resistance beats the smaller alternatives. One SN74HC595 die measures 73 °C/W in narrow SOIC and 108 °C/W in TSSOP, per data sheet SCLS041H.
• It is not the cheapest option. At DigiKey on 13 August 2026, the same shift register cost $0.27488 in SOIC reel quantity against $0.22400 in TSSOP.
• Assembly is forgiving: 0.125 mm stencil foil, MSL 2 or 3 at 260 °C peak depending on the device, and 12 mm or 16 mm tape.
• Pick something else when height must drop below 1.75 mm, when board area is the binding constraint, or when the pin count passes 28 at 1.27 mm pitch.

What a SOIC package actually is

The construction is a copper leadframe, a die attached to a central paddle, wire bonds, and an epoxy mold compound over the top. The leads exit the two long sides and are formed into the gull-wing shape that gives the joint its compliance. NXP describes the standard Pb-free finish on these leads as matte tin in AN2409.

Three properties follow from that geometry and explain why the SOIC package survives against smaller options. The compliant lead absorbs the mismatch between the silicon, the mold compound and the FR-4 board across temperature. The exposed fillet can be inspected optically rather than by X-ray. And the 1.27 mm pitch leaves 0.67 mm of bare laminate between 0.60 mm pads, which is a wide process window for solder paste.

Naming is inconsistent across vendors. SOIC-8, SO-8, SOIC-8N and SOP-8 can all point at the same outline or at three different ones. The reliable identifier is the lead span on the mechanical drawing, not the label.

[IMAGE 1: cutaway of a SOIC package showing leadframe, die paddle, wire bonds, mold compound and gull-wing lead form | alt: “SOIC package cutaway showing leadframe, die paddle and gull-wing leads”]

The four outlines that get called SOIC

Two JEDEC registrations cover most parts. A third outline comes from the Japanese standard, and a fourth exists only for 8-lead isolators, where the die needs a wide body but the pinout needs eight leads.

Table 1. SOIC outlines, dimensions in millimeters

Outline	Registration	Body width	Lead span	Max height	Pitch	Typical lead counts
Narrow body	JEDEC MS-012	3.90	5.80–6.19	1.75	1.27	8, 14, 16
Wide body	JEDEC MS-013	7.50	9.97–10.63	2.65	1.27	16, 20, 24, 28
Wide body, fine pitch	JEDEC MS-013	7.50	9.97–10.63	2.45–2.65	0.65	32, 54
Wide body, 8 lead	vendor outline	7.50	11.25–11.75	2.80	1.27	8
EIAJ Type II	JEITA	5.30	vendor drawing	varies	1.27	8 and up

Body length grows with lead count while the width stays fixed, which is what sets the courtyard. NXP lists the family in AN2409: 3.90 mm × 4.90 mm for 8 leads, 3.90 mm × 8.60 mm for 14, 3.90 mm × 9.90 mm for 16 narrow, then 7.50 mm × 10.30 mm for 16 wide, rising to 7.50 mm × 17.90 mm at 28 leads.

Footprint: the numbers to put in your library

For a narrow-body part, TI drawing 4214825/C and Microchip drawing C04-2057-C2X Rev K specify the same land pattern: eight pads of 0.60 mm × 1.55 mm on 1.27 mm pitch, with 5.40 mm between pad-row centers. That places the toes 6.95 mm apart and leaves a 3.85 mm heel gap.

For a 16-lead wide-body part, TI drawing 4220721/A gives 2.00 mm × 0.60 mm pads at 9.30 mm row spacing. Both drawings specify a non-solder-mask-defined pad with 0.07 mm of mask clearance all around, and both dimension the paste example for 0.125 mm stencil foil.

Two cautions. First, an IPC-7351B calculation run on the same MS-012 limits returns a longer pad, roughly 2.18 mm at Nominal density, because the JEDEC foot-length tolerance of 0.41 mm to 1.27 mm dominates the heel equation. Second, exposed-pad variants need their own pattern: NXP requires at least 0.25 mm between the thermal land and the lead pads, thermal vias of 0.30 mm to 0.33 mm on a 1.2 mm grid, and a stencil aperture 0.25 mm smaller than the copper.

Thermal performance against the alternatives

Package choice moves junction temperature more than most designers expect. TI publishes the SN74HC595 in six packages, all measured per JESD 51-7, which isolates the package variable because the die is identical.

Table 2. One die, six packages: SN74HC595 (TI data sheet SCLS041H)

Package	Body size	Body area	RθJA	Note
SOIC wide (DW), 16	10.30 × 7.50 mm	77 mm²	57 °C/W	Best of the surface-mount options
SO / EIAJ (NS), 16	not published	—	64 °C/W	The 5.30 mm middle width
PDIP (N), 16	through hole	—	67 °C/W	Through-hole reference
SOIC narrow (D), 16	9.90 × 3.90 mm	39 mm²	73 °C/W	The default choice
SSOP (DB), 16	6.20 × 5.30 mm	33 mm²	82 °C/W	0.65 mm pitch
TSSOP (PW), 16	5.00 × 4.40 mm	22 mm²	108 °C/W	43% less area, 48% worse thermally

Work the numbers. At 500 mW dissipation and 85 °C ambient, that die runs near 121 °C in narrow SOIC and near 139 °C in TSSOP. The TSSOP still passes on paper, but the margin to a 150 °C limit has shrunk to 11 °C before any neighbouring heat source is counted.

For higher power, the exposed-pad variant, marked -EP by NXP, moves the primary heat path from the leads to a soldered slug under the body. That option needs a thermal plane and a via array to be worth anything, which is a board decision rather than a package decision.

Why isolators still use the wide body

Creepage scales with body width, and no amount of silicon improvement changes that. TI ships the ISO7721 in three packages from the same die, and the insulation table in SLLSEP3G makes the trade explicit: 4 mm of creepage and clearance in the 8-lead narrow body against 8 mm in the 16-lead wide body.

That distance sets the ratings. The narrow version is certified to 3000 VRMS under UL 1577 with a 450 VRMS maximum working voltage, while the wide version reaches 5000 VRMS and 1500 VRMS. Under CSA 62368-1 the narrow package is basic insulation at 400 VRMS; the wide package is reinforced at 600 VRMS.

The land pattern can spend that margin. TI dimensions its IPC-nominal footprint for the 16-lead wide body at 7.3 mm of board creepage and offers a high-voltage layout, with 1.65 mm pads at 9.75 mm spacing, that restores 8.1 mm. Choosing the part and then using the default library footprint fails the requirement the part was chosen to meet.

Assembly, MSL and handling

A 1.27 mm-pitch SOIC package is one of the easiest devices on a modern line. NXP recommends 0.125 mm to 0.150 mm stencil foil at that pitch and a pad width near 60 percent of pitch, which is where the 0.60 mm figure comes from. Below 0.65 mm pitch, on the 32- and 54-lead wide bodies, that drops to 0.100 mm to 0.125 mm foil and a 0.38 mm pad.

Moisture sensitivity is device-specific rather than package-specific. NXP classifies its SOIC family at MSL 3 with a 260 °C peak in AN2409, while TI lists the ISO7721 in the same body style as Level 2 at 260 °C with a one-year floor life. Read the label on the dry pack, not the package name.

Reels differ by body. TI supplies 8-lead narrow parts on 12 mm tape at 2500 pieces, 16-lead narrow parts on 16 mm tape at 2500, and 16-lead wide parts on 16 mm tape at 2000. Feeder allocation and reel-change frequency both follow from that, which matters on a line running a single high-mix panel.

On counterfeit risk, the SOIC package is a frequent target because the surface is large enough to remark and the parts are commodity-priced. Buy through authorized distribution, compare the laser mark and date code against the vendor marking guide, and treat a broker offer of a long-lead part at spot pricing as a reason to decap a sample.

Cost and availability reality check

The common claim that SOIC is the cheap option does not survive a price check. Reading DigiKey on 13 August 2026 for the same TI shift register in two bodies gives the figures below.

Table 3. SN74HC595, SOIC against TSSOP, DigiKey US pricing read 13 August 2026

Metric	SN74HC595DR (16-SOIC)	SN74HC595PWR (16-TSSOP)
Unit price, quantity 1	$0.61000	$0.50000
Unit price, quantity 100	$0.33650	$0.27330
Full-reel unit price	$0.27488 (2500 pcs)	$0.22400 (2000 pcs)
Stock at time of reading	14,787	6,659
Manufacturer lead time quoted	16 weeks	6 weeks

The SOIC package costs about 23 percent more per piece at reel quantity than the TSSOP of the same die, and carried a longer quoted factory lead time on that date. What it buys is assembly margin, rework access and the thermal difference in Table 2.

Lifecycle is the quiet advantage. The TI shift register above carries an original data sheet date of December 1982, and its SOIC orderable is still listed Active in 2026. Package families that reach volume in this body tend to stay orderable for decades, which is why industrial and automotive programs with fifteen-year build horizons keep specifying it long after a consumer design would have moved to a leadless body.

Second sourcing is the other half of the answer. The same listing shows an onsemi MC74HC595ADR2G marked as a direct substitute at $0.46000 with 280,998 pieces in stock, which is the usual pattern for jellybean logic in this body: one manufacturer is short, another is not, and the footprint is identical.

[IMAGE 2: bar chart of reel-quantity unit price and RθJA for SOIC, SSOP and TSSOP versions of the same die | alt: “SOIC package price and thermal resistance compared with SSOP and TSSOP”]

When to choose something else

• Height under 1.75 mm: go to TSSOP or a leadless body. No SOIC variant clears that limit.
• Board area is binding: the 16-lead TSSOP body occupies 22 mm² against 39 mm² for narrow SOIC, before courtyard.
• Pin count above 28 at 1.27 mm pitch: MS-013 stops there. Fine-pitch wide bodies reach 54, then QFP or QFN takes over.
• Power above roughly 1 W: an exposed-pad SOIC or a QFN with a thermal pad, because plain leadframe conduction runs out.
• Mains-referenced isolation: wide body only, and check creepage against the certification target rather than the kilovolt headline.
• Hand assembly, prototyping, field rework: stay with SOIC. It is the largest pitch still in volume production for these functions.

Design mistakes that cause real failures

• Using one footprint for narrow and wide bodies. The pad rows sit 5.40 mm apart against 9.30 mm, and no compromise pattern works.
• Treating the 5.30 mm EIAJ outline as a JEDEC SOIC. Its lead span matches neither pattern, and the toes land on pad edges.
• Printing a single full-size aperture over an exposed pad, which floats the package and starves the lead joints.
• Assuming the package name in the schematic symbol carries the outline. Put the vendor package suffix in the symbol.
• Ignoring MSL on a board that will see two reflow passes plus rework. Three passes is the standard qualification, and a bake is cheaper than delamination.

Frequently asked questions

What does SOIC stand for?

Small Outline Integrated Circuit. It describes a surface-mount plastic package with gull-wing leads along two sides at 1.27 mm pitch. JEDEC registers the common outlines as MS-012 for the 3.90 mm body and MS-013 for the 7.50 mm body.

What is the difference between SOIC and SOP?

The terms overlap. TI and several other vendors reserve SOIC for the JEDEC 3.90 mm and 7.50 mm bodies and use SOP or SO for the EIAJ 5.30 mm outline. Since the lead spans differ, treat the two names as a prompt to open the drawing rather than as a specification.

What is the pin pitch of a SOIC package?

1.27 mm, equal to 50 mil, on every standard SOIC. The exceptions are the 32-lead and 54-lead wide bodies, which shrink to 0.65 mm to fit more leads on the same body length. Pitch is a basic dimension and carries no tolerance.

Can you hand-solder a SOIC package?

Yes. The 1.27 mm pitch and the exposed gull-wing fillet make it the largest surface-mount IC body still in wide production, and drag-soldering with flux works reliably. Use the IPC Level A land pattern if the board will be assembled or reworked by hand, since it adds toe length for the iron.

Is SOIC better than TSSOP?

For heat and handling, yes. The same SN74HC595 die measures 73 °C/W in narrow SOIC and 108 °C/W in TSSOP. For area and unit cost, no: the TSSOP body is 43 percent smaller and priced about 18 percent lower at reel quantity. Choose on whichever constraint is binding.

What does the -EP suffix mean on a SOIC?

It marks an exposed pad version, where the die paddle is exposed on the bottom of the package and soldered to a thermal land. NXP notes that this becomes the primary heat path and also serves as a ground connection, but only when the board provides a thermal plane and a via array under the pad.

What to do next

Start with the mechanical drawing for the exact orderable part number, record the lead span, and match it to Table 1 before touching the library. Take the land pattern from the vendor drawing for production reflow, or run IPC-7351B at Level A if the board will be hand-assembled. If the device dissipates real power, compare RθJA across the vendor package options the way Table 2 does rather than assuming the physically larger body wins. Then price both bodies at your build quantity and check stock on the day, because on this class of part the package that ships is often worth more than the package that measures best.

Sources

• Texas Instruments, SNx4HC595 data sheet (SCLS041H, revised November 2009; device information and package data current revision) – thermal impedance per JESD 51-7 and body sizes across six packages – https://www.ti.com/lit/ds/symlink/sn74hc595.pdf
• Texas Instruments, ISO7720/ISO7721 data sheet SLLSEP3G, revised May 2024 – insulation specifications, thermal information, tape-and-reel data, package drawings D0008B / DW0016B / DWV0008A – https://www.ti.com/lit/ds/symlink/iso7721.pdf
• Texas Instruments, D0008A package drawing 4214825/C, 02/2019 – JEDEC MS-012 AA outline and land pattern example – https://www.ti.com/lit/pdf/msoi002k
• Texas Instruments, DW0016A package drawing 4220721/A, 07/2016 – JEDEC MS-013 outline and land pattern example – https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/14/DW16drawing.pdf
• NXP / Freescale, AN2409 Rev 3.0, 10/2014, Small Outline Integrated Circuit (SOIC) Package – body sizes, pad rules, exposed-pad and stencil guidance, MSL ratings – https://www.nxp.com/docs/en/application-note/AN2409.pdf
• Microchip, recommended land pattern drawing C04-2057-C2X Rev K, published in LR645 data sheet DS20005384B – https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/LR645-Data-Sheet-DS20005384.pdf
• DigiKey product listings for SN74HC595DR and SN74HC595PWR, pricing and stock read 13 August 2026 – https://www.digikey.com/en/products/detail/texas-instruments/SN74HC595DR/296-14857-1-ND/562567