Narrow-body SOIC is JEDEC MS-012: a 3.90 mm body, a 6.00 mm nominal lead span and a 1.75 mm height limit. Wide-body SOIC is MS-013: a 7.50 mm body, a 10.30 mm lead span and a 2.65 mm limit. The SOIC narrow vs wide decision is rarely about pin count. It is about heat and creepage, and both are measurable. A TI ISO7721 offers 4 mm of creepage in the narrow package and 8 mm in the wide one.

Key takeaways

• Narrow body, JEDEC MS-012: 3.90 mm body, 5.80 mm to 6.19 mm lead span, 1.75 mm maximum height, 8 to 16 leads on 1.27 mm pitch.
• Wide body, JEDEC MS-013: 7.50 mm body, 9.97 mm to 10.63 mm lead span, 2.65 mm maximum height, 16 to 28 leads on 1.27 mm pitch and 32 or 54 leads on 0.65 mm pitch.
• Thermal: the SN74HC595 die measures 73 °C/W junction-to-ambient in the narrow D package and 57 °C/W in the wide DW package, per data sheet SCLS041H.
• Isolation: the ISO7721 gives 4 mm creepage and 3000 VRMS in the narrow D-8, against 8 mm and 5000 VRMS in the wide DW-16, per SLLSEP3G.
• A careless footprint discards the difference. TI dimensions its IPC-nominal land pattern for the DW-16 at 7.3 mm of board creepage and its high-voltage option at 8.1 mm.
• Board cost: a wide 16-lead courtyard runs about 130 mm² against 78 mm² narrow, and the parts arrive on 16 mm tape at 2000 per reel instead of 12 mm tape at 2500.

SOIC narrow vs wide: the dimensional split

Four package families ship under the SOIC label. Three are JEDEC and one is not, which is where most footprint mistakes start.

Table 1. SOIC body variants, dimensions in millimeters

Variant	JEDEC	Body width	Lead span	Max height	Lead counts	Pitch
Narrow body (SOIC-N)	MS-012	3.90	5.80–6.19	1.75	8, 14, 16	1.27
Wide body (SOIC-W)	MS-013	7.50	9.97–10.63	2.65	16, 20, 24, 28	1.27
Wide body, fine pitch	MS-013	7.50	9.97–10.63	2.65 (2.45 for 54L)	32, 54	0.65
Wide body, 8 lead (TI DWV)	not MS-012/013	7.50	11.25–11.75	2.80	8	1.27
EIAJ / JEITA Type II	none	5.30	see vendor drawing	varies	8 and up	1.27

The 8-lead wide-body outline in the fourth row deserves attention. TI drawing 4218796/A gives it an 11.5 mm ±0.25 mm lead span and a 5.75 mm to 5.95 mm body length, so it is longer across the leads than a 16-lead wide body is, and it fits neither MS-012 nor MS-013. Any library entry named SOIC-8 will be wrong for it.

[IMAGE 1: top-down outlines of MS-012 narrow, MS-013 wide and the 8-lead wide body drawn to the same scale with lead spans labeled | alt: “SOIC narrow vs wide body outlines showing 3.9 mm and 7.5 mm bodies to scale”]

How to tell which one you have

Package suffixes are the fastest check when the vendor is known. TI uses D for narrow SOIC, DW for 16-lead and larger wide SOIC, and DWV for the 8-lead wide body, while NS means the EIAJ-derived SO outline and DB means SSOP. Ordering an ISO7721DR instead of an ISO7721DWR changes the footprint, the creepage and the isolation rating in one letter.

When the suffix is unfamiliar, measure from the mechanical drawing instead. A lead span near 6.0 mm is narrow body, near 10.3 mm is wide body, and near 11.5 mm is the 8-lead wide outline. Body width alone is a weaker test, because the EIAJ 5.3 mm outline sits between the two JEDEC widths and is often sold as SOIC by distributors.

Check the reel too. TI ships D-8 parts in 12 mm tape and DW-16 parts in 16 mm tape, so a footprint error usually shows up as a feeder that will not accept the reel before it shows up as a failed board.

Thermal performance: the wide body usually wins

A wide body carries a larger die paddle and more leadframe metal, which shortens the path from junction to board. The SN74HC595 is the cleanest comparison available, because TI publishes six package options for one die in data sheet SCLS041H, measured per JESD 51-7.

Table 2. Junction-to-ambient thermal resistance for one die across packages, SN74HC595 (SCLS041H)

Package	Body	RθJA (°C/W)	Relative to narrow SOIC
DW (SOIC), 16 pins	Wide, 7.50 mm	57	22% lower
NS (SO), 16 pins	EIAJ, 5.30 mm	64	12% lower
N (PDIP), 16 pins	Through hole	67	8% lower
D (SOIC), 16 pins	Narrow, 3.90 mm	73	baseline
DB (SSOP), 16 pins	Shrink, 5.30 mm	82	12% higher
PW (TSSOP), 16 pins	Thin, 4.40 mm	108	48% higher

Work an example. A shift register dissipating 500 mW at an 85 °C ambient reaches a junction temperature of about 121 °C in the narrow package and 114 °C in the wide one. Neither exceeds the rating, but the 7 °C margin matters when the part sits next to a regulator and the derating curve is already tight.

The same pattern holds for isolators, where it is quantified as safety limiting power. The ISO7721 datasheet lists 908 mW for the D-8 package and 1445 mW for the DW-16 at 25 °C ambient and a 150 °C junction, a 59 percent increase from body width alone.

Creepage and clearance: the real reason wide body exists

Signal isolation is where the two bodies stop being interchangeable. Creepage is the shortest path across the package surface between the two sides of the barrier, and it scales with body width because there is nowhere else for the distance to come from.

Table 3. Same isolator die, three packages (TI ISO7721, SLLSEP3G May 2024)

Parameter	D-8 narrow	DWV-8 wide	DW-16 wide
External creepage and clearance	4 mm	8.5 mm	8 mm
Withstand isolation, UL 1577	3000 VRMS	5000 VRMS	5000 VRMS
Maximum working isolation voltage	450 VRMS	1500 VRMS	1500 VRMS
Maximum surge isolation voltage	10000 VPK	12800 VPK	12800 VPK
Overvoltage category at 600 VRMS mains	not rated	I–IV	I–IV
CSA 62368-1 insulation class	Basic, 400 VRMS	Reinforced, 600 VRMS	Reinforced, 600 VRMS
RθJA	137.7 °C/W	84.3 °C/W	86.5 °C/W

Read the last two rows together. The narrow package is not a cheaper version of the same function; it is a basic-insulation part capped at 400 VRMS working voltage with 63 percent worse thermal resistance. On a 230 VAC mains-referenced design, the narrow option is out of scope before cost enters the conversation.

One caveat on the headline numbers. Skyworks documents in AN583 that a standard JEDEC 16-lead wide-body SOIC measures 7.6 mm of creepage rather than the nominal 8 mm, because tie-bar metal remains on the package sides after singulation, and that conformal coating is needed to recover the full distance. Applications specifying 8 mm for 220 VAC to 250 VAC medical and industrial equipment need to account for that gap.

Your land pattern can throw the creepage away

Package creepage is an upper bound. What the certification body measures is the copper on your board, and a standard IPC land pattern extends the pads inward from the leads on both sides of the barrier. TI publishes two footprints per isolator package for exactly this reason.

• DW-16 wide body, drawing 4221009/B: the IPC-nominal layout uses 2.00 mm × 0.60 mm pads at 9.3 mm row spacing and leaves 7.3 mm of board clearance and creepage. The high-voltage option shortens the pads to 1.65 mm and spreads them to 9.75 mm, recovering 8.1 mm.
• D-8 narrow body, drawing 4221445/C: the IPC-nominal layout gives 3.85 mm; the high-voltage option, using 1.40 mm pads at 5.5 mm spacing, gives 4.1 mm.
• DWV-8 wide body, drawing 4218796/A: a single layout with 1.80 mm × 0.60 mm pads and a 10.9 mm outer span, dimensioned at 9.1 mm nominal clearance and creepage.

The consequence is blunt. Specifying a DW-16 isolator for its 8 mm rating and then dropping in the default library footprint leaves 7.3 mm on the assembled board, which fails the requirement the part was chosen to meet. Slotting the board under the barrier is the usual remedy when the layout cannot be widened.

[IMAGE 2: DW-16 land pattern shown twice, IPC nominal at 7.3 mm and HV option at 8.1 mm, with the creepage path highlighted | alt: “Wide body SOIC land pattern creepage of 7.3 mm versus 8.1 mm”]

Board area, height and the assembly line

Wide body costs area in two dimensions. Including a Nominal-density courtyard, a 16-lead wide part occupies roughly 11.8 mm × 11.0 mm, about 130 mm². The narrow 16-lead equivalent is roughly 7.45 mm × 10.5 mm, about 78 mm². An 8-lead narrow part needs only 41 mm², so a wide 16 costs the area of three narrow 8s.

Height matters where a board slots into an enclosure or stacks under a display. Narrow body is capped at 1.75 mm, wide body at 2.65 mm, and TI’s 8-lead wide body at 2.80 mm. That 1.05 mm swing has ended more package decisions than thermal margin has.

On the line, tape width follows body width. TI supplies ISO7721 narrow parts on 12 mm tape at 2500 pieces per reel, the DW-16 on 16 mm tape at 2000, and the DWV-8 on 16 mm tape at 1000 pieces. Wide-body parts consume the wider feeder slots and force reel changes more often at the same build volume.

Moisture sensitivity does not track body width. Both ISO7721 package options are classified Level 2 at 260 °C, while NXP rates its whole SOIC family, narrow and wide, at MSL 3 with a 260 °C peak in AN2409. Check the specific device rather than assuming the larger body bakes differently.

Decision path

Five conditions settle SOIC narrow vs wide in practice, and they are checked in this order.

• Crossing a mains-referenced or safety-rated barrier: wide body, and confirm the working voltage and overvoltage category, not just the kilovolt headline.
• Dissipating more than a few hundred milliwatts with no exposed pad: wide body buys roughly 20 percent lower RθJA on the same die.
• More than 16 leads at 1.27 mm pitch: wide body is the only JEDEC option; MS-012 stops at 16.
• Height limit below 2.65 mm, or board area under pressure: narrow body, and move heat with copper pour and vias instead.
• Second-sourcing an existing design: match the lead span on the drawing, since two vendors can both call a part SOIC-16 and ship different outlines.

Five mistakes that reach the assembler

• Ordering the D suffix when the schematic called for DW. The parts place and reflow on the wrong footprint only if someone forces them; usually the line stops.
• Reusing a SOIC-8 footprint for an 8-lead wide-body isolator, whose lead span is 11.5 mm rather than 6.0 mm.
• Treating the 5.3 mm EIAJ outline as a narrow SOIC. Its lead span misses both JEDEC patterns and the toes land on pad edges.
• Buying an 8 mm creepage package and laying it out at 7.3 mm.
• Assuming wide body always dissipates better. It does on a shared die, but a narrow package with an exposed pad beats a plain wide body every time.

Frequently asked questions

What is the difference between SOIC narrow and wide?

Narrow body follows JEDEC MS-012 with a 3.90 mm body, a 5.80 mm to 6.19 mm lead span and a 1.75 mm height limit. Wide body follows MS-013 with a 7.50 mm body, a 9.97 mm to 10.63 mm lead span and a 2.65 mm limit. They need different land patterns and are not interchangeable on a board.

How do I know if my SOIC-8 is narrow or wide?

Read the lead span on the mechanical drawing. About 6.0 mm means narrow body to MS-012. About 11.5 mm means an 8-lead wide-body outline such as TI’s DWV, which is used for isolators. The vendor suffix is the shortcut: D is narrow at TI, DW and DWV are wide.

Is wide-body SOIC better for heat?

Usually yes, for the same die. TI publishes 57 °C/W for the SN74HC595 in the wide DW package against 73 °C/W in the narrow D package. The advantage disappears against any package with an exposed thermal pad, which moves heat through the board rather than the leadframe.

Why do digital isolators use wide-body SOIC?

Creepage and clearance scale with body width. The ISO7721 provides 4 mm in the narrow D-8 package and 8 mm in the wide DW-16, which lifts UL 1577 withstand voltage from 3000 VRMS to 5000 VRMS and working voltage from 450 VRMS to 1500 VRMS. Reinforced insulation certification depends on those distances.

Can I use one footprint for both narrow and wide SOIC?

No. The pad rows sit 5.40 mm apart for narrow body and 9.30 mm apart for wide body, a 3.90 mm difference. No compromise pattern makes reliable joints on both, and combined footprints fail solder fillet inspection on whichever part they were not drawn for.

What to do next

Open the drawing for the exact orderable part number and record the lead span, body width and maximum height. If the design crosses an isolation barrier, take the creepage figure from the insulation table rather than the package name, then verify that your land pattern preserves it, using the high-voltage layout option when the vendor publishes one. If the design only dissipates heat, compare RθJA across the vendor’s package options for that device and decide whether 16 °C/W is worth 50 mm² of board. Put the package suffix in the schematic symbol, not only in the bill of materials, so the next person to open the project cannot get it wrong.

Sources

• Texas Instruments, ISO7720/ISO7721 data sheet SLLSEP3G, November 2016, revised May 2024 (thermal, insulation, package drawings D0008B, DW0016B, DWV0008A, tape-and-reel data) – https://www.ti.com/lit/ds/symlink/iso7721.pdf
• Texas Instruments, SN54HC595 / SN74HC595 data sheet SCLS041H, December 1982, revised November 2009 (package thermal impedance per JESD 51-7) – https://www.ti.com/lit/ds/symlink/sn74hc595.pdf
• Texas Instruments, DW0016A package drawing 4220721/A, 07/2016 – https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/14/DW16drawing.pdf
• Texas Instruments, D0008A package drawing 4214825/C, 02/2019 – https://www.ti.com/lit/pdf/msoi002k
• NXP / Freescale, AN2409 Rev 3.0, 10/2014, Small Outline Integrated Circuit (SOIC) Package (body size table, MSL, stencil and pad guidance) – https://www.nxp.com/docs/en/application-note/AN2409.pdf
• Skyworks Solutions, AN583, Safety Considerations and Layout Recommendations for Digital Isolators (measured creepage of JEDEC wide-body SOIC) – https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN583.pdf