The SO-14 package most engineers mean is JEDEC MS-012 variation AB: fourteen gull-wing leads on 1.27 mm pitch, a body 8.55 mm to 8.75 mm long and 3.80 mm to 4.00 mm wide, a 5.80 mm to 6.20 mm lead span and 1.75 mm maximum height. Strictly, the package has no pinout. Pin 1 sits at the marked corner; what each pin does is device-specific, and two of the most common 14-pin parts put the supply in different places.

Key takeaways

• SO-14 in the JEDEC sense is MS-012 variation AB, the same outline Texas Instruments draws as D0014A and Nexperia registers as SOT108-1.
• Texas Instruments uses SO (14) for a different package: 10.20 mm × 5.30 mm, not 8.65 mm × 3.90 mm. Read the package drawing, not the two-letter name.
• Pin numbering is fixed by the package; pin function is not. On the SN74HC00 the supply pins are 14 and 7; on the LM324 they are 4 and 11.
• Published land patterns for this one outline span 6.35 mm to 7.40 mm across the rows, a difference of over a millimetre.
• At 1.27 mm pitch the solder-mask web is about 0.53 mm and the stencil area ratio is around 1.7. Neither is a constraint here.
• A 14-lead TSSOP occupies 38% less board area for the same function, at 1.20 mm height instead of 1.75 mm.

[IMAGE 1: dimensioned SO-14 outline, top and side views, with D, E, E1, A, A1, b, c, L and e called out | alt: “SO-14 package dimensions diagram showing 1.27 mm lead pitch and 3.80 to 4.00 mm body width”]

SO-14 dimensions per JEDEC MS-012 variation AB

An SO-14 is a 14-lead plastic surface-mount package with seven gull-wing leads per side on 1.27 mm pitch, a body 3.80 mm to 4.00 mm wide and no more than 1.75 mm tall. Texas Instruments publishes the outline as D0014A and cites JEDEC registration MS-012, variation AB.

Symbol	Dimension	Min (mm)	Max (mm)	Source note
D	Body length	8.55	8.75	Excludes mould flash up to 0.15 mm per side
E1	Body width	3.80	4.00	Excludes interlead flash up to 0.43 mm per side
E	Lead span, toe to toe	5.80	6.20	Typical dimension on the drawing
A	Overall height	—	1.75	Maximum only
A1	Standoff	0.10	0.25	Diodes SO-14 rev 2024-04-08
A2	Body thickness	1.25	1.55	Diodes SO-14 rev 2024-04-08
b	Lead width	0.31	0.51	Excludes dambar protrusion
c	Lead thickness	0.13	0.25	TI D0014A
L	Foot length	0.40	1.27	Gauge plane 0.25 mm above seating plane
e	Lead pitch	1.27	1.27	12 spaces, 7.62 mm across the row

Table 1. Outline limits from the TI D0014A drawing 4220718/A, 09/2016, referencing JEDEC MS-012 variation AB, cross-checked against the Diodes SO-14 package file rev 2024-04-08 and Nexperia SOT108-1 dated 7 November 2023. Lead angle 0° to 8°, coplanarity 0.10 mm.

Vendors agree here in a way they rarely do. Diodes, Nexperia and TI all publish 8.55 mm to 8.75 mm body length, 3.80 mm to 4.00 mm width and a 1.75 mm height cap. The only wobble is in the nominal figures quoted in device tables: TI’s SN74HC00 datasheet lists the D package as 8.70 mm × 3.90 mm while its LM324-N datasheet lists 8.65 mm × 3.91 mm, for the same drawing. Use the drawing, not the summary line.

Two different packages answer to “SO-14”

This matters more than the tolerances. In TI’s own device tables, SOIC (14) is 8.70 mm × 3.90 mm and SO (14) is 10.20 mm × 5.30 mm. They are different parts: SN74HC00D is the narrow JEDEC body, SN74HC00NS is the wider EIAJ-derived one. Nexperia, meanwhile, names the narrow 3.9 mm body SO14 outright, in outline SOT108-1.

So the string SO-14 identifies a lead count and nothing else. Confirm the body width and the lead span before you place a footprint.

14-lead package	TI code	Body L × W (mm)	Pitch (mm)	Lead span (mm)	Max height (mm)	θJA (°C/W)
SOIC, MS-012 AB	D	8.75 × 4.00	1.27	5.8 to 6.2	1.75	133.6
SO, wider body	NS	10.20 × 5.30 nom	1.27	not in this document	not in this document	91.0
SSOP, MO-150	DB	6.50 × 5.60	0.65	7.4 to 8.2	2.00	108.3
TSSOP, MO-153	PW	5.10 × 4.50	0.65	6.2 to 6.6	1.20	151.7
PDIP	N	19.30 × 6.40 nom	2.54	7.62 row	not in this document	57.5

Table 2. Outline figures from the TI D0014A, DB0014A and PW0014A drawings; nominal body sizes and all θJA values from the SN74HC00 datasheet SCLS181H, revised August 2021, measured on 14-pin parts. Two counterintuitive results: the wider NS body runs 32% cooler than the D, and the TSSOP runs hottest of the surface-mount options.

Board area follows the same shape. Taking maximum body length times maximum lead span from each drawing, the SOIC-14 needs 54.2 mm², the SSOP-14 needs 53.3 mm² despite being 2.25 mm shorter, and the TSSOP-14 needs 33.7 mm². A 14-pin PDIP needs 123.5 mm², which is the 2.3-times saving that put this package on boards in the first place.

SO-14 pin numbering, and why the package has no pinout

Pin numbering is a package property and it is fixed. Pin 1 is at the corner carrying the index mark, a dimple, a bevel or a moulded notch depending on vendor. Numbering runs down that side to pin 7, crosses to the opposite corner and runs back up to pin 14. Pin 14 therefore sits directly across from pin 1, and pins 1, 7, 8 and 14 are the four corners. All of that is true of every SO-14 ever made.

Pin function is a device property and it is not fixed. Two of the most common parts in this package disagree about where the supply goes.

Pin	SN74HC00 (quad NAND)	LM324-N (quad op amp)
1	1A, input	OUTPUT1
2	1B, input	INPUT1−
3	1Y, output	INPUT1+
4	2A, input	V+, positive supply
5	2B, input	INPUT2+
6	2Y, output	INPUT2−
7	GND	OUTPUT2
8	3Y, output	OUTPUT3
9	3A, input	INPUT3−
10	3B, input	INPUT3+
11	4Y, output	GND or negative supply
12	4A, input	INPUT4+
13	4B, input	INPUT4−
14	VCC	OUTPUT4

Table 3. SN74HC00 pin functions from TI datasheet SCLS181H, revised August 2021. LM324-N pin functions from TI datasheet SNOSC16D, revised January 2015. Both are top views of the 14-pin package.

The op amp puts its supply pins in the middle of each row on purpose. TI’s LM324-N datasheet states that the pinout was arranged so inverting inputs sit next to outputs and the four outputs land on the package corners, pins 1, 7, 8 and 14. That is a layout convenience, and it is also why a decoupling capacitor placed at the corner of an LM324 footprint does nothing useful. Put it across pins 4 and 11.

Four published SO-14 land patterns, compared

Land pattern source	Pad width X (mm)	Pad length Y (mm)	Outer span Z (mm)	Inner span G (mm)	Toe beyond E max (mm)
TI D0014A, 4220718/A 09/2016	0.60	1.55	6.95	3.85	0.375
Diodes SO-14, rev 2024-04-08	0.60	1.50	6.90	3.90	0.35
Nexperia SOT108-1, 7 Nov 2023	not resolved	1.75	7.40	3.90	0.60
Analog Devices S14, 05-08-1610 rev G	0.762	1.143	6.35	4.064	0.075
IPC-7351B Level B, calculated	0.615	2.184	6.924	2.555	0.362

Table 4. Toe projection measured against the 6.20 mm maximum lead span. The ADI outer span is derived from the drawing’s 0.160 in inner span plus two 0.045 in pads, not dimensioned directly. The Nexperia pad width could not be resolved from the PDF text layer, which carries two similar width sets for solder land and solder resist; read it off Figure 2 before use.

[IMAGE 2: the four published land patterns drawn to scale on one grid with the package body outline overlaid | alt: “SO-14 land pattern comparison showing TI, Diodes, Nexperia and IPC-7351B pad geometry”]

TI and Diodes are within 0.05 mm of each other and both land within 0.03 mm of the IPC-7351B Level B outer span of 6.924 mm. That is unusual agreement, and it makes either a safe default. The outliers are worth understanding.

Nexperia’s 7.40 mm span projects 0.60 mm past a worst-case lead tip, more generous than an IPC Level A calculation returns. It inspects beautifully and costs 0.5 mm of routing channel. The Analog Devices S14 pattern goes the other way at 6.35 mm, leaving 0.075 mm of toe at maximum material condition, which is below Level C. Its pads are the widest of the four at 0.762 mm, so it trades toe fillet for side fillet.

Stencil, mask and packing at 1.27 mm pitch

This is the comfortable end of surface mount. With 0.60 mm pads on 1.27 mm pitch the gap between lands is 0.67 mm, and TI’s own drawing calls for 0.07 mm of solder-mask clearance all around, leaving a 0.53 mm mask web. No fabricator will argue about that.

Paste release has margin to spare. TI’s stencil example uses apertures equal to the land, 0.60 mm × 1.55 mm, on a 0.125 mm stencil, which returns an IPC-7525 area ratio of 1.73 against a floor of 0.66. Nexperia recommends 0.15 mm stencil thickness for its pattern, which still gives 1.49. Print 1:1 and spend the effort elsewhere.

Packing is worth checking against your feeder setup. Diodes ships SO-14 in tubes of 100 or on 16 mm tape at 2,500 per 13-inch reel. TI ships the SN74HC00DR on the same 16 mm tape at 2,500 per reel, with A0 6.5 mm, B0 9.0 mm and K0 2.1 mm; the LM324MX uses B0 9.35 mm and K0 2.3 mm for the same package outline, because the pocket accommodates the actual moulded body, not the drawing limit.

Modern SO-14 parts are rated MSL 1 with a 260 °C peak reflow, and Diodes specifies 260 °C for 30 s per J-STD-020. Older documentation can be much more conservative: the LM324-N datasheet still lists 215 °C vapour phase for 60 s and 220 °C infrared for 15 s for the small-outline package. If you are working from a legacy datasheet, check the current package qualification rather than the printed limit.

Four SO-14 mistakes that cause rework

• Ordering by the string SO-14 without checking body width. The NS and D packages differ by 1.4 mm in width and 1.5 mm in length.
• Reusing a 14-pin symbol across a logic part and an op amp. Supply pins move from 14 and 7 to 4 and 11.
• Placing the decoupling capacitor at the corner of an op amp footprint, where neither supply pin is.
• Copying the tightest published land pattern onto a board that will be graded on toe fillet. Two of the four here differ by more than a millimetre in span.

SO-14 package FAQ

What are the SO-14 package dimensions?

Body length 8.55 mm to 8.75 mm, body width 3.80 mm to 4.00 mm, lead span 5.80 mm to 6.20 mm, height 1.75 mm maximum, lead pitch 1.27 mm, foot length 0.40 mm to 1.27 mm, lead width 0.31 mm to 0.51 mm. Those are the JEDEC MS-012 variation AB limits as drawn by TI in D0014A.

What is the SO-14 pinout?

The package fixes pin numbering, not pin function. Pin 1 is at the index mark, numbering runs down that side to pin 7 and back up the far side to pin 14. Function depends on the device: an SN74HC00 has VCC on 14 and GND on 7, while an LM324 has V+ on 4 and GND on 11.

Is SO-14 the same as SOIC-14?

Usually but not always. Nexperia calls the 8.65 mm × 3.9 mm JEDEC body SO14. Texas Instruments reserves SO (14) for a wider 10.20 mm × 5.30 mm package and calls the narrow one SOIC (14). Check the body width on the drawing before assuming the two names describe one footprint.

How do I find pin 1 on an SO-14?

Look for the index feature moulded or marked at one corner of the top surface: a dimple, a bevelled edge, a notch in the body end, or a printed dot. Analog Devices notes on its S14 drawing that pin 1 may be either a bevel edge or a dimple. Orient the part top-side up before counting.

SO-14 or TSSOP-14 for a new design?

TSSOP-14 if area or height drives the decision: 33.7 mm² against 54.2 mm², and 1.20 mm against 1.75 mm. SO-14 if hand assembly, rework or probing matters, or if the part is only sold in it. On the SN74HC00, TSSOP also runs hotter, 151.7 °C/W against 133.6 °C/W.

What to do next

Open the package drawing for your exact part number and confirm three things: the body width, the lead span and the JEDEC variation. If the drawing says MS-012 AB you can use the TI or Diodes land pattern with confidence, because both sit within 0.03 mm of the IPC-7351B Level B result. Then draw the pinout from the device datasheet rather than from a package library symbol, and place the decoupling capacitor across the two pins that actually carry the supply for that device.

External references consulted for this article:

Texas Instruments SN74HC00 datasheet SCLS181H, including the D0014A package drawing and land pattern: https://www.ti.com/lit/ds/symlink/sn74hc00.pdf

Texas Instruments LM124-N/LM324-N datasheet SNOSC16D: https://www.ti.com/lit/ds/symlink/lm324-n.pdf

Diodes Incorporated SO-14 package information, rev 2024-04-08: https://www.diodes.com/assets/Package-Files/SO-14.pdf

Nexperia SOT108-1 package information, 7 November 2023: https://assets.nexperia.com/documents/package-information/SOT108-1.pdf

Analog Devices S14 package drawing, LTC DWG 05-08-1610 rev G: https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-soic/05081610_g_s14.pdf

Suggested internal links:

[INTERNAL LINK: JEDEC MS-012 and the SOIC family -> JEDEC MS and MO registration guide]

[INTERNAL LINK: IPC-7351B density levels -> land pattern density level explainer]

[INTERNAL LINK: TSSOP-14 package dimensions -> TSSOP package reference page]

[INTERNAL LINK: solder paste stencil area ratio -> stencil design guide]

[INTERNAL LINK: reading a package drawing -> how to read JEDEC package outlines]