Post: QSOP-20 Package: Dimensions and Land Pattern

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QSOP-20 Package: Dimensions and Land Pattern

The QSOP-20 package is a 20-lead gull-wing plastic package on 0.635 mm (25 mil) pitch, 3.81 mm to 3.99 mm wide, 8.56 mm to 8.76 mm long, with a 5.79 mm to 6.20 mm lead span. JEDEC registers the outline as MO-137-AD. The body limits are settled across vendors. The land pattern is not: three published footprints for this same outline differ by 0.66 mm in overall span, and copying the wrong one costs you either heel fillet or board area.

Key takeaways

QSOP-20 is JEDEC MO-137-AD: 0.635 mm pitch, 0.150 in nominal body width, 1.75 mm maximum seated height.
Body and lead limits agree across Analog Devices, Diodes, Renesas and Texas Instruments. Their recommended land patterns do not.
Published overall land spans run from 6.40 mm (Diodes) to 7.06 mm (Renesas). An IPC-7351B Level B calculation lands at 6.92 mm.
JEDEC titles this family SSOP, not QSOP. TI ships the identical outline as package code DBQ and labels current drawings SSOP.
Board area is 24% larger than a TSSOP-20 and 2.5 times smaller than a 20-lead wide-body SOIC.
At 0.635 mm pitch the binding constraint is the solder-mask web between lands, not the copper itself.

[IMAGE 1: dimensioned QSOP-20 outline, top and side views, with D, E, E1, A, A1, b, c, L and e called out | alt: “QSOP-20 package dimensions diagram showing 0.635 mm lead pitch and 3.81 to 3.99 mm body width”]

QSOP-20 dimensions per JEDEC MO-137-AD

A QSOP-20 (quarter size outline package, 20 leads) is a plastic surface-mount package carrying ten gull-wing leads per side on 0.635 mm pitch, with a 3.81 mm to 3.99 mm body width and a 1.75 mm maximum height. Analog Devices publishes it as package option RQ-20 and marks the drawing compliant to JEDEC MO-137-AD.

Symbol	Dimension	Min (mm)	Max (mm)	Min (in)	Max (in)
D	Body length	8.56	8.76	0.337	0.345
E	Lead span, toe to toe	5.79	6.20	0.228	0.244
E1	Body width	3.81	4.01	0.150	0.158
A	Overall height	1.35	1.75	0.053	0.069
A1	Standoff	0.10	0.25	0.004	0.010
A2	Body thickness	1.24	1.63	0.049	0.064
b	Lead width	0.20	0.30	0.008	0.012
c	Lead thickness	0.15	0.25	0.006	0.010
L	Foot length	0.41	1.27	0.016	0.050
e	Lead pitch	0.635 BSC	0.635 BSC	0.025 BSC	0.025 BSC

Table 1. QSOP-20 outline limits, Analog Devices RQ-20 drawing rev 04-09-2021-B, compliant to JEDEC MO-137-AD. Coplanarity 0.10 mm max, lead angle 0° to 8°.

Two vendor drawings for the same outline disagree on the height band. Analog Devices allows 1.35 mm to 1.75 mm overall; the Diodes QSOP-20 package file (rev 2017-04-04) narrows it to 1.55 mm to 1.73 mm and quotes D as 8.56 mm to 8.74 mm. Neither is wrong; MO-137 is a family registration and vendors qualify their own subset. Use the drawing in the datasheet of the part you are actually buying when you set courtyard height or connector clearance.

Why your QSOP-20 may be labelled SSOP

JEDEC’s own registration is titled Plastic Shrink Small Outline Package (SSOP) Family, R-PDSO/SSOP/SOIC, with 0.025 inch pitch and 0.150 inch body width. The current issue is MO-137E, published March 2010 under committee JC-11.11. QSOP is a vendor name layered on top of an SSOP registration, which is why the same physical part shows up under two package names in parametric searches.

Leads	JEDEC variation	Body length D (mm)	ADI package code
16	MO-137-AB	4.80 to 5.00	RQ-16
20	MO-137-AD	8.56 to 8.76	RQ-20
24	MO-137-AE	8.56 to 8.76	RQ-24
28	MO-137-AF	9.80 to 10.01	RQ-28

Table 2. MO-137 variation letters, read off the Analog Devices RQ-16, RQ-20, RQ-24 and RQ-28 package drawings. Note that the 20-lead and 24-lead variations share the same body length; only the pitch fill differs.

Texas Instruments uses package code DBQ for this outline. Its 2011 packaging guide lists DBQ under QSOP with 8.56 mm to 8.74 mm body length and 5.8 mm to 6.2 mm span, while the current DBQ mechanical drawings are titled Shrink Small-Outline Package. Same copper, two names on two documents from one vendor.

The trap is the other direction. A part sold as SSOP-20 from TI (package code DB) is 5.00 mm to 5.60 mm wide on 0.65 mm pitch with a 7.40 mm to 8.20 mm span. It will not sit on a QSOP-20 footprint. Confirm the pitch and the span, never the marketing name.

Three published QSOP-20 land patterns, compared

Every source below describes a footprint for the same MO-137-AD outline. They are not interchangeable.

Land pattern source	Pad width X (mm)	Pad length Y (mm)	Outer span Z (mm)	Inner span G (mm)	Toe beyond E max (mm)
Diodes QSOP-20 package file, rev 2017-04-04	0.350	1.450	6.400	3.500	0.10
Renesas PCG20D1, PSC-4973-01 rev 01	0.330	1.245	7.060	4.570	0.43
KiCad Package_SO, QSOP-20_3.9×8.7mm_P0.635mm	0.410	1.600	6.909	3.709	0.354
IPC-7351B Level B, calculated below	0.433	2.189	6.924	2.545	0.362

Table 3. QSOP-20 land pattern comparison. Toe projection is measured against the 6.20 mm maximum lead span, which is the condition an inspector sees at worst case.

[IMAGE 2: the three land patterns drawn to scale on one grid, package body outline overlaid | alt: “QSOP-20 land pattern comparison showing Diodes, Renesas and IPC-7351B nominal pad geometry”]

The spread is not cosmetic. The Diodes pattern projects only 0.10 mm past a worst-case lead tip, which is close to IPC Density Level C territory and leaves almost nothing for an inspector to call a toe fillet. The Renesas pattern projects 0.43 mm and pulls the inner edge 0.29 mm clear of the maximum body outline, so no copper hides under the package. The Diodes and KiCad patterns tuck the heel 0.25 mm and 0.14 mm under the body edge respectively, which buys heel fillet at the cost of optical access.

Pick by process, not by preference. If the board goes through automated optical inspection with a bridging spec, the Renesas geometry inspects better. If you are fighting for routing channels under the part, the Diodes geometry gives back 0.66 mm of span. If you hand-solder or rework, take the longest pads you can fit.

Check the IPC-7351B math before you copy a footprint

The IPC-7351B gull-wing equations use the component limits plus a solder-joint goal for toe, heel and side. Level B (nominal) goals for a SOIC-family gull-wing lead are JT 0.35 mm, JH 0.35 mm and JS 0.03 mm, with 0.10 mm allowed for fabrication and 0.10 mm for placement. Feeding MO-137-AD limits in:

Z max = L min + 2 × JT + √(CL² + F² + P²) = 5.79 + 0.70 + 0.434 = 6.92 mm

G min = S max − 2 × JH − √(CS² + F² + P²) = 5.38 − 0.70 − 2.135 = 2.55 mm

X max = W min + 2 × JS + √(CW² + F² + P²) = 0.20 + 0.06 + 0.173 = 0.43 mm

The Z figure is useful: 6.92 mm sits within 0.02 mm of the KiCad footprint’s 6.91 mm, which is a good sign that the library part was generated to Level B. The G figure is the trap. Foot length L in MO-137-AD is specified from 0.41 mm to 1.27 mm, an 0.86 mm range, so the heel span S swings from 3.25 mm to 5.38 mm and the root-sum-square term alone eats 2.13 mm. The equation answers honestly and hands you a 2.19 mm pad reaching 0.72 mm under the package body.

That is why no vendor publishes the raw Level B result. If your EDA tool’s IPC wizard produces pads that look absurdly long for a QSOP-20, this is the mechanism, not a bug. Two ways out: constrain the foot length input to the vendor’s own tighter tolerance where the datasheet gives one, or start from a vendor pattern and audit it against the toe and side goals only.

Stencil, mask and assembly at 0.635 mm pitch

The copper is the easy part. The gap between adjacent lands is 0.225 mm on the KiCad pattern, 0.285 mm on the Diodes pattern and 0.305 mm on the Renesas pattern. Once the fab applies its solder-mask expansion, the remaining mask web on the narrowest of those is thin enough that many shops will simply gang the openings. Ask your fabricator for its minimum mask dam before you commit to the widest pads.

Paste release is comfortable at this pitch, which is worth knowing before anyone proposes shrinking the apertures. IPC-7525 wants an area ratio above 0.66. For a 0.41 mm by 1.60 mm aperture in a 0.127 mm (5 mil) stencil the area ratio is 1.29; the narrower Renesas aperture still returns 1.03. There is no release problem to solve here, so print 1:1 with the land and spend your process margin on registration instead.

One packaging detail catches feeder setups. The Diodes QSOP-20 ships on 16 mm tape at 2,500 parts per 13-inch reel, while the otherwise identical QSOP-16 uses 12 mm tape. Swapping a 16-lead part for a 20-lead part in the same product family is a feeder change, not a reel change.

QSOP-20 vs SSOP-20, TSSOP-20 and SOIC-20

20-lead package	TI code	Body L × W (mm)	Pitch (mm)	Lead span (mm)	Max height (mm)	Board area (mm²)
QSOP	DBQ	8.74 × 3.99	0.635	5.8 to 6.2	1.75	54.2
SSOP	DB	7.5 × 5.6	0.65	7.4 to 8.2	2.00	61.5
TSSOP	PW	6.6 × 4.5	0.65	6.2 to 6.6	1.20	43.6
SOIC wide	DW	12.95 × 7.59	1.27	10.15 to 10.65	2.65	137.9

Table 4. Dimensions from the Texas Instruments packaging guide (document sszb138). Board area is computed here as maximum body length times maximum lead span, so it is a placement envelope rather than a courtyard.

The decision path is short. Need the lowest profile, for example under a shield can or a stacked board: TSSOP-20 at 1.20 mm. Need the smallest placement envelope: TSSOP-20 again, 20% less area. Need 1.27 mm pitch because the assembly line is set up for it or the part must be hand-reworked in the field: SOIC-20 wide, at 2.5 times the area. QSOP-20 wins when the design is pin-limited on a narrow body and 1.75 mm of height is acceptable, which is why it is common in digital isolators and bus switches.

Thermal headroom and isolation clearance

Junction-to-ambient resistance for this package is around 76 °C/W. Analog Devices specifies exactly that for the ADuM7640 family in the 20-lead QSOP, measured with a thermocouple at the centre of the package underside. Run the arithmetic before you assume the package is fine: at 250 mW dissipation the junction sits 19 °C above ambient, and holding a 40 °C rise caps you at 526 mW.

Isolation parts add a second constraint that has nothing to do with the land pattern. The ADuM7640 datasheet specifies a 4 mm minimum external air gap and 4 mm creepage from input terminals to output terminals, measured per IEC 62368-1 for pollution degree 2 at altitudes up to 2,000 m. The package body is only 8.66 mm long, so the barrier region is most of the part. No copper, no silkscreen fill and no via may cross it, and the datasheet explicitly warns that pad layout can compromise the rated clearance.

[IMAGE 3: QSOP-20 footprint with the isolation barrier keep-out shaded across the package centre | alt: “QSOP-20 land pattern with 4 mm creepage keep-out marked for a digital isolator”]

Five mistakes that send QSOP-20 boards back

Assuming SSOP-20 and QSOP-20 share a footprint. Different pitch, different span, guaranteed rework.
Generating a Level B footprint from a wizard, accepting the 2.19 mm pads, and losing the routing channel under the part.
Copying the shortest published pattern into a design that will be AOI-inspected against a toe-fillet criterion.
Routing a ground pour under an isolator body and breaking the 4 mm creepage the safety file depends on.
Reusing the 12 mm feeder from a QSOP-16 build. The 20-lead part is on 16 mm tape.

QSOP-20 FAQ

What is a QSOP-20 package?

A QSOP-20 is a 20-lead plastic surface-mount package with gull-wing leads on 0.635 mm pitch, a 3.81 mm to 3.99 mm body width and a 1.75 mm maximum height. JEDEC registers it as MO-137-AD. It fits 20 leads into roughly the body length of an 8-lead SOIC by shrinking the pitch to half of 1.27 mm.

Is QSOP the same as SSOP?

Not as a footprint. JEDEC files the QSOP outline inside its SSOP family registration, so the names overlap on paper. In practice a part sold as SSOP-20 is usually 0.65 mm pitch on a 5.3 mm body, while QSOP-20 is 0.635 mm pitch on a 3.9 mm body. Check pitch and lead span, not the name.

What is the pitch of a QSOP-20?

0.635 mm, specified as a basic dimension. That is exactly 25 mil, or half the 1.27 mm pitch of a standard SOIC. Every MO-137 variation, from 16 leads to 28 leads, uses the same 0.635 mm pitch; only the body length changes with lead count.

Can you hand solder a QSOP-20?

Yes. At 0.635 mm pitch, drag soldering with flux and a chisel tip works reliably, and the leads stay visible for inspection. Choose the longest published land pattern you can fit, since extra pad length outside the toe gives the iron somewhere to work. Adapter boards to DIP-20 exist for bench prototyping.

What JEDEC standard covers the QSOP-20 package?

JEDEC MO-137, currently at issue E (March 2010), titled Plastic Shrink Small Outline Package (SSOP) Family with 0.025 inch pitch and 0.150 inch body width. The 20-lead variation is MO-137-AD. The 16, 24 and 28-lead variations are AB, AE and AF respectively.

QSOP-20 or TSSOP-20 for a new design?

TSSOP-20 if height or area is the constraint: 1.20 mm maximum versus 1.75 mm, and about 20% less placement area. QSOP-20 if the function you need only exists in that package, which is often the case for digital isolators, or if your line already qualifies 0.635 mm pitch and the extra 0.55 mm of height is free.

What to do next

Pull the package drawing from the datasheet of the exact part number you are buying, not from a generic QSOP-20 page, and confirm the height band and the foot length against Table 1. Then pick the land pattern by process: Renesas geometry if the board is AOI-inspected or the part is an isolator with a creepage requirement, Diodes geometry if you need the routing channel back, KiCad or IPC-7351B Level B as the default for general production. If your CM has an opinion on mask dams at 0.225 mm, that opinion outranks all three.

External references consulted for this article:

Analog Devices RQ-20 package drawing: https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/qsoprq/rq_20.pdf

Diodes Incorporated QSOP-20 package information: https://www.diodes.com/assets/Package-Files/QSOP-20.pdf

Renesas PCG20D1 20-QSOP package outline and recommended land pattern: https://www.renesas.com/en/document/psc/package-outline-drawing-package-code-pcg20d1-20-qsop-865-x-381-x-147-mm-body-0635mm-pitch

JEDEC MO-137E registration record: https://www.jedec.org/standards-documents/docs/mo-137e

Analog Devices ADuM7640 to ADuM7643 datasheet, rev A: https://www.analog.com/media/en/technical-documentation/data-sheets/ADuM7640_7641_7642_7643.pdf

KiCad Package_SO QSOP-20 footprint source: https://github.com/KiCad/kicad-footprints/blob/master/Package_SO.pretty/QSOP-20_3.9×8.7mm_P0.635mm.kicad_mod