The CLCC package is a square ceramic surface-mount package with metallized castellations down its four edges instead of leads, usually on 1.27 mm or 1.02 mm centers. It buys hermeticity, a short electrical path and an optional glass window. It costs you compliance: with no lead to flex, the solder joints absorb the full expansion mismatch between alumina and your board. That single fact drives every design decision below.
Key takeaways
- Analog Devices’ 20-terminal LCC drawing E-20-1 gives a body of 8.69 mm to 9.09 mm square on a 1.27 mm terminal pitch.
- The acronym is unreliable. TI, Wikipedia and the patent literature assign CLCC, LCC and LCCC to different things, and two of them contradict each other outright.
- Alumina runs about 6–7 ppm/°C against 14–17 ppm/°C for standard FR-4. Over a −55 to +125 °C swing, a 9.09 mm body sees roughly 8.6 µm of corner shear.
- Solder joint standoff height is the dominant reliability variable, not pad geometry.
- The package survives today mainly where the window matters: image sensors and optical devices, plus military and aerospace hermetic parts.
What is a CLCC package?
The CLCC package is a ceramic leadless chip carrier: a square or rectangular surface-mount package with no protruding leads, using metallized castellations recessed into the four side walls and wrapping onto the bottom face. Pad counts run from 8 to about 100, at 1.27 mm or 1.02 mm pitch. The ceramic body allows a hermetic seal and, with a glass lid, an optical window.
[IMAGE 1: bottom-view macro of a 20-terminal CLCC showing the plated castellations wrapping from side wall to underside, with the 45° corner chamfer lit | alt: “CLCC package bottom view showing castellated terminals and the pin 1 corner chamfer”]
The acronym is not reliable. Check the drawing.
This is the first thing to settle, because two vendors can hand you drawings of physically different packages under the same four letters.
| Source | What it calls CLCC | What it calls LCCC |
| Texas Instruments package pages | Uses LCC and LCCC for the ceramic leadless package; JLCC for the J-leaded ceramic version | Ceramic leadless |
| Evergreen Semiconductor Materials | Ceramic leadless chip carrier, used interchangeably with LCC | not used |
| Wikipedia, Chip carrier | Ceramic leadless chip carrier | Leaded ceramic chip carrier |
| Patent literature, e.g. US 2005/0056769 A1 | Ceramic leaded chip carrier | not used |
| Distributor listings, e.g. OmniVision OV07960-C48N | 48-pin CLCC image sensor, 14.22 mm square | not used |
Table 1. The same four letters across five sources. Wikipedia and TI assign LCCC to opposite meanings.
Wikipedia and Texas Instruments assign LCCC to opposite things. TI’s own package page is headed Leaded Chip Carrier while its body text describes a ceramic leadless package. And image-sensor patents use CLCC to mean leaded.
The practical rule: never order or lay out from the acronym. Pull the vendor’s dimensioned drawing and look for castellations versus J-leads. If your CAD library calls a footprint CLCC, verify what generated it.
CLCC dimensions: the 20-terminal case
Analog Devices publishes drawing E-20-1 for its 20-terminal ceramic leadless chip carrier, revision 12-12-2023-C, package identifier PKG-000045. Controlling dimensions on that drawing are inches; the millimeter figures are rounded equivalents.
| Feature | Min | Max |
| Body, square | 8.69 mm | 9.09 mm |
| Body, square, maximum envelope | — | 9.09 mm |
| Terminal pitch | 1.27 mm BSC | 1.27 mm BSC |
| Castellation width | 0.56 mm | 0.71 mm |
| Corner chamfer | 0.38 mm min, 45° typical | — |
| Overall height | 1.63 mm | 2.54 mm |
Table 2. 20-terminal CLCC outline, per Analog Devices drawing E-20-1 rev 12-12-2023-C.
Two features on that drawing are easy to miss. The 45° corner chamfer is the pin 1 index, and it is the only orientation feature on a package with four identical edges. And the castellation is a plated half-hole, not a flat pad, so solder wets up the side wall as well as across the bottom.
Why leadless ceramic cracks solder joints
A gull-wing or J-lead flexes and absorbs differential expansion. A castellation cannot. Everything the mismatch produces ends up as strain in the solder.
Alumina packages run roughly 6–7 ppm/°C, against 14–17 ppm/°C in-plane for standard FR-4, per CTE guidance published by ceramic PCB fabricators. Silicon itself is near 2.6 ppm/°C.
Work the corner. Take the 9.09 mm maximum body from E-20-1 and a −55 °C to +125 °C excursion, 180 K. Using 17 ppm/°C for the board and 6.5 ppm/°C for the package, the corner terminal moves relative to its pad by 10.5 ppm/°C × 180 K × 4.55 mm, or about 8.6 µm. At the low end of the FR-4 range, 14 ppm/°C, it is 6.1 µm. On a ceramic board matched at 6.5 ppm/°C it is zero.
An 8.6 µm excursion across a solder joint 50 µm to 100 µm tall is a large cyclic shear strain, and it repeats every thermal cycle. A 1988 patent on LCCC mounting describes the mechanism in two regimes: below room temperature the mismatch is largely taken up by bimetallic-strip bending of the board and carrier, while above room temperature it is taken up by shear in the solder.
[IMAGE 2: cross-section diagram of a castellated terminal soldered to a land, with arrows showing corner displacement between ceramic body and FR-4 over temperature | alt: “CLCC package solder joint shear from CTE mismatch between alumina and FR-4”]
Fixes that actually work
Match the substrate. The patent literature describes 84-terminal LCCC parts surface-mounted to alumina printed wiring boards specifically because the CTEs match, at the cost of a more expensive and heavier board. One ceramic fabricator reports its LCCC joints on ceramic surviving 2,000 thermal shock cycles from −55 °C to +125 °C without crack growth against 500 cycles for the same joints on FR-4.
Raise the standoff. A 2022 study in Microelectronics Reliability concludes that solder joint height is the dominant factor in LCCC thermal fatigue life, and evaluates Sn10Pb90 column mounting as the method that meets the widest range of environmental requirements. Taller joints spread the same displacement over more solder.
Use an adapter. A 2024 IEEE conference paper evaluates mounting LCCC devices to a small adapter board first, then attaching that assembly to the FR-4. Adapter and column approaches trade shock and vibration margin for thermal cycling life, so qualify against whichever your environment actually applies.
Constrain the body size. Corner displacement scales with half the diagonal, so a 9 mm part is manageable where a 25 mm part on the same board is not. If the part is large and the board is organic, the package is the wrong choice.
Where CLCC still ships
Optical devices are the surviving volume application. The ceramic cavity with a sealed glass lid is difficult to reproduce in plastic, which is why image sensors used the format for years. OmniVision’s OV07960-C48N is a 48-pin CLCC measuring 14.22 mm square, rated −20 °C to +70 °C; RS Components lists it as no longer stocked, which is representative of the category.
Hermetic and screened parts are the other. Ceramic construction supports a true seal, so the dry-pack and floor-life rules written for molded plastic do not drive handling. The relevant screen is a seal test.
Windowed devices, historically UV-erasable memory, used the same construction with a quartz lid. Those parts are gone from franchise distribution.
Footprint, assembly and inspection
Three rules cover most of it.
Design the land pattern for a wetted castellation, not a flat terminal. The joint climbs the side wall, and that fillet is what you inspect.
Keep the chamfer visible. Silkscreen the pin 1 corner explicitly. A square ceramic body with four identical edges gives an operator no other cue, and a 90° rotation error is not recoverable.
Inspect the side fillet optically. Unlike a BGA, a CLCC joint is visible from outside the package, which is one genuine advantage over the array packages that replaced it. Use it.
[IMAGE 3: a soldered CLCC on a board photographed at a low angle so the side-wall fillets on each castellation are visible for inspection | alt: “CLCC package side-wall solder fillets visible for optical inspection”]
Design mistakes that cause returns
- Trusting the acronym. Confirm castellations against J-leads on the vendor drawing before you commit a footprint.
- Putting a large CLCC on standard FR-4 and qualifying it only at room temperature.
- Reducing solder volume to tighten the joint, which shortens standoff and cuts thermal fatigue life.
- Treating the corner chamfer as cosmetic instead of the sole orientation index.
- Assuming the CLCC package footprint in a CAD library matches your part. Pitch is 1.27 mm on some families and 1.02 mm on others.
- Specifying a windowed or image-sensor CLCC for a new design without checking franchise availability first.
Frequently asked questions
What is a CLCC package?
A ceramic leadless chip carrier: a square surface-mount ceramic package with metallized castellations along its four side walls instead of leads. Pad counts run from 8 to about 100 at 1.27 mm or 1.02 mm pitch. The ceramic body supports a hermetic seal and, with a glass lid, an optical window for image sensors.
Does CLCC mean leaded or leadless?
Both, depending on who wrote the document. Most vendors read the C as ceramic and the L as leadless, but image-sensor patents use CLCC for ceramic leaded chip carrier, and Wikipedia and TI assign LCCC to opposite meanings. Take the geometry from the drawing, never from the acronym.
What is the difference between CLCC and PLCC?
Material and lead form. A PLCC is a molded plastic body with J-shaped leads that flex and absorb board expansion; a CLCC is ceramic with rigid castellations. The PLCC is cheaper and far more tolerant on FR-4. The CLCC gives hermeticity, a window option and a shorter electrical path.
What is the CLCC pad pitch?
Typically 1.27 mm (0.050 in) or 1.02 mm (0.040 in) on center. Analog Devices’ 20-terminal E-20-1 drawing specifies 1.27 mm BSC on an 8.69 mm to 9.09 mm square body. Confirm the pitch on the specific drawing, since both values appear across the family.
Why do CLCC solder joints crack?
Because the package has no compliant lead. Alumina expands at about 6–7 ppm/°C and FR-4 at 14–17 ppm/°C, so every thermal cycle forces the difference into the solder as shear. Fixes raise the standoff height, match the substrate, or interpose an adapter board.
What to do next
If the design needs a hermetic seal or an optical window and the body is under about 10 mm, the CLCC package is defensible on an organic board, provided you qualify it over the full temperature range rather than at room temperature and you protect the standoff height in the stencil design.
If the body is large or the environment cycles hard, either move the assembly to a CTE-matched ceramic substrate or interpose an adapter. And before any of that, pull the vendor drawing and confirm whether the part in your BOM actually has castellations. On this package, the acronym is the least reliable piece of information you have.
Primary sources
- Analog Devices 20-terminal ceramic leadless chip carrier drawing E-20-1 — https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lcce/e_20_1.pdf
- Texas Instruments leaded / leadless chip carrier package listing — https://www.ti.com/packaging/docs/searchtipackages.tsp?packageName=LCC
- JEDEC MS-004, leadless chip carrier on 0.050 in centers — https://www.jedec.org/standards-documents/docs/ms-004-b
- JEDEC Publication 95 MS index by device type — https://www.jedec.org/sites/default/files/MSIND_DT_0.pdf
- US Patent 4,855,872, leadless ceramic chip carrier printed wiring board adapter — https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/4855872
Proposed internal links
- [INTERNAL LINK: “PLCC package and J-lead footprints” → PLCC package guide]
- [INTERNAL LINK: “QFN land pattern design” → QFN footprint guide]
- [INTERNAL LINK: “CTE mismatch and solder joint fatigue” → thermal cycling reliability guide]
- [INTERNAL LINK: “hermetic packaging and seal testing” → package hermeticity explainer]
- [INTERNAL LINK: “TO-99 metal can op-amp outline” → TO-99 package reference page]
