A DIP-40 is 15.24 mm between lead rows on 2.54 mm pitch, and the hole pattern spans 48.26 mm end to end. It is the largest DIP most engineers ever place, and the one where board area, insertion force and silkscreen tolerance all start to matter. This page gives the verified numbers.

Key takeaways

• Pitch is 2.54 mm (0.100 in), row spacing 15.24 mm (0.600 in). Twenty leads per side.
• NXP specifies its DIP40 as 13.97 × 52.07 × 5.08 mm under package code SOT129-4, referenced to JEDEC as E-PDIP-T40.
• The hole pattern is 48.26 mm, fixed by 19 spaces × 2.54 mm and identical across every vendor.
• Body length varies: NXP publishes 52.07 mm, while RS lists the Microchip PIC16F877A-I/P at 52.45 mm.
• A 1000 mil (25.4 mm) row spacing variant exists in footprint libraries but is rare outside legacy CPUs.
• The package is alive because of 8-bit microcontrollers. The PIC16F877A-I/P is Active at $6.80 with 1,384 in stock.

What is a DIP-40 package?

A DIP-40 package is a 40-lead dual in-line package: a rectangular molded body with twenty through-hole leads down each long side on 2.54 mm pitch, rows 15.24 mm apart. It mounts through plated holes or into an IC socket. PDIP-40 denotes the plastic-bodied version; ceramic versions exist as CERDIP for high-reliability parts.

Forty pins was the practical ceiling for mainstream DIP. It is what an 8-bit microprocessor or a mid-range microcontroller needed: a full 8-bit data bus, 16 address lines, control signals, oscillator pins and power. The 6502, Z80 and 8051 all shipped in this body, and the PIC16F87XA family still does.

DigiKey lists the PIC16F877A-I/P as 40-DIP (0.600″, 15.24mm) with supplier device package 40-PDIP. That row spacing covers essentially all modern 40-pin parts.

[IMAGE 1: DIP-40 package outline drawing with body length, row spacing, pitch and lead dimensions | alt: “DIP-40 package dimensions diagram showing 2.54 mm pitch and 15.24 mm row spacing”]

DIP-40 dimensions

Manufacturer figures for the 600 mil 40-lead package. NXP publishes a package-level specification; Microchip parametric data covers a specific part.

Dimension	Value	Source
Lead pitch	2.54 mm (0.100 in)	NXP SOT129-4
Row spacing	15.24 mm (0.600 in)	DigiKey package field, PIC16F877A-I/P
Body width	13.97 mm	NXP SOT129-4
Body length	52.07 mm	NXP SOT129-4
Body height	5.08 mm	NXP SOT129-4
Body length (PIC16F877A-I/P)	52.45 mm	RS Components parametric
Body width (PIC16F877A-I/P)	14.22 mm	RS Components parametric
Body height (PIC16F877A-I/P)	4.06 mm	RS Components parametric
Hole pattern length	48.26 mm	Calculated: 19 × 2.54 mm

The hole pattern figure is the one that never moves. Nineteen spaces at 2.54 mm gives 48.26 mm from the pin 1 hole centre to the pin 20 hole centre, and that is true of every DIP-40 regardless of manufacturer or body variation.

Everything else varies. NXP gives 52.07 mm of body length and 13.97 mm of width; the Microchip part measures 52.45 mm and 14.22 mm. Height differs more, 5.08 mm against 4.06 mm, which is a 1 mm spread that matters if you are checking enclosure clearance or stacking a board above.

Draw the silkscreen to the longest body, not the drawing you happened to open

At this size the vendor spread has real consequences. A 0.38 mm difference in length and 0.25 mm in width sounds small until you place two DIP-40s end to end with minimum clearance between them.

Draw the outline to about 52.6 mm by 14.4 mm and you will clear both figures above with margin. Leaving the silkscreen slightly generous costs nothing; a part that overhangs its printed outline generates assembly queries every build.

Height is the one to check against mechanical. If your stackup assumed 4.06 mm because that is what the MCU datasheet said, a second-source part built to the NXP outline at 5.08 mm will not fit under the same standoff.

The 1000 mil variant, and when you will meet it

Footprint libraries carry a DIP-40 at 25.4 mm (1000 mil) row spacing alongside the standard 15.24 mm entry. It is not a mistake.

Some early microprocessors used the wider body to fit a larger die and lead frame. If you are working on vintage hardware or a replica board, check the row spacing before assuming 600 mil. Measuring across the lead tips settles it: a 600 mil part reads roughly 15 to 17 mm, a 1000 mil part over 25 mm.

For anything designed in the last three decades, assume 15.24 mm and verify from the distributor package field. The wide variant is a legacy case, not a live design choice.

DIP-40 pinout and pin 1 identification

Pin 1 sits at one end, marked by a notch, a molded dot, or a chamfered corner. Orient the package with the notch at the top and the leads pointing away from you. Pin 1 is the upper-left lead. Numbering runs down the left side to pin 20, across the end, and back up the right side from pin 21 to pin 40.

For a DIP-40 specifically:

• Left column, top to bottom: pins 1 through 20
• Right column, bottom to top: pins 21 through 40
• Pin 1 and pin 40 face each other across the body
• Pin 20 and pin 21 face each other at the opposite end

Unlike DIP-32, where byte-wide memory follows a common JEDEC pinout, there is no shared pin map at 40 pins. A PIC16F877A, an 8051 and a Z80 have nothing in common electrically beyond the package outline. Pin 1 on one is not pin 1 in function on another.

That has a practical consequence for anyone socketing. A DIP-40 socket accepts all of them mechanically and none of them interchangeably. Label the board, not just the schematic.

[IMAGE 2: Top-down DIP-40 pinout diagram with notch, pin 1 dot, and numbering 1 to 40 counterclockwise | alt: “DIP-40 pinout diagram showing pin 1 notch and counterclockwise pin numbering to pin 40”]

DIP-40 footprint: hole and pad sizing

Twenty holes per row on 2.54 mm pitch, rows at 15.24 mm. The hole pattern spans 19 × 2.54 mm = 48.26 mm end to end.

Size the hole from the maximum lead width in your specific datasheet. Plastic DIP lead width maxima at this size typically fall around 0.51 to 0.58 mm; the worked example below uses 0.58 mm as a conservative case. Confirm against the drawing for the part you are placing.

Applying the IPC-2222 density levels to a 0.58 mm maximum lead:

• Level A: minimum hole = max lead diameter + 0.25 mm → 0.58 + 0.25 = 0.83 mm
• Level B: + 0.20 mm → 0.78 mm
• Level C: + 0.15 mm → 0.73 mm

Then the pad. Pad diameter = minimum hole size + (2 × minimum annular ring) + minimum fabrication allowance, where the minimum annular ring is 0.05 mm and the fabrication allowance is 0.6 mm for Level A, 0.5 mm for Level B and 0.4 mm for Level C.

Level B worked through: 0.78 + (2 × 0.05) + 0.5 = 1.38 mm pad on a 0.78 mm hole.

Round up to a stocked 0.9 mm drill. A 1.6 mm pad on a 0.9 mm hole is a manufacturable Class 2 default, matching the geometry used on other 600 mil DIPs.

Two checks before committing:

• Aspect ratio. Keep board thickness to hole diameter under 10:1 for reliable plating. A 0.9 mm hole is good to 9 mm of board, so this never binds in practice.
• Annular ring class. IPC-6012 Class 3 requires a minimum 0.001969 in external-layer annular ring measured from the finished hole to the land edge. Class 2 permits 90-degree breakout provided the land-conductor junction is teardropped.

Board area, insertion force and the reasons to think twice

A DIP-40 occupies roughly 48 by 15 mm of hole grid before clearance, plus the body overhang at each end. That is about 7 square centimetres of board given over to one component. The TQFP-44 equivalent of a PIC16F877A fits in well under a quarter of that.

Forty leads also means real insertion force. The leads splay outward from the factory, and a fresh part will not drop into a socket without first rolling both rows inward against a flat surface. Push evenly from both ends; levering one end first bends the far-row leads.

Removal is worse. Use a proper 40-pin extractor rather than a screwdriver. Prying at one corner is the standard way to bend a row of pins beyond recovery, and at $6.80 a part that is an expensive habit.

Routing and decoupling under a 600-mil DIP-40

The 15.24 mm row spacing leaves a wide channel. With 1.6 mm pads on 15.24 mm centres, the clear gap between opposing pad edges is about 13.6 mm, running the full 48 mm length of the package.

That channel is the single most useful piece of real estate on a through-hole MCU board. Put the decoupling capacitors there, adjacent to the supply pins, and route the crystal traces short. On a two-layer board it is also where the bulk of your signal routing will go.

One layout note specific to 40-pin microcontrollers: the oscillator pins are usually near one end and the supply pins near the other. Keep the crystal loop tight and local rather than running it down the channel alongside switching signals.

Library footprints

The KiCad Package_DIP library carries DIP-40 in these through-hole variants:

• DIP-40_W15.24mm — 600 mil, plus LongPads, Socket and Socket_LongPads variants
• DIP-40_W25.4mm — 1000 mil, plus LongPads, Socket and Socket_LongPads variants
• DIP-40_W16.51mm and DIP-40_W26.67mm — SMD socket variants at 650 and 1050 mil
• SMDIP-40 at 15.24 mm and 25.24 mm — surface-mount DIP versions

Both widths get full LongPads and Socket treatment, so whichever you need is available without drawing it. Type the width explicitly rather than picking the first DIP-40 entry from an autocomplete list.

Availability and cost

The 40-pin DIP survives on 8-bit microcontroller demand. Verified DigiKey listings:

Part	Function	Package	Status	Qty-1	Stock
PIC16F877A-I/P	PIC MCU, 14 KB flash, 33 I/O	40-DIP (0.600 in)	Active	$6.80	1,384
PIC16F874A-I/P	PIC MCU, 7 KB flash	40-DIP	Active	$6.31	—
A-40-LC-TT	40-position DIP socket, tin	40-position	Active	$1.36	—

Two things worth noting. The PIC16F877A-I/P carries a 5-week manufacturer standard lead time with 1,384 units in stock, which is healthy for a through-hole part in 2026. It is also DigiKey-programmable, so pre-programmed parts are available without a separate handling step.

At $6.80 the DIP is not cheap relative to its surface-mount siblings. The same die in TQFP-44 sells for less and uses a fraction of the board area. What the DIP buys you is socketability, hand assembly, and the ability to pull and reprogram a part without touching the board.

The socket is the quiet cost. At $1.36 for the Assmann A-40-LC-TT, a socketed DIP-40 position costs about $8.16 in parts before you have soldered anything. That is worth it for development boards and field-serviceable equipment, and hard to justify in volume.

[IMAGE 3: A 600-mil DIP-40 microcontroller beside a 40-position DIP socket and an IC extractor tool | alt: “DIP-40 package next to a 40-pin DIP socket and an IC extractor”]

Design mistakes that cause rework

• Silkscreen drawn to one vendor drawing. Published body lengths run 52.07 to 52.45 mm and widths 13.97 to 14.22 mm. Draw to the larger figures.
• Assuming a shared pinout across 40-pin parts. Unlike byte-wide memory, there is no common pin map at 40 pins. A socket fits everything and matches nothing.
• Ignoring the height spread. NXP publishes 5.08 mm against 4.06 mm on the Microchip part. That 1 mm matters under a stacked board.
• Hole sized from nominal lead width. Size from the datasheet maximum, then round up to a 0.9 mm stocked drill.
• Levering the part out at one end. Forty leads bend easily. Use a 40-pin extractor and lift evenly.
• Committing the board area without checking the alternative. A DIP-40 takes roughly 7 square centimetres of grid. Price the TQFP version before you spend it.

Frequently asked questions

What is a DIP-40 package?

A 40-lead dual in-line package with twenty through-hole leads per side on 2.54 mm pitch, rows 15.24 mm apart. The plastic version is PDIP-40. It was the standard body for 8-bit microprocessors and mid-range microcontrollers, and remains in production for parts like the PIC16F87XA family.

What are the dimensions of a DIP-40?

NXP specifies its DIP40 as 13.97 mm wide, 52.07 mm long and 5.08 mm high at 2.54 mm pitch. Microchip parametric data for the PIC16F877A-I/P gives 14.22 by 52.45 by 4.06 mm. The hole pattern spans 48.26 mm regardless of vendor.

Is DIP-40 always 600 mil?

Nearly always in modern parts. Footprint libraries also carry a 1000 mil (25.4 mm) variant used by some early microprocessors. Measure across the lead tips to settle it, or read the row spacing from the distributor package field.

How do I identify pin 1 on a DIP-40?

Look for a notch, molded dot, or chamfer at one end. With the notch at the top and leads pointing away, pin 1 is the upper-left lead. Numbering runs counterclockwise: down the left to pin 20, then up the right side from 21 to 40.

What hole size should I use for a DIP-40 footprint?

Size from the maximum lead width in your datasheet. For a 0.58 mm maximum, IPC-2222 Level B gives 0.78 mm minimum and Level A gives 0.83 mm. Round to a 0.9 mm drill with a 1.6 mm pad for a Class 2 default.

Are DIP-40 microcontrollers still available?

Yes. The PIC16F877A-I/P is Active with 1,384 units in stock at DigiKey and a 5-week lead time. It costs more than the surface-mount equivalent and uses far more board area, but remains the standard choice for socketed and hand-assembled designs.

What to do next

Confirm the row spacing first. For anything designed since the 1990s it will be 15.24 mm, but the 1000 mil variant exists and both have stock library footprints. Read it from the distributor package field rather than assuming.

Set the drill at 0.9 mm, draw the silkscreen to about 52.6 by 14.4 mm, and use the channel between the pad rows for decoupling and routing. Those three choices cover most of what goes wrong at this size.

Then make the honest call on package. If the board is a development platform, a teaching board, or field-serviceable equipment where someone will pull the chip, the DIP earns its area and its price. For anything going to volume, price the TQFP version and the board space it frees before committing 7 square centimetres to one component.