A DIP-32 is almost always 15.24 mm between lead rows on 2.54 mm pitch, and almost always holds parallel memory. The 300-mil variant exists in footprint libraries but is rare in real parts. This page gives verified dimensions with tolerances, the pin-1 rule, and the hole-size arithmetic.

Key takeaways

• Pitch is 2.54 mm (0.100 in). Row spacing E is 15.24 ± 0.254 mm on the standard 600 mil part.
• Alliance Memory publishes body length D as 41.910 ± 0.127 mm for its 32-pin 600 mil P-DIP.
• The hole pattern spans 38.10 mm end to end, fixed by 15 spaces × 2.54 mm.
• Microchip’s packaging specification lists PDIP outlines at 28 and 40 leads with no 32-lead entry. The 32-pin DIP came from the memory industry, not the general-purpose MCU lines.
• Nearly every DIP-32 in production is parallel memory: SRAM, EEPROM, EPROM or NOR flash.
• Lead times are the real constraint. The AS6C4008-55PCN carries a 20-week manufacturer lead time even with stock on the shelf.

What is a DIP-32 package?

A DIP-32 package is a 32-lead dual in-line package: a rectangular molded body with sixteen through-hole leads down each long side on 2.54 mm pitch. The two lead rows sit 15.24 mm apart on the standard part. It mounts through plated holes or into an IC socket. PDIP-32 denotes the plastic-bodied version.

The device mix at this pin count is narrower than at any smaller DIP size. Thirty-two pins is what a byte-wide parallel memory needs: an address bus wide enough for 128 KB to 512 KB, eight data lines, three control lines and power. That is why the package exists and why almost nothing else uses it.

Distributors spell out the width. DigiKey lists the AS6C4008-55PCN as 32-DIP (0.600″, 15.24mm) with supplier device package 32-PDIP. Treat a listing that gives only “32-PDIP” as incomplete, though at this pin count the 600 mil assumption is usually safe.

[IMAGE 1: DIP-32 package outline drawing with body length D, row spacing E, lead tip spread eB, pitch e and lead dimensions | alt: “DIP-32 package dimensions diagram showing 2.54 mm pitch and 15.24 mm row spacing”]

DIP-32 dimensions

The table below is from the Alliance Memory AS6C4008 datasheet, revision v1.4 dated August 2009, which publishes a complete 32-pin 600 mil P-DIP outline with tolerances. Values in millimetres as printed.

Dimension	Symbol	Value (mm)	Note
Standoff	A1	0.381 min	Body does not sit flush
Molded body thickness	A2	3.937 ± 0.127
Lead width	B	0.457 ± 0.127	Max 0.584; sets the drill
Body length	D	41.910 ± 0.127	Excludes mold flash
Row spacing	E	15.240 ± 0.254	Nominal 600 mil
Molded body width	E1	13.843 ± 0.127	Excludes mold flash
Lead pitch	e	2.540 typ
Lead tip spread	eB	16.256 ± 0.508	Splayed, as measured
Lead length	L	3.302 ± 0.254
End lead to body	S	1.905 ± 0.254	Excludes mold flash
Shoulder detail	Q1	1.778 ± 0.127

Three width figures again need separating. E1 at 13.843 mm is the molded plastic. E at 15.240 mm is the row spacing your footprint uses. eB at 16.256 mm is the lead tip spread, wider because the leads splay outward before insertion. Calipers on a loose part read eB.

The tolerance on eB is the loosest on the drawing at ±0.508 mm. That spread is why a fresh DIP-32 often will not drop into a socket without rolling the leads inward against a flat surface first.

Body length varies by vendor, as usual

Alliance Memory gives D as 41.910 ± 0.127 mm, so 41.783 to 42.037 mm. RS Components lists the Microchip SST39SF010A-70-4C-PHE at 42.04 mm long by 13.97 mm wide by 3.81 mm high. Those agree at the top of the Alliance tolerance band, which is reassuring but not identical.

Draw silkscreen to roughly 42.1 mm and you will clear both. As with every DIP size, the hole pattern is fixed and the body is not.

Why there is no JEDEC-standard 32-lead PDIP in some vendor catalogs

Microchip’s packaging specification is worth a look here. Its PDIP index runs 8, 14, 16, 18, 20, 24, 28, then 40 leads. There is no 32-lead PDIP entry, even in revisions that document 32-lead PLCC in detail.

The 32-pin DIP came out of the memory industry rather than the general-purpose logic and microcontroller lines, and it followed the JEDEC byte-wide memory pinout convention instead of a mainstream PDIP outline family. That is why you will more often find its drawing inside a memory datasheet, as with the Alliance table above, than in a vendor package handbook.

The practical consequence: when you need a DIP-32 outline, go to the datasheet of the specific memory part. Do not expect a package handbook to carry it.

DIP-32 pinout and pin 1 identification

Pin 1 sits at one end, marked by a notch, a molded dot, or a chamfered corner. Orient the package with the notch at the top and the leads pointing away from you. Pin 1 is the upper-left lead. Numbering runs down the left side to pin 16, across the end, and back up the right side from pin 17 to pin 32.

For a DIP-32 specifically:

• Left column, top to bottom: pins 1 through 16
• Right column, bottom to top: pins 17 through 32
• Pin 1 and pin 32 face each other across the body
• Pin 16 and pin 17 face each other at the opposite end

At this pin count the pinout is close to standardised across vendors, because byte-wide memories follow a common JEDEC convention. On the AS6C4008 the arrangement is address lines down the left side from A18 at pin 1, VCC at pin 32 and VSS at pin 16, with the data bus DQ0 to DQ7 gathered at pins 13 to 15 and 17 to 21.

That convention is what makes DIP-32 memory largely pin-compatible across densities. A 512 Kbit and a 4 Mbit part in the same package usually differ only in how many of the upper address pins are real rather than no-connect.

[IMAGE 2: Top-down DIP-32 pinout diagram with notch, pin 1 dot, and numbering 1 to 32 counterclockwise | alt: “DIP-32 pinout diagram showing pin 1 notch and counterclockwise pin numbering to pin 32”]

One caution for anyone swapping densities in a socket. Pins that are no-connect on a smaller part may be live address lines on a larger one. Check the specific datasheet rather than assuming an upgrade drops in.

DIP-32 footprint: hole and pad sizing

Sixteen holes per row on 2.54 mm pitch, rows at 15.24 mm. The hole pattern spans 15 × 2.54 mm = 38.10 mm end to end. That figure is fixed by pin count and identical for every DIP-32.

Size the hole from the maximum lead width. The Alliance drawing gives B as 0.457 ± 0.127 mm, so the maximum is 0.584 mm. Use that rather than the nominal.

Applying the IPC-2222 density levels to a 0.584 mm maximum lead:

• Level A: minimum hole = max lead diameter + 0.25 mm → 0.584 + 0.25 = 0.83 mm
• Level B: + 0.20 mm → 0.78 mm
• Level C: + 0.15 mm → 0.73 mm

Then the pad. Pad diameter = minimum hole size + (2 × minimum annular ring) + minimum fabrication allowance, where the minimum annular ring is 0.05 mm and the fabrication allowance is 0.6 mm for Level A, 0.5 mm for Level B and 0.4 mm for Level C.

Level B worked through: 0.78 + (2 × 0.05) + 0.5 = 1.38 mm pad on a 0.78 mm hole.

Round up to a stocked drill. 0.9 mm is a sensible choice here rather than the 0.8 mm that suits narrower DIPs, because the 0.584 mm lead maximum leaves less clearance than a 0.51 mm one. A 1.6 mm pad on a 0.9 mm hole is a manufacturable Class 2 default.

Two checks before committing:

• Aspect ratio. Keep board thickness to hole diameter under 10:1 for reliable plating. A 0.9 mm hole is good to 9 mm of board, so this never binds in practice.
• Annular ring class. IPC-6012 Class 3 requires a minimum 0.001969 in external-layer annular ring measured from the finished hole to the land edge. Class 2 permits 90-degree breakout provided the land-conductor junction is teardropped.

Routing and decoupling under a 600-mil DIP-32

The 15.24 mm row spacing leaves a generous channel. With 1.6 mm pads on 15.24 mm centres, the clear gap between opposing pad edges is about 13.6 mm. On a two-layer board that is enough to route a full byte-wide data bus straight down the middle.

Put the decoupling capacitor in that channel, close to VCC and VSS. On the AS6C4008 pinout those are pins 32 and 16, which sit at diagonally opposite corners of the package. A single cap cannot be close to both, so the usual approach is one 100 nF ceramic adjacent to the VCC pin with a short return to the ground plane.

Parallel memory switches eight outputs at once, so supply transients are larger than on a logic part of similar size. Do not skip the bulk capacitor on the rail feeding a bank of these.

Library footprints and a naming inconsistency

The KiCad Package_DIP library carries DIP-32 in these through-hole variants:

• DIP-32_W15.24mm — 600 mil, plus LongPads, Socket and Socket_LongPads variants
• DIP-32_W7.62mm — 300 mil, a single entry with no LongPads or Socket variants
• DIP-32_W16.51mm — SMD socket variant at 650 mil
• SMDIP-32 at 7.62, 9.53, 11.48 and 15.24 mm — surface-mount DIP versions

The 300-mil entry is worth treating with care. It is the only through-hole DIP footprint in the whole library described as a “32-lead dip package” rather than the standard “32-lead though-hole mounted DIP package” wording used everywhere else, and it is the only DIP-32 width with no Socket or LongPads companions. If you select it, verify its pad geometry against your part rather than assuming it received the same review as the 600-mil family.

What actually ships in DIP-32

The device mix is narrow and almost entirely memory. Verified listings:

Part	Function	Package	Status	Qty-1	Stock
AS6C4008-55PCN	SRAM, 4 Mbit (512K × 8)	32-DIP (0.600 in)	Active	$10.66	1,638
AS6C4008-55PIN	Same, industrial temp	32-PDIP	Active	$14.98	1,656
AS6C1008-55PCN	SRAM, 1 Mbit	32-DIP	Active	$8.58	—
AT27C010-70PU	EPROM, 1 Mbit	32-DIP	Active	$4.62	—
SST39SF010A-70-4C-PHE	NOR flash, 1 Mbit	32-PDIP (600 mil)	See note	—	—

Two things stand out. First, price. A DIP-32 SRAM runs $8 to $15 in single quantity, several times what the same die costs in TSOP or SOP. The AS6C4008 is offered in six packages, and the 600 mil P-DIP is the most expensive way to buy it.

Second, lead time. DigiKey shows a 20-week manufacturer standard lead time on the AS6C4008-55PCN despite 1,638 units in stock. Distributor stock is the entire supply for months at a time. If a production build needs these, buy the whole run at once rather than trusting reorder.

RS Components has already dropped the SST39SF010A-70-4C-PHE from its catalog, listing it as no longer stocked. The surface-mount versions of the same flash die remain widely available. That is the pattern across this package: the die lives on, the DIP body does not.

[IMAGE 3: A 600-mil DIP-32 memory IC beside a 32-pin wide IC socket and a PLCC-32 to DIP-32 adapter | alt: “DIP-32 package next to a 32-pin DIP socket and a PLCC to DIP-32 adapter”]

Sockets, programmers and adapters

DIP-32 is the native format of most bench EPROM programmers, which is why the package persists in repair and retro-computing work long after new designs stopped specifying it. A ZIF socket on a programmer is DIP-32 wide, and smaller DIP parts sit in the pin-1 end of the same socket.

PLCC-32 to DIP-32 adapters are a standard item, letting a surface-mount flash part be programmed in a DIP-only programmer or dropped into a legacy DIP socket. If a design must keep a socketed DIP-32 after the through-hole part disappears, that adapter route is the realistic path.

Design mistakes that cause rework

• Sizing the hole from nominal lead width. The Alliance drawing gives 0.457 ± 0.127 mm, so the maximum is 0.584 mm. Size from the maximum and use a 0.9 mm drill.
• Drawing silkscreen to the hole pattern. The pattern is 38.10 mm but the body runs to about 42.0 mm. Leave room at both ends.
• Assuming a package handbook has the outline. Several vendors list no 32-lead PDIP. Take dimensions from the specific memory datasheet.
• Dropping a higher-density part into an existing socket. No-connect pins on a smaller memory become address lines on a larger one. Compare datasheets pin by pin.
• Trusting reorder on a 20-week lead time. Distributor stock is the supply. Buy the full build quantity in one go.
• Selecting the 300-mil library footprint without checking it. The KiCad DIP-32_W7.62mm entry is described differently from every other through-hole DIP and has no socket variant.

Frequently asked questions

What is a DIP-32 package?

A 32-lead dual in-line package with sixteen through-hole leads per side on 2.54 mm pitch, rows normally 15.24 mm apart. The plastic version is PDIP-32. At this pin count it almost always holds byte-wide parallel memory: SRAM, EEPROM, EPROM or NOR flash.

What are the dimensions of a DIP-32?

Alliance Memory publishes body length 41.910 ± 0.127 mm, row spacing 15.240 ± 0.254 mm, molded width 13.843 ± 0.127 mm and lead pitch 2.540 mm typical for its 32-pin 600 mil P-DIP. The hole pattern spans 38.10 mm regardless of vendor.

Is DIP-32 always 600 mil?

Nearly always in real parts. Footprint libraries carry a 300 mil DIP-32 and surface-mount DIP variants at several widths, but production 32-pin memory is 600 mil. Check the distributor package field before laying out.

How do I identify pin 1 on a DIP-32?

Look for a notch, molded dot, or chamfer at one end. With the notch at the top and leads pointing away, pin 1 is the upper-left lead. Numbering runs counterclockwise: down the left to pin 16, then up the right side from 17 to 32.

What hole size should I use for a DIP-32 footprint?

Size from the 0.584 mm maximum lead width. IPC-2222 Level B gives 0.78 mm minimum and Level A gives 0.83 mm. Round to a 0.9 mm drill with a 1.6 mm pad for a manufacturable Class 2 default.

Are DIP-32 parts still available?

Yes, but as legacy production. Parallel SRAM, EEPROM and flash remain active in 32-pin DIP, priced several times above their surface-mount equivalents and often carrying 20-week lead times. Some parts have already been dropped by individual distributors.

What to do next

For a DIP-32 footprint, use the 15.24 mm library entry and take your dimensions from the datasheet of the specific memory part. A package handbook probably will not have the outline, and the 300-mil library variant deserves inspection before you trust it.

Set the drill at 0.9 mm rather than the 0.8 mm you would use on a narrower DIP. The 0.584 mm lead maximum at this pin count is wider than on 300-mil packages and leaves less insertion clearance.

On sourcing, treat lead time as the binding constraint rather than price. Twenty weeks with stock on the shelf means the shelf is the supply. Buy the whole build at once, and if the design is new rather than a repair, price the TSOP or SOP version of the same die before committing to the through-hole body.