Semiconductor packaging is the back-end process that turns a bare silicon die into a usable component. It protects the die, routes its I/O to the board, carries heat away, and gives assembly a standard body to place. This guide explains the packaging process step by step and maps the package types — from through-hole DIP to 3D-stacked chiplets — with the pitch, I/O, and thermal numbers that actually separate them.
Key takeaways
- Packaging does four jobs: protection, electrical I/O, a heat path, and a standard body for handling.
- The back-end flow runs wafer thinning → dicing → die attach → interconnect → molding → marking → ball attach → singulation → test.
- The interconnect method — wire bond, flip chip, or hybrid bonding — drives density and cost more than the outline does.
- Pitch scales from DIP at 2.54 mm down to fine-pitch BGA and WLCSP below 0.5 mm; flip-chip copper pillar reaches 40 µm, and hybrid bonding goes sub-10 µm.
- Advanced packaging — 2.5D (CoWoS, EMIB), 3D (Foveros, SoIC), HBM, and chiplets on UCIe — exists to beat the reticle limit and shorten die-to-die links.
- A datasheet θJA is board-dependent: the same package can read about 50 % higher on a bare board than on the JEDEC test board it was measured on.
What semiconductor packaging does
Semiconductor packaging is the set of assembly steps that encloses a die and connects it to the outside world. It protects the silicon from moisture and mechanical stress, fans the die’s tiny bond pads out to board-level pitch, conducts heat from the junction to the case or board, and standardizes the body so pick-and-place and reflow can handle it.
[IMAGE 1: cutaway of a packaged IC showing die, die attach, bond wires, leadframe, and mold compound | alt: “semiconductor package cutaway showing die, interconnect, leadframe and encapsulation”]
Engineers describe the connection in two levels. First-level packaging joins the die to a carrier — a leadframe or substrate — by wire bond or flip-chip bump. Second-level packaging joins that carrier to the PCB through leads, balls, or lands. The package you specify is really a stack of both.
The packaging process, step by step
The wafer arrives from the fab already fabricated and probed. Everything below is the back end, and the order matters because each step constrains the next.
- Wafer thinning (backgrind). The wafer back is ground and stress-relieved, often to 100–300 µm, so the finished package is thin and heat moves through the die.
- Dicing (singulation). A blade or laser cuts the wafer into individual dies along the scribe lines.
- Die attach. Each die is bonded to a leadframe pad or substrate with epoxy or solder.
- Interconnect. Bond pads are connected out — wire bonding with fine gold or copper wire, or flip-chip bumping with the die inverted onto the substrate.
- Encapsulation (molding). An epoxy mold compound encapsulates the assembly, or underfill flows beneath a flip-chip die.
- Marking, ball attach, and singulation. The package is laser-marked; for BGA, solder balls are attached; then units are singulated and leads are trimmed and formed.
- Final test and MSL bake/bag. Each part is electrically tested, then baked and sealed in a moisture-barrier bag per its moisture sensitivity level.
One fork splits the whole flow. In conventional packaging the wafer is diced first, then each die is packaged. In wafer-level packaging (WLP), part or all of the packaging is done on the wafer before dicing, which is how chip-scale packages stay close to die size.
Package types: from through-hole to area array
Packages sort by how they mount and how many I/O they carry. Through-hole gave way to surface mount; leaded gave way to leadless and then to area-array balls as pin counts climbed.
[IMAGE 2: side-by-side of DIP, SOIC, QFP, QFN, and BGA packages at matched scale | alt: “semiconductor package types compared: DIP, SOIC, QFP, QFN and BGA”]
The table lists the main families with typical interconnect, pitch, and I/O. Values are nominal; confirm against the specific datasheet.
| Family | Mounting | Interconnect | Typical pitch | Typical I/O | Where it fits |
| DIP / TO | Through-hole | Wire bond | 2.54 mm | 4–64 | Legacy logic, prototyping, power discretes |
| SOIC / SOP / SOT | SMT gull-wing | Wire bond | 1.27 mm and finer | 3–56 | Jelly-bean analog, logic, transistors |
| QFP (LQFP/TQFP) | SMT gull-wing, 4 sides | Wire bond | 0.4–1.0 mm | 32–300+ | MCUs, mid-density FPGAs, ASSPs |
| QFN / DFN | SMT leadless + exposed pad | Wire bond | 0.4–0.65 mm | 6–100 | Power-conscious, RF, compact SoCs |
| BGA (PBGA / FCBGA) | SMT area-array balls | Wire bond or flip chip | 1.0 / 0.8 / 0.5 mm | 100–2000+ | High-I/O SoCs, FPGAs, processors |
| LGA | SMT area-array lands | Wire bond or flip chip | 0.5–1.0 mm | 100–2000+ | Sockets, processors, modules |
| CSP / WLCSP | Wafer-level, near die size | Fan-in RDL + balls | 0.35–0.5 mm | 4–200 | Mobile, space-constrained designs |
Two anchors are worth memorizing. A DIP has 2.54 mm lead pitch, which is why it fits breadboards. A QFP runs 0.4–1.0 mm across 32 to 300-plus leads, per package vendor outlines. Below QFN, the die stops fanning out to leads and starts talking to the board through balls.
The QFN earns its place with an exposed thermal pad on the bottom, which drops thermal resistance sharply versus a leaded package of the same size. Once I/O passes a few hundred, BGA and LGA win because area-array packs far more connections under the body than any perimeter-lead package can.
Wire bond vs flip chip: the interconnect that defines the package
The single choice that shapes a package’s density, electrical performance, and cost is how the die connects to its carrier.
Wire bonding runs fine wire from perimeter die pads up to the substrate. It is mature and cheap, but the loops add inductance and the pads have to sit on the die edge. Flip chip inverts the die and drops it onto the substrate through an area array of bumps, using the whole die face and shortening every connection.
The footprint difference is concrete. For one die, a copper-pillar flip-chip build fits an 11 mm × 11 mm package with a die-to-package area ratio of 0.71, while the smallest wire-bond package for the same die is 19 mm × 19 mm at a ratio of 0.23, with a Z-height of 1.71 mm (per an ISOM Cu-pillar characterization paper). Flip chip is smaller, thinner, and faster — at higher substrate cost.
Interconnect pitch is where the roadmap lives:
| Interconnect | Pitch / size | Notes |
| Wire bond | Perimeter pads, loop-limited | Gold or copper wire; lowest cost |
| C4 solder bump | 200 → 75 µm diameter | Original flip chip; coarse pitch |
| Copper pillar / microbump | 130 → 40 µm | Finer pitch, better current and heat |
| Cu-Cu hybrid bond | Sub-10 µm (to ~1 µm) | No solder; highest density, 3D |
Those numbers come from primary sources. C4 bumps range from 200 µm down to 75 µm in diameter, and starting at the 65 nm node in 2006 the industry moved to copper microbumps that began near 25 µm, per Semiconductor Engineering. Copper pillar reaches finer than 130 µm down to 40 µm (per an IPC fine-pitch paper), and hybrid bonding replaces solder with direct copper-to-copper joints at sub-10 µm — Sony has shown 1 µm pitch.
Advanced packaging: 2.5D, 3D, fan-out, and chiplets
When a design outgrows one reticle or needs terabytes-per-second between dies, the answer is to package multiple dies together. This is where the field’s growth is, driven by AI, HPC, and memory.
[IMAGE 3: cross-sections of 2.5D interposer, embedded bridge, and 3D-stacked packages | alt: “advanced packaging cross-sections: 2.5D interposer, embedded bridge and 3D stack”]
The architectures split by how dies are integrated and how they talk to each other.
| Architecture | Integration | Die-to-die link | Example use | Lead vendor |
| Fan-out WLP (InFO) | RDL, no substrate | Redistribution traces | Mobile application processors | TSMC, ASE, Amkor |
| 2.5D interposer (CoWoS, I-Cube) | Dies on silicon interposer | Microbumps + TSV (~1200 IO/mm²) | AI/HPC GPUs with HBM | TSMC, Samsung |
| Embedded bridge (EMIB) | Dies on substrate with Si bridge | Microbumps (~800–1000 IO/mm²) | Server CPUs with HBM | Intel |
| 3D stacking (Foveros) | Dies stacked on active base | Microbumps ~36–50 µm | Client CPU tiles | Intel |
| 3D hybrid bonding (SoIC, Foveros Direct) | Cu-Cu bonded dies | Sub-10 µm, no solder | Cache stacking, HBM4 | TSMC, Intel |
| HBM | Stacked DRAM over logic | TSV + microbumps | High-bandwidth memory | SK hynix, Samsung, Micron |
The verified figures set these apart. Intel Foveros-S 2.5D uses a 36 µm microbump pitch (per Intel’s product brief), down from 50 µm on the first-generation part. CoWoS delivers roughly 1200 IO/mm² against EMIB’s 800–1000 IO/mm², and EMIB runs 30–40 % cheaper than a full interposer (per an EMIB analysis). Above roughly 10 µm pitch, microbumps still work; below it, hybrid bonding at 9–10 µm is now in commercial production.
Chiplets tie this together. Instead of one large die, a design is split into smaller dies — often on different process nodes — and reassembled in one package. UCIe (Universal Chiplet Interconnect Express) is the open die-to-die standard that lets chiplets from different vendors interoperate. The catch of 3D is yield: a single bad die in a stack scraps the whole stack, so known-good-die testing and thermal design get harder.
The standards that govern packaging
Package outlines, moisture handling, and thermal ratings are not vendor inventions. Three JEDEC documents do most of the work.
JEP95 (JEDEC Publication 95) is the registry of package outlines — over 500 registrations across some 3000 pages. It is why part numbers map to standard bodies: the SOT-23 transistor is JEDEC type TO-236, and the plastic QFP is MO-086, per JEDEC. Surface-mount resistors and capacitors are not in JEP95; those live in separate EIA publications.
IPC/JEDEC J-STD-020 classifies moisture and reflow sensitivity for plastic surface-mount devices. It defines MSL 1 through 6, the reflow peak temperature, and the floor life — how long a part may sit out of its dry bag. Skip the bake and the trapped moisture flashes to steam at reflow, causing popcorn cracking, delamination, and wire necking, per the standard’s own failure list.
JESD51 defines how thermal resistance is measured, and this is the number engineers misuse most. θJA depends on the test board. A 2s2p board (two signal, two plane layers, per JESD51-7) pulls heat far better than a bare 1s0p board (JESD51-3) — the difference is about 50 %, per Electronics Cooling. The datasheet’s headline θJA usually reflects the good board.
Worked example. Suppose a package lists θJA = 40 °C/W on a 2s2p board. On a bare board it may be near 80 °C/W. At 1 W dissipation in a 55 °C ambient, the good-board number predicts a junction temperature of 95 °C, but the real bare board gives:
TJ = 55 °C + (80 °C/W × 1 W) = 135 °C
That 40 °C error can blow past a 125 °C limit. Design to the board you actually have, and for automotive parts, confirm the grade is AEC-Q100 qualified.
How to choose a package
Work the decision in this order, and the field narrows fast.
- Set the I/O count. Under ~100 pins, a QFP or QFN usually fits; past a few hundred, move to BGA or LGA.
- Fix the thermal budget. Compute TJ from θJA and your real board; if it is tight, choose an exposed-pad QFN, a flip-chip package, or add copper and vias.
- Weigh assembly capability. Fine-pitch BGA and WLCSP need reflow and X-ray inspection; leaded packages tolerate hand rework.
- Check board space and height. For thin or dense products, flip chip and wafer-level packages shrink both footprint and profile.
- Confirm supply and compliance. Verify MSL handling, RoHS/REACH, and — for cars — AEC-Q100, and that a second source exists in the same outline.
Packaging mistakes that cause respins
- Using the datasheet θJA on a bare board, so junction temperature runs far hotter than predicted.
- Ignoring MSL floor life and reflowing moisture-loaded parts, causing popcorn cracking.
- Under-designing the QFN thermal pad — too few vias — so the exposed-pad advantage is lost.
- Specifying fine-pitch BGA without X-ray inspection or the rework capability to match.
- Drawing a footprint from the body outline instead of the JEDEC land pattern.
- Assuming package interchangeability across vendors without checking the JEP95 outline and ball map.
FAQ
What is semiconductor packaging?
Semiconductor packaging is the back-end process that encloses a silicon die and connects it to a board. It protects the die, routes its I/O out to usable pitch, carries heat away, and provides a standard body for assembly. The package spans first-level (die-to-carrier) and second-level (carrier-to-board) interconnect.
What are the steps in the semiconductor packaging process?
The main steps are wafer thinning (backgrind), dicing, die attach, interconnect (wire bond or flip chip), encapsulation or underfill, marking, ball attach for BGA, singulation and lead forming, then final test with moisture bake and bagging. Wafer-level packaging performs some steps before dicing rather than after.
What are the main types of semiconductor packages?
The main families are through-hole (DIP, TO), leaded surface-mount (SOIC, SOP, SOT, QFP), leadless (QFN, DFN), area-array (BGA, LGA), and chip-scale or wafer-level (CSP, WLCSP). They differ mainly in mounting style, pitch, and I/O count — from DIP at 2.54 mm to WLCSP below 0.5 mm.
What is the difference between wire bonding and flip chip?
Wire bonding runs fine wire from perimeter die pads to the substrate; it is cheap but adds inductance. Flip chip inverts the die onto the substrate through an area of bumps, using the whole die face for shorter, faster connections. Flip chip yields smaller, thinner, higher-performance packages at higher substrate cost.
What is the difference between 2.5D and 3D packaging?
In 2.5D, dies sit side by side on a shared silicon interposer or an embedded bridge, connected through microbumps and TSVs. In 3D, dies stack vertically and connect through TSVs with microbumps or, in the newest generation, direct copper-to-copper hybrid bonds. 3D gives the shortest links and highest density, but tighter thermal and yield limits.
What is a chiplet, and what is UCIe?
A chiplet is a small die that is combined with other dies in one package instead of building a single large die, often mixing process nodes. UCIe (Universal Chiplet Interconnect Express) is the open die-to-die interconnect standard that lets chiplets from different vendors work together, which is central to advanced 2.5D and 3D designs.
The bottom line
Start from I/O count and the thermal budget on your real board, then let those pick the family. For most designs, a QFP or exposed-pad QFN covers moderate pin counts, and BGA or LGA takes over as I/O climbs. Reach for flip chip or wafer-level packaging when size, height, or speed demand it, and for multi-die systems, evaluate 2.5D, 3D, and chiplets on UCIe. Whatever you choose, size the thermals to the board you will actually build and handle the part to its MSL — those two mistakes cause more respins than the outline ever will.
