Picking a package is not a cosmetic choice made after the schematic is done. It fixes your thermal ceiling, your minimum PCB class, whether you can rework a board by hand, and whether the part will still be buildable in three years. This IC package selection guide turns that decision into a repeatable procedure and puts a verified number behind each threshold, so you commit to a footprint with evidence instead of habit.
Key takeaways
- Package choice is driven by six inputs: pin count and pitch, thermal budget, assembly capability, signal speed, availability, and cost. Rank them for your project before looking at any datasheet.
- The datasheet junction-to-ambient value is measured per JESD51-7 on a 1-inch-square FR-4 board under natural convection, a condition that rarely matches a real application.
- Moisture sensitivity level (MSL) sets factory floor life. An MSL 3 part has 168 hours of floor life; MSL 4 has 72; MSL 5a has just 24, after which the reel must be baked.
- QFN and BGA win on thermal and density but demand reflow and, for BGA, X-ray inspection. Do not put them in a first prototype without that infrastructure.
- Confirm your fabricator can hold the trace and space a fine-pitch part needs before you commit. A 0.4 mm-pitch QFP or micro-BGA requires trace and space widths down to 75 to 100 micrometres.
What package selection actually decides
Choose wrong early and the cost lands later, in places that are expensive to unwind. Four consequences do most of the damage.
Thermal path is the first. Packages with an exposed thermal pad or die-attach area, such as QFN and BGA, cut junction-to-board resistance sharply. A QFN running a power regulator can move heat several times more efficiently than the same die in an SOIC. Signal integrity is the second: above roughly a gigahertz, lead inductance and interconnect length become parasitic elements, and short-interconnect packages pull ahead. The third is manufacturability, where fine-pitch and leadless parts raise the floor on PCB tolerance, stencil design, and inspection. The fourth is field reliability, where mechanical attachment and moisture behaviour decide whether joints survive vibration and thermal cycling.
The six inputs that drive IC package selection
IC package selection comes down to six inputs: pin count and pitch, thermal dissipation, assembly capability, signal speed, part availability, and cost. Rank them for your specific board first, because the highest-ranked constraint usually eliminates most of the options before you compare the survivors on the rest.
Pin count sets the floor: a 200-I/O device will not fit a leaded package at a sane size, so the count alone often forces a quad-flat or array package. Pitch then interacts with your fab: wider pitch is forgiving, sub-0.5 mm pitch is not. Thermal budget decides whether you need an exposed pad. Assembly capability is the hard gate, since hand-build shops cannot place BGAs reliably. Signal speed pushes you toward stubless array packages as edge rates sharpen. Availability and cost are the constraints engineers discover last and regret most.
[IMAGE 1: decision-flow diagram mapping the six inputs to package families | alt: “IC package selection guide decision flow from pin count, thermal, assembly, speed, availability and cost to package type”]
IC package comparison table
The table below is built for decisions, not description. It pairs pitch and hand-solderability with inspection method and the practical PCB class each package demands, the combination that actually determines whether a part is buildable on your line.
| Package | Mount | Pins | Pitch | Thermal path | Hand-solder? | Inspect / rework | Typical use |
| DIP | Through-hole | 4–64 | 2.54 mm | Moderate (leads) | Yes | Visual / easy | Breadboard, sockets, legacy |
| SOT-23 | SMD | 3–6 | 0.95 mm | Low–moderate | Yes | Visual / easy | Transistors, references, single-gate logic |
| SOIC | SMD | 8–28 | 1.27 mm | Moderate (leads) | Yes | Visual / easy | Op-amps, logic, LDOs, gate drivers |
| SSOP / TSSOP | SMD | 8–48 | 0.5–0.65 mm | Moderate | With care | Visual / medium | Space-limited logic and analog |
| LQFP / TQFP | SMD | 32–256 | 0.4–0.8 mm | Good | Flux + fine tip | Visual / medium | MCUs, DSPs, mid-range FPGAs |
| DFN | SMD | 2–16 | 0.4–0.5 mm | Excellent (pad) | Difficult | X-ray / hard | PMICs, current-sense, sensors |
| QFN | SMD | 8–128 | 0.4–0.65 mm | Excellent (pad) | Difficult | X-ray / hard | RF SoCs, PMICs, wireless MCUs, motor drivers |
| LGA | SMD | 4–2000+ | 0.5–1.0 mm | Excellent | No | X-ray / medium | CPUs (sockets), RF modules, MEMS |
| BGA | SMD | 100–2000+ | 0.4–1.0 mm | Excellent | No | X-ray / very hard | CPUs, FPGAs, DDR memory, SoCs |
| CSP / WLP | SMD | 4–400 | ≤0.4 mm | Good | No | X-ray / specialist | Phones, wearables, IoT nodes |
Pitch and pin ranges follow standard JEDEC-registered families. The workhorse embedded example is the STM32 line, which ships the same H7 core in both LQFP-144 and TFBGA-240 depending on whether pin count or board area dominates.
[IMAGE 2: side-by-side of QFP gull-wing leads versus QFN flush pads with exposed thermal pad | alt: “QFN versus QFP package comparison showing exposed thermal pad for IC package selection”]
A decision path from requirements to package
Work the choice in order. Each step either eliminates families or hands you a short list.
- Count your I/O, then check pitch against your fab. Under about 48 pins, SOIC or SOT variants stay in play. Past about 100 pins, you are in quad-flat or array territory. If the only option is sub-0.5 mm pitch, confirm your board house can hold it before going further.
- Compute the thermal requirement. Estimate power dissipation and the maximum ambient, then back out the junction-to-ambient resistance you need. If you need low resistance at real power, an exposed-pad package such as QFN or DFN is likely mandatory; a plain SOIC or QFP will not get there.
- Gate on assembly capability. Hand-build or hot-air rework only? Stay with DIP, SOIC, SOT, and manageable LQFP. Reflow line without X-ray? QFN is reachable, BGA is not. Full SMT line with X-ray? Everything is open.
- Check signal speed. Below a few hundred MHz, leaded packages are fine. Above a few hundred megahertz, QFP lead inductance starts to limit performance, and that is typically the trigger to move toward BGA.
- Verify availability and lifecycle in the exact package. Filter distributor stock by package before you commit. Some parts exist in only one package; DDR4 and DDR5 and high-end SoCs are BGA-only.
- Price the full package, not the chip. Fold in stencil, inspection, and rework burden, not just the unit cost of the device.
Thermal reality check: how to size the thermal resistance
Every device has a maximum junction temperature; exceed it and reliability collapses. The governing relation is simple:
TJ = TA + (P × θJA)
Here T_J is junction temperature, T_A is ambient, P is dissipated power, and theta-JA is junction-to-ambient thermal resistance in degrees C per watt. Rearrange it to find the theta-JA you can tolerate, then check candidate packages against that number.
The trap is the datasheet value itself. A datasheet junction-to-ambient figure is measured on a JEDEC JESD51-7 board, a 1-inch-square FR-4 coupon under natural convection, which almost never matches your stack-up, copper pour, or airflow. Treat it as a relative figure of merit between packages, not a prediction for your board.
Real numbers show the spread. Analog Devices lists the DS1620 in an 8-pin SO at a theta-JA of 27.72 degrees C per watt, fine for a milliwatt-class sensor and hopeless for a watt-class regulator. Junction-to-case tells a different story again: International Rectifier’s IRF2807 in TO-220 specifies a junction-to-case resistance of 0.65 degrees C per watt against a junction-to-ambient resistance of 62 degrees C per watt, a roughly 95-times gap that exists entirely because the case path assumes a heatsink and the ambient path does not. That same part carries a 1.5 W per degree C linear derating factor, a reminder that the 230 W on the front page is a heatsinked ceiling, not a free-air rating. Among surface-mount options, QFN junction-to-case runs about 2 to 10 degrees C per watt depending on die and pad area, DFN about 5 to 15, and power-QFN about 1 to 5. A well-designed QFN on a four-layer board reaches a junction-to-board resistance of roughly 3 to 5 degrees C per watt, but only when the pad is via-stitched to a plane, which is a layout obligation, not a given.
[IMAGE 3: annotated thermal-resistance path from die junction through case and board to ambient | alt: “Junction-to-ambient thermal resistance path used in IC package selection thermal calculation”]
Moisture sensitivity level (MSL): the spec that stops your line
Almost every IC-package guide skips the one spec most likely to scrap a production run. Plastic-encapsulated surface-mount parts absorb atmospheric moisture; at reflow, that moisture flashes to steam and can crack the package from the inside, the popcorn failure. IPC/JEDEC J-STD-020 rates this susceptibility on a scale from MSL 1, least sensitive, to MSL 6, most sensitive, and the rating dictates how long a part can sit in open factory air before it must be soldered or re-baked.
| MSL | Floor life after dry-pack opening | Condition |
| 1 | Unlimited | ≤30 °C / 85% RH |
| 2 | 1 year | ≤30 °C / 60% RH |
| 2a | 4 weeks | ≤30 °C / 60% RH |
| 3 | 168 hours | ≤30 °C / 60% RH |
| 4 | 72 hours | ≤30 °C / 60% RH |
| 5 | 48 hours | ≤30 °C / 60% RH |
| 5a | 24 hours | ≤30 °C / 60% RH |
| 6 | Bake before use | ≤30 °C / 60% RH |
Source: IPC/JEDEC J-STD-020 floor-life classification.
Two practical points follow. First, exceeding floor life is recoverable by baking, but bake time tracks package geometry, not MSL number: a thin QFN takes about 24 hours at 125 degrees C whether it is rated MSL 5a or MSL 3, because moisture-diffusion path length scales with mold-compound thickness. Second, this is a package-level decision input, not just a stockroom chore. A denser, thinner package tends to be more moisture-sensitive, so an MSL 3 or worse rating on a fine-pitch BGA is a real cost the moment your build volume grows.
Footprint, land pattern, and fab capability
A package is only as good as the land pattern under it. IPC-7351, harmonised as IEC 61188-5-1, covers land-pattern design for the full range of active and passive surface-mount devices, from SOP and QFP to BGA and QFN, and gives each component three geometries so you can trade robustness against density. Those tiers are Most, or Level A, for the largest and most solderable pads; Nominal, or Level B, as the default; and Least, or Level C, for the smallest compliant footprint in space-constrained designs. Pick the density level deliberately, because Least buys board area but leaves less margin for placement and inspection.
Leadless packages need extra attention. On a QFN, the centre thermal pad is a functional connection, not an anchor: it must be via-stitched to a plane, and the paste stencil must control solder volume. IPC-7093 caps voiding under the pad at 25% of its area, which in practice means a stencil aperture around 50 to 70% of the pad, split into several smaller openings rather than one large window. And before any of this matters, the fab has to be able to build it, since hitting 0.4 mm pitch means holding 75 to 100 micrometre trace and space, a tolerance not every shop guarantees.
Availability, second-sourcing, and lifecycle
The package that is easiest to design can still be the one that strands you. Three sourcing checks belong in the selection step, not after tape-out.
Confirm the part exists in your chosen package and has stock, because package availability is not uniform across a part number, and a QFN variant can be in stock while the BGA variant is on a 40-week lead. Prefer a package with a credible second source: general-purpose logic and analog in SOIC or LQFP usually have drop-in alternates, whereas a proprietary SoC in a vendor-specific BGA has none. And weigh lifecycle against your product’s life, since a consumer-grade part in a leading-edge CSP may reach end-of-life before an industrial design does, forcing a re-layout you could have avoided by choosing a more stable package from the start. For automotive and other high-reliability work, add the qualification layer: an AEC-Q100 grade tied to the package, and wettable-flank QFN variants when your line relies on optical inspection of side-view fillets.
Selection mistakes that cause field returns
The recurring failures cluster in a few places.
Treating the QFN thermal pad as optional is the classic one: leave it floating or skip the via array and you lose the entire thermal advantage that justified the package. Specifying BGA without an X-ray-equipped line is next, since hidden joints cannot be verified visually, and the result is intermittent failures that surface weeks later and resist root-cause analysis. Over-engineering the prototype is a quieter tax, because building an early board in BGA when the same die ships in LQFP slows every debug cycle for no benefit; use the accessible package during bring-up and migrate to the production package after validation. Finally, mismatching fab capability to package requirement, committing to a 0.4 mm-pitch part on a stack-up your board house cannot reliably hold, turns into bridging, opens, and yield loss that a five-minute capability check would have caught.
FAQ
How do I choose the right IC package?
Rank six inputs for your project: pin count and pitch, thermal budget, assembly capability, signal speed, availability, and cost, then eliminate families top-down. Your hardest constraint, often assembly capability or pitch, removes most options immediately; compare the survivors on the rest and verify stock in the exact package before committing.
What is the difference between QFN and QFP?
QFP has gull-wing leads on all four sides, so joints are visible and hand-reworkable. QFN has flush pads on the underside plus a central thermal pad, giving better thermal performance and a smaller footprint at equal pin count, but it needs reflow, and the pad cannot be inspected without X-ray. The footprints are not interchangeable.
Which IC package is best for beginners?
DIP, because it plugs into breadboards and sockets and tolerates hand soldering. SOIC is the right first surface-mount step: its 1.27 mm pitch is forgiving with a fine tip and flux. Leave QFN and BGA until you have a reflow process, since neither is realistically hand-solderable.
What is moisture sensitivity level (MSL)?
MSL is a J-STD-020 rating from 1 to 6 describing how long a surface-mount part can sit in open air before reflow risks internal cracking from absorbed moisture. MSL 1 is unlimited; MSL 3 allows 168 hours, MSL 5a only 24. Past the floor life, the part must be baked before soldering.
Can I swap a QFN for a QFP to make assembly easier?
Not directly, since they have different land patterns and cannot share a footprint. You would redesign the footprint, and the QFP’s larger size and lead inductance may not fit your board or speed budget. If hand-assembly is the goal, choose a leaded package at the schematic stage rather than substituting late.
Where this leaves you
Do this: write down your six inputs and rank them, size the junction-to-ambient resistance you actually need, then screen candidate packages against assembly capability and fab tolerance before you look at anything else. Use the most accessible package that meets the thermal and electrical requirement for prototypes, SOIC or LQFP where they fit, QFN when you need the thermal pad in a small footprint, and reserve BGA for designs where pin count or signal speed leave no alternative and you have reflow plus X-ray in place. Confirm stock, a second source, and MSL rating in that exact package on the day you commit, not after layout. The package is a system decision; make it with numbers, and the board that comes back from assembly will match the one you designed.
