Memory arrives in two distinct tiers, and confusing them is the most common mistake in a sourcing spreadsheet. TSOP and FBGA are chip-level packages that hold one die and solder to a board. DIMM and the newer LGA-based CAMM2 are module-level form factors that carry many chips on a small PCB. This guide covers all four memory package types with the dimensions, pin counts, and standards you need to specify or second-source correctly.
Key takeaways
- TSOP and FBGA package an individual DRAM or flash die; DIMM and LGA/CAMM2 are assemblies of those chips.
- High-speed DDR moved from TSOP to fine-pitch BGA because short balls beat long leads on signal integrity.
- A DDR5 SDRAM ×4/×8 die ships in a 78-ball VFBGA on an 0.8 mm × 0.8 mm ball pitch, per Micron’s 16 Gb datasheet.
- DDR5 desktop modules use 288 pins; DDR5 laptop SODIMMs use 262 pins — not interchangeable with DDR4.
- LGA-style CAMM2 modules deliver roughly 30% more bandwidth than DDR5 SODIMM at 5600 MT/s and 58% lower active power.
- Most fine-pitch BGA memory is MSL 3: bake before reflow if floor life is blown.
The two tiers: chip package vs. module form factor
A memory chip package encloses a single silicon die and presents its I/O as leads or balls for surface-mount soldering. TSOP and FBGA live here. A memory module is a small printed circuit board populated with several of those packaged chips plus support silicon, presented to the system through an edge connector or a land array. DIMM, SODIMM, and CAMM2 live here.
The distinction is practical, not academic. When a datasheet says a DDR5 device is a 78-ball FBGA, that is the chip. When a spec sheet says 262-pin SODIMM, that is the module the chip rides on. Design decisions — reflow profile, footprint, signal integrity, field-replaceability — depend on knowing which tier you are specifying.
TSOP: the legacy leaded package
TSOP (Thin Small Outline Package) is a rectangular surface-mount package with gull-wing leads and a profile of about 1 mm. It comes in two orientations: Type I places leads on the short sides, Type II on the long sides. Memory almost always used TSOP II — a 54-lead DRAM body runs roughly 22.22 mm long on a 0.5 mm lead pitch, per the JEDEC-referenced dimensions.
For a decade TSOP II was the default for SDRAM and early DDR. Its weakness is electrical: the leadframe adds inductance, and at PC133 speeds and above that inductance created signal-integrity problems in large memory arrays, which pushed high-speed DRAM to BGA. TSOP survives today in NAND and NOR flash, EEPROM, and low-speed SDRAM, where its exposed leads make hand-rework and chip-off data recovery far easier than a hidden ball array.
Common memory TSOP outlines and their JEDEC-referenced dimensions:
| Outline | Leads | Body W (mm) | Body L (mm) | Lead pitch (mm) |
| TSOP II 40/44 | 40/44 | 10.16 | 18.42 | 0.80 |
| TSOP II 54 | 54 | 10.16 | 22.22 | 0.80 |
| TSOP II 66 | 66 | 10.16 | 22.22 | 0.65 |
| TSOP I 48 | 48 | 12.0 | 18.4 | 0.50 |
| TSOP I 56 | 56 | 14.0 | 18.4 | 0.50 |
Source: Wikipedia TSOP dimension tables (Intel/JEDEC-referenced).
The 0.5 mm-pitch Type I outlines pack the most leads into the least length, which is why fine-pitch NOR flash favored them; the wider-pitch Type II outlines dominated DRAM before BGA took over.
FBGA: the modern DRAM chip package
FBGA (Fine-pitch Ball Grid Array) replaced TSOP for mainstream DRAM. Instead of peripheral leads, solder balls sit underneath the package on a fine grid, shortening every interconnect and cutting inductance. That is what lets DDR4 and DDR5 run at multi-gigatransfer speeds.
What package does DDR5 use? DDR5 SDRAM ships as a fine-pitch BGA. A ×4 or ×8 die uses a 78-ball VFBGA on an 0.8 mm × 0.8 mm ball pitch under JEDEC outline MO-210, while the ×16 organization adds rows for the wider data bus. Earlier DDR3 ×16 parts commonly used a 96-ball FBGA. Balls, not leads, are now the norm for anything fast.
FBGA’s advantages are density, a shorter thermal path to the board, and clean high-speed signaling. The trade-off is inspection and rework: the joints are hidden, so verification needs X-ray or boundary-scan, and rework needs a BGA rework station rather than a soldering iron. The very fine ball array under LPDDR also enables package-on-package (PoP) stacking directly on an SoC, which no leaded package can match.
DIMM and SODIMM: the module form factor
A DIMM (Dual In-line Memory Module) is a PCB carrying multiple FBGA DRAMs, an SPD EEPROM, and — on DDR5 — an on-module power management IC and, for registered parts, a register/clock driver. The system talks to it through a gold edge connector. SODIMM is the small-outline version for laptops and compact systems.
Pin count is keyed to generation, and physical notch positions block the wrong module from seating. Note that DDR4 and DDR5 desktop DIMMs both use 288 pins but are electrically incompatible and notched differently, and their supply drops from 1.2 V on DDR4 to 1.1 V on DDR5.
| Generation | DIMM (desktop/server) | SODIMM (laptop) | Module voltage |
| DDR | 184-pin | 200-pin | 2.5 V |
| DDR2 | 240-pin | 200-pin | 1.8 V |
| DDR3 | 240-pin | 204-pin | 1.5 V / 1.35 V |
| DDR4 | 288-pin | 260-pin | 1.2 V |
| DDR5 | 288-pin | 262-pin | 1.1 V |
Sources: Wikipedia SO-DIMM pin list; Kingston and VisionTek module specifications.
DDR5 SODIMMs carry 262 pins versus 260 on DDR4, a two-pin difference that still requires a different socket.
DIMMs also split by buffering: UDIMM (unbuffered, mainstream desktop), RDIMM (registered, servers), and LRDIMM (load-reduced, highest-capacity servers). The choice trades signal loading and latency against how many ranks you can hang on a channel.
DDR5 also moved regulation onto the stick: each module carries its own power management IC instead of relying on the motherboard’s rails, and the module splits into two independent 32-bit sub-channels (40-bit with ECC) rather than one 64-bit bus. That is why a DDR5 module is not just a faster DDR4 module — the board itself is architecturally different, and the notch position shifts so a DDR5 stick physically cannot seat in a DDR4 socket.
LGA, CAMM2, and LPCAMM2: the compression-attached future
This is where LGA enters memory. Traditional modules use an edge connector; the new CAMM2 family uses a compression-attached land grid array — flat gold lands on the module pressed onto pins in a connector by a retention plate, the same land-array principle used under CPUs. JEDEC standardized it as JESD318, published in November 2023, defining both DDR5 and LPDDR5/5X compression-attached memory modules.
The numbers are the story. LPCAMM2 uses a 644-pin interface with a 128-bit dual-channel architecture, supports up to 128 GB, and reaches 7500 MT/s with LPDDR5X. The connector itself carries 644 or 666 pins on a 1 mm × 1.38 mm pitch and can operate without ground shielding, per Amphenol’s CAMM2 data. Against a DDR5 SODIMM at 5600 MT/s, LPCAMM2 delivers about 30% more bandwidth, 58% lower active power, and 80% lower standby power.
The design win is that CAMM2 makes LPDDR replaceable. Previously, LPDDR5X had to be soldered to the board (memory-down); CAMM2 turns it into a serviceable module while cutting form factor roughly 50% versus a SODIMM connector at similar Z-height. The format began as Dell’s proprietary CAMM before being opened to JEDEC — a rare case of a vendor handing its form factor to the standards body.
Parametric comparison: all four memory package types
| Attribute | TSOP (II) | FBGA / VFBGA | DIMM / SODIMM | LGA (CAMM2) |
| Tier | Chip package | Chip package | Module | Module |
| Interconnect | Gull-wing leads | Solder balls | Edge connector | Compression lands |
| Typical pitch | 0.5 mm lead | 0.8 mm ball (DDR5) | Edge fingers | 1.0 × 1.38 mm |
| Contacts | 44–66 leads | 78–96 balls | 204–288 pins | 644 pins (LPCAMM2) |
| Profile | ~1 mm | <1 mm | Vertical / edge | Low, flat |
| Field-replaceable | No (soldered) | No (soldered) | Yes | Yes |
| Best for | Flash, slow SDRAM | High-speed DDR/LPDDR | Desktop/server RAM | Thin, low-power laptops |
| Rework | Iron-friendly | BGA station | Toolless / screws | Retention plate |
| Governing spec | JEDEC outlines | JEDEC MO-210 | JEDEC module std. | JEDEC JESD318 |
How to choose: a memory package decision path
Work top-down from the system constraint, not from habit:
- Embedded, space-constrained, highest signal integrity, no service need → solder the die down as FBGA (memory-down), or stack LPDDR as PoP on the SoC.
- Desktop or server, must be field-replaceable and scalable → DIMM: UDIMM for mainstream, RDIMM/LRDIMM when capacity and RAS matter.
- Thin laptop or handheld, want low power and high bandwidth and serviceability → LGA-based LPCAMM2; fall back to SODIMM where the ecosystem or budget demands it.
- Flash storage, low-speed logic, or hand-rework/repair workflow → TSOP for parallel NAND/NOR and EEPROM; small managed NAND (eMMC/UFS) uses BGA.
Design, handling, and sourcing gotchas
Moisture sensitivity. Fine-pitch BGA memory is typically MSL 3, meaning 168 hours of floor life at 30 °C / 60% RH before reflow. Blow that window and trapped moisture flashes to steam during reflow, cracking the package — the “popcorn” failure. The fix per J-STD-033 is a bake, commonly 125 °C for 24 hours, with a 260 °C peak Pb-free reflow for bodies under 2.5 mm. Worked example: a reel of MSL 3 DDR5 FBGA left open on the line for nine days at ambient is past floor life; bake it before the paste hits the oven, or expect intermittent field failures months later.
Counterfeit and remarking. TSOP flash is a favorite target for remarking because the flat top is easy to sand and re-laser; BGA parts get re-balled. Verify date and lot codes, X-ray suspect BGAs for re-ball tells, and buy through authorized distribution.
Second-sourcing. A drop-in replacement must match density, organization (×8 vs ×16 changes the module ballout), speed bin, package outline, and die revision. Two 16-gigabit DDR5 chips at the same data rate are not interchangeable if one is ×8 and the other ×16. DDR5 also pushes single-die density far higher than DDR4 — up to 64 Gb per die versus DDR4’s 16 Gb ceiling — so verify the density map before you assume a swap.
Frequently asked questions
Is FBGA better than TSOP?
For high-speed DRAM, yes. FBGA’s short balls cut inductance and improve signal integrity, which is why DDR high-speed parts left TSOP. TSOP remains better only where exposed leads help — flash storage, low-speed logic, and easy hand-rework or data recovery.
What is the difference between DIMM and SODIMM?
Both are edge-connector modules; SODIMM is the shorter version for laptops and compact systems. A DDR5 desktop DIMM has 288 pins, while the DDR5 SODIMM has 262. They are not cross-compatible, and the sockets differ.
Is CAMM2 replacing SODIMM?
Gradually, in thin and low-power laptops. LPCAMM2 offers more bandwidth, much lower power, and a smaller footprint than SODIMM while staying replaceable. SODIMM remains cheaper and ubiquitous, so both will coexist for years.
What is a VFBGA package?
Very-fine-pitch Ball Grid Array — an FBGA with especially tight ball spacing. DDR5 SDRAM uses a 78-ball VFBGA at 0.8 mm pitch, letting a full DRAM I/O fit under a package only millimeters across.
Can you replace a single memory chip on a module?
Technically yes, but only with an identical part — same density, organization, speed bin, package, and revision — and a BGA rework station. In practice it is rarely economical versus replacing the whole module.
Bottom line
Specify by tier first. If the memory is soldered and speed-critical, you are choosing a chip package — FBGA for fast DDR/LPDDR, TSOP for flash and slow logic. If it must be serviceable, you are choosing a module — DIMM for desktops and servers, and increasingly LGA-based LPCAMM2 where thin, low-power, high-bandwidth laptops need both performance and replaceability. Match density, organization, and revision on any second-source, respect the MSL floor life on every BGA reel, and the package will never be the thing that fails your board.
