A PQFP package is a plastic quad flat package: a leadframe-based surface-mount IC package with gull-wing leads on all four sides, a molded body 2.0 mm to 4.1 mm tall, and lead pitches from 1.0 mm down to 0.5 mm. This guide gives the numbers you need at the bench: the correct JEDEC outline for each lead count, measured thermal resistance, land-pattern dimensions, and the reflow peak temperature the body size forces on you.
Key takeaways
- The 208- and 240-lead outlines are registered under JEDEC MS-029, not MS-022. MS-022 covers 1.0, 0.8 and 0.65 mm pitch only.
- Lead coplanarity tightens from 0.10 mm at 0.65 mm pitch to 0.08 mm at 0.5 mm pitch. Placement accuracy and paste volume have to hold that.
- A 28 mm × 28 mm × 3.4 mm body classifies at 245 °C peak reflow, not 260 °C, under IPC/JEDEC J-STD-020 Table 4-2.
- Junction-to-ambient resistance is roughly 30 °C/W in still air for a 208-lead part. A heat-slug version of the same outline reaches about 18 °C/W on the identical land pattern.
- Most 208-lead PQFP FPGAs and CPLDs are now obsolete at franchised distributors. Treat the PQFP package as a maintenance format, not a new-design default.
What is a PQFP package?
A PQFP (plastic quad flat package) is a surface-mount integrated circuit package with gull-wing leads on all four sides of a molded epoxy body. Lead counts run from 44 to 240, pitches from 1.0 mm to 0.5 mm, and body height from about 2.0 mm to 4.1 mm.
Construction is deliberately ordinary. A copper-alloy leadframe carries the die, which is attached with conductive epoxy and wired out with gold or copper bonds, then the whole assembly is encapsulated in epoxy mold compound. Xilinx specified EFTEC-64 or C7025 copper leadframe with an 85/15 Sn/Pb finish of 300 microinches minimum on its PQ-series parts. Nothing in that stack is exotic, which is exactly why the failure modes are so thoroughly characterized after thirty years of volume production.
The leads are the point. Every joint stays visible after reflow, so a technician can inspect it under a microscope, probe it with a scope, and reflow one lead with an iron. No area-array package gives you that.
[IMAGE 1: labeled cross-section of a PQFP package showing leadframe, die attach, wire bond, mold compound and gull-wing lead form | alt: “Cross-section of a PQFP package (plastic quad flat package) showing leadframe, wire bonds and gull-wing leads”]
PQFP, LQFP and TQFP are height classes, not different technologies
The prefix letter encodes a mounted-height band. JEITA redefined the QFP family by body thickness rather than by construction, so the same die, leadframe and pitch can ship in three different names.
| Designation | Mounted height band | Where you see it |
| QFP / PQFP | Body 2.0 mm to 3.8 mm; overall up to 4.10 mm | Legacy high-pin-count logic, FPGAs, CPLDs |
| LQFP | 1.20 mm < L ≤ 1.70 mm (1.4 mm body) | Current-generation MCUs and interface ICs |
| TQFP | 1.00 mm < T ≤ 1.20 mm (1.0 mm body) | Height-constrained industrial boards |
| VQFP | 0.80 mm < V ≤ 1.00 mm | Portable and handheld products |
| WQFP | 0.65 mm < W ≤ 0.80 mm | Very thin consumer assemblies |
Electrically the variants are interchangeable. Mechanically they are not. Lead length, lead thickness and mold-compound mass all scale with the height class, and so does warpage behavior during reflow. A 1.0 mm TQFP body has far less thermal mass above the die than a 3.4 mm PQFP body, which changes both the reflow profile it tolerates and the peak temperature it is classified to.
Lead counts, pitches and the JEDEC outline that actually applies
This is where published summaries go wrong most often. The table below is built from manufacturers’ own package outline drawings rather than from secondary sources.
| Leads | Body (mm) | Overall D × E (mm) | Pitch (mm) | Max height A (mm) | Coplanarity | JEDEC outline | Mass (typ.) |
| 44 | 10.0 × 10.0 | 13.90 nom | 0.80 | 2.35 | not stated | MO-112 AA-2 | not stated |
| 100 | 14.0 × 20.0 | 17.20 × 23.20 | 0.65 | 3.40 | 0.10 mm | MS-022 GC-1 | 1.9 g |
| 160 | 28.0 × 28.0 | 31.20 × 31.20 | 0.65 | 4.10 | 0.10 mm | MS-022 DD-1 | 6.2 g |
| 208 | 28.0 × 28.0 | 30.60 × 30.60 | 0.50 | 4.10 | 0.08 mm | MS-029 FA-1 | 6.3 g |
| 240 | 32.0 × 32.0 | 34.60 × 34.60 | 0.50 | 4.10 | 0.08 mm | MS-029 GA | 8.0 g |
Source: 44-lead row from the Microchip 44-lead PQFP outline (JEDEC MO-112 Variation AA-2, Issue B, September 1995); all other rows from the Altera Package Information Datasheet for Mature Altera Devices, DS-PKG-16.8, December 2011.
Two corrections worth making before you commit a footprint. Republished tables often list the 208-lead outline as “MO-208” and the 240-lead as “MS-022”. Altera registers both under MS-029, and JEDEC’s own Publication 95 master index defines MS-022 as the metric plastic quad flat pack family for 1.0, 0.8 and 0.65 mm pitch only, with MS-029 covering the fine-pitch 2.6 mm footprint family. A 0.5 mm-pitch part cannot sit under MS-022.
The same physical outline can also carry more than one registration. Xilinx listed its PQ208 and PQ240 against MO-143 FA1 and MO-143 GA, and its PQ100 and PQ160 against MO-108 CC1 and DD1, for parts with the same body sizes Altera registered under MS-029 and MS-022. Neither vendor is wrong. Register your land pattern against the outline printed in the specific datasheet revision you are buying to, not against any summary table, including this one.
When a PQFP package is the right call
The decision is almost never about electrical performance. It is about who has to inspect, rework and service the board, and how much outline area you can spend.
Run the area numbers before you argue about anything else. A 240-lead PQFP package needs 34.60 mm × 34.60 mm of board outline, about 1,197 mm², for 240 connections. A 484-ball FineLine BGA on 1.0 mm pitch occupies 23.00 mm × 23.00 mm, about 529 mm², for twice the I/O. That is a 4.5× difference in connections per square millimeter, and it is the reason perimeter packages stopped scaling.
| Choose a PQFP package when | Choose something else when |
| Field service or depot repair reflows individual leads | Board height budget is under 2 mm |
| Inspection is visual or AOI only, with no X-ray | Sustained dissipation exceeds about 2 W in still air |
| You are maintaining or second-sourcing an existing design | You are routing DDR3 or multi-gigabit serial links |
| Pin count is 240 or below and outline area is available | Outline area or layer count is the binding constraint |
| Prototype volumes are hand-assembled | The design is new and expected to ship past 2030 |
One nuance that rarely appears in comparisons: lead compliance. Gull-wing leads flex, so they absorb board flex and CTE mismatch that would load a solder ball directly. On a large, thick, vibration-exposed assembly this is a genuine reliability argument for the PQFP package, not nostalgia.
Thermal resistance is the number that decides the package
Plastic mold compound is an insulator. Almost all heat leaves a PQFP package through the leads into board copper, which makes junction-to-ambient resistance a property of your layout as much as of the part. Measured values, from vendor characterization to the JEDEC JESD51 series, look like this.
| Device and package | θJC (°C/W) | θJA still air | θJA 100 ft/min | θJA 200 ft/min | θJA 400 ft/min |
| EP2C5, 208-lead PQFP | 5.5 | 30.4 | 29.2 | 27.3 | 22.3 |
| EPM7256S, 208-lead PQFP | 5.0 | 30.0 | 29.0 | 26.0 | 21.0 |
| EPM7256S, 208-lead RQFP (heat slug) | 1.0 | 18.0 | 17.0 | 16.0 | 15.0 |
| EP2C20, 240-lead PQFP | 4.2 | 26.6 | 24.0 | 21.4 | 17.4 |
| EP20K200E, 240-lead PQFP | 3.0 | 22.0 | 19.0 | 18.0 | 16.0 |
Source: Altera Package Information Datasheet for Mature Altera Devices, December 2011, thermal resistance tables 29, 32 and 37.
Worked example: does 2.5 W fit in a 240-lead package?
Take a Xilinx XC4013E in a PQ240, rated at 2.50 W in a specific design, in an enclosure at 55 °C ambient, with a junction temperature target below 100 °C. Xilinx published θJA of 23.7 °C/W in still air for that combination on a two-layer board with no internal planes.
Still air: TJ = 55 + (23.7 × 2.50) = 114.25 °C. That misses the target.
With 250 ft/min forced air, θJA falls to 17.5 °C/W: TJ = 55 + (17.5 × 2.50) = 98.75 °C. That passes, but with 1.25 °C of margin, which is no margin at all.
Swap to the heat-slug HQ240 at 12.5 °C/W: TJ = 55 + (12.5 × 2.50) = 86.25 °C, in still air.
The reason that last option matters: Xilinx confirmed the HQ series conforms to the same JEDEC drawings as the PQ series and uses the same PCB land patterns, with the heatsink oriented down at 240 pins and below to preserve pin-to-pin compatibility. You can roughly halve θJA without touching the footprint. Check your specific vendor before assuming it, but where a slug variant exists it is the cheapest thermal fix available.
[IMAGE 2: heat-flow diagram comparing a standard PQFP package against a heat-slug variant on identical land patterns | alt: “Heat flow through a standard PQFP package leads versus a heat-slug variant on the same footprint”]
Land pattern and stencil: the numbers that survive production
Most defects blamed on the package originate in the land pattern. Two verified reference points, one per pitch class:
- 0.50 mm pitch, 208 and 240 leads: Xilinx published an EIA standard soldered-pad layout with pad width 0.30 mm to 0.40 mm, pad length 1.60 mm, and an inner-to-inner span of 28.20 mm for PQ208 and 32.20 mm for PQ240.
- 0.65 mm pitch, 100 leads: the Microchip recommended land pattern for the 100-lead metric PQFP, 20 mm × 14 mm body, calls for contact pads 1.90 mm long by 0.45 mm wide on 0.65 mm pitch, with 23.00 mm contact pad spacing.
Note what the 0.65 mm case implies. A 0.45 mm pad on 0.65 mm pitch leaves a 0.20 mm gap between adjacent copper. That gap is your entire solder-mask dam budget, and it is the reason a mask-defined dam that a fabricator cannot hold at 0.20 mm turns into bridging on the first build. Confirm the dam width against your fabricator’s minimum before you release.
IPC-7351B gives three land-pattern density levels for gull-wing devices: Most material condition (Level A) for hand soldering and rework, Nominal (Level B) as the production default, and Least (Level C) for high-density work. Four-sided gull-wing attachment specifically falls under IPC-7355. For a package chosen because it is reworkable, Level A is usually the coherent choice, since selecting the smallest pads on a part you picked for serviceability works against the reason you picked it.
Four footprint mistakes that generate returns
- Reusing one library footprint across pitches. A pattern that works at 0.80 mm bridges at 0.50 mm.
- Deriving pad width from the body size rather than from the datasheet lead width b, which is 0.17 mm to 0.27 mm on 0.5 mm-pitch parts and 0.22 mm to 0.40 mm on 0.65 mm-pitch parts.
- Ignoring the coplanarity spec. At 0.08 mm, a lead sitting high produces an open that passes visual inspection and fails after thermal cycling.
- Copying stencil apertures 1:1 from pad geometry on fine pitch, which deposits enough paste volume to bridge before the flux has anywhere to go.
MSL, reflow classification and the 245 °C trap
Every plastic package absorbs moisture, and PQFP bodies are large. The classification consequence is specific and frequently missed.
Compute the body volume: 28 mm × 28 mm × 3.4 mm = 2,666 mm³. IPC/JEDEC J-STD-020 Table 4-2 assigns a Pb-free classification temperature of 245 °C to any package with thickness at or above 2.5 mm and volume above 2,000 mm³. A 14 mm × 14 mm × 1.4 mm LQFP, by contrast, comes to 274 mm³ and classifies at 260 °C.
So a board carrying both parts is constrained by the lower number. Profile the PQFP body, not the small parts, and hold peak package body temperature at or below 245 °C unless the specific datasheet says otherwise. Running a 260 °C profile because the LQFPs tolerate it is how large bodies delaminate.
For recovery after floor-life expiry, Xilinx documented two equivalent bake schedules: 24 hours at 125 °C in air, in shipping media rated for that temperature, or 192 hours at 40 °C in an atmosphere at or below 5 percent relative humidity. Sealed moisture barrier bags carry a 12-month expiry from the seal date, and the humidity indicator card threshold is 20 percent on opening. Floor life is cumulative across every period the bag has been open.
Sourcing a PQFP package in 2026
Lifecycle status is now the dominant sourcing risk. DigiKey lists the XC2S200-5PQ208I and XC2S200-6PQ208C, both 208-PQFP 28 mm × 28 mm parts, as obsolete and no longer manufactured. The pattern repeats across Spartan-II, Spartan-3 and the older MAX CPLD families. Franchised stock on 208-lead perimeter parts is thin and shrinking.
That pushes buyers toward the open market, which is precisely where remarked parts live. Large-body plastic packages are attractive counterfeit targets because the mold surface takes a blacktop coating well. SAE AS6081 is the distributor-facing standard for avoidance and detection, and IDEA-STD-1010 is the working visual-inspection standard at most independent-distributor benches. Inspection checks date-code consistency, mold-compound texture, solvent reactivity of the top surface, ghost markings, lead-finish integrity under magnification, and pin coplanarity.
Two package-specific checks matter more than the generic advice. First, factory-trimmed copper leads show exposed copper at the cut face; replated pull-outs do not. Second, leads are formed after plating at the factory, leaving visible stress marks at the bend, which replating covers. On a 208-lead part you have 208 opportunities to spot either.
If you are buying to a build, check the shipping format too. Xilinx shipped 160-pin QFPs in 44 mm carrier tape at 40 mm pitch, 200 devices per 13-inch reel, with pedestals to protect the leads; 100-pin parts ran 32 mm pitch at 250 per reel. Anything arriving loose in a tube or a tray with mismatched date codes deserves a closer look.
[IMAGE 3: side-by-side macro photo of an authentic PQFP lead bend versus a replated pull-out | alt: “Authentic versus replated leads on a plastic quad flat package under magnification”]
Frequently asked questions
What does PQFP stand for?
PQFP stands for plastic quad flat package, sometimes written plastic quad flat pack. “Quad” refers to leads on all four sides, “flat” to the low-profile molded body, and “plastic” to the epoxy mold compound, which distinguishes it from ceramic CQFP variants used in high-reliability and military parts.
What is the difference between PQFP and LQFP?
Height. LQFP is defined by a mounted height above 1.20 mm and at or below 1.70 mm, typically a 1.4 mm body, while PQFP bodies run 2.0 mm to 3.8 mm with overall height up to 4.10 mm. Pinout and electrical behavior can be identical, but the land patterns and reflow classifications differ, so they are not drop-in swaps.
Is PQFP the same as QFP?
PQFP is a plastic-bodied member of the QFP family. QFP is the umbrella term covering LQFP, TQFP, VQFP, CQFP and others. In practice, engineers use PQFP for standard-profile plastic parts with 0.5 mm to 1.0 mm pitch, particularly the 100 to 240-lead FPGA and CPLD packages.
Are PQFP packages moisture sensitive?
Yes. They are non-hermetic plastic packages, so they carry a moisture sensitivity level printed on the moisture barrier bag and require dry storage, floor-life tracking and bake-out after expiry. Large bodies also classify at a lower peak reflow temperature, commonly 245 °C rather than 260 °C, which constrains the whole board profile.
Can you hand-solder a PQFP package?
Yes, and that is a real reason to choose one. Drag soldering a 0.5 mm-pitch 208-lead part with flux and braid is routine bench work, and individual leads can be reflowed without disturbing neighbors. Use IPC-7351B Level A land patterns if hand assembly or depot rework is part of the plan.
What to do next
For a new design, specify LQFP or BGA and keep the PQFP package out of the bill of materials. The area penalty is 4.5× against a 1.0 mm BGA, franchised supply on the large perimeter outlines is disappearing, and nothing about the format helps a modern interface.
For a maintenance build or a second source on an existing board, the PQFP package is still the right answer, with three conditions. Verify the exact JEDEC outline and variation in the datasheet revision you are buying to, not from a summary table. Hold the reflow profile at or below 245 °C for any body over 2.5 mm thick and 2,000 mm³. Buy through the franchised channel where stock exists, and where it does not, require AS6081-level inspection with documented provenance before the parts reach your line.
And if the thermal budget is tight, check whether a heat-slug variant of the same outline exists before you redesign. Halving θJA on an unchanged land pattern is the least expensive fix on the table.
External references: Altera Package Information Datasheet for Mature Altera Devices (https://www.mouser.com/datasheet/2/612/pkgds-1299398.pdf); Xilinx PQFP (PQ208/PQG208) package drawing PK007 v1.2 (https://sigma.octopart.com/138898769/technical_drawing/Xilinx-XCS30-3PQ208I.pdf); JEDEC MS-022-B, Metric Plastic Quad Flat Pack (https://www.jedec.org/standards-documents/docs/ms-022-b); JEDEC MS-029, Fine Pitch Plastic Quad Flat Package Outline (https://www.jedec.org/standards-documents/docs/ms-029); IPC/JEDEC J-STD-020E (https://ez.analog.com/cfs-file/__key/communityserver-wikis-components-files/00-00-00-01-14/J_2D00_STD_2D00_020E.PDF); SAE AS6081 (https://www.sae.org/standards/as6081-fraudulent-counterfeit-electronic-parts-avoidance-detection-mitigation-disposition-distributors).
Internal links: [INTERNAL LINK: Xilinx FPGA series list and pricing → https://fpga.io/xilinx-fpga/]; [INTERNAL LINK: FPGA brands and manufacturers guide → https://fpga.io/fpga-brand/]; [INTERNAL LINK: Gowin FPGA package and series guide → https://fpga.io/gowin-fpga/]; [INTERNAL LINK: Efinix FPGA sourcing and package trade-offs → https://fpga.io/efinix-fpga/].
